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head/sys/x86/include/specialreg.h

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/* /*
* Important bits in the Thermal and Power Management flags * Important bits in the Thermal and Power Management flags
* CPUID.6 EAX and ECX. * CPUID.6 EAX and ECX.
*/ */
#define CPUTPM1_SENSOR 0x00000001 #define CPUTPM1_SENSOR 0x00000001
#define CPUTPM1_TURBO 0x00000002 #define CPUTPM1_TURBO 0x00000002
#define CPUTPM1_ARAT 0x00000004 #define CPUTPM1_ARAT 0x00000004
#define CPUTPM1_HWP 0x00000080
#define CPUTPM1_HWP_NOTIFICATION 0x00000100
#define CPUTPM1_HWP_ACTIVITY_WINDOW 0x00000200
#define CPUTPM1_HWP_PERF_PREF 0x00000400
#define CPUTPM1_HWP_PKG 0x00000800
#define CPUTPM1_HWP_FLEXIBLE 0x00020000
#define CPUTPM2_EFFREQ 0x00000001 #define CPUTPM2_EFFREQ 0x00000001
/* Intel Processor Trace CPUID. */ /* Intel Processor Trace CPUID. */
/* Leaf 0 ebx. */ /* Leaf 0 ebx. */
#define CPUPT_CR3 (1 << 0) /* CR3 Filtering Support */ #define CPUPT_CR3 (1 << 0) /* CR3 Filtering Support */
#define CPUPT_PSB (1 << 1) /* Configurable PSB and Cycle-Accurate Mode Supported */ #define CPUPT_PSB (1 << 1) /* Configurable PSB and Cycle-Accurate Mode Supported */
#define CPUPT_IPF (1 << 2) /* IP Filtering and TraceStop supported */ #define CPUPT_IPF (1 << 2) /* IP Filtering and TraceStop supported */
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#define MSR_MC4_STATUS 0x411 #define MSR_MC4_STATUS 0x411
#define MSR_MC4_ADDR 0x412 #define MSR_MC4_ADDR 0x412
#define MSR_MC4_MISC 0x413 #define MSR_MC4_MISC 0x413
#define MSR_RAPL_POWER_UNIT 0x606 #define MSR_RAPL_POWER_UNIT 0x606
#define MSR_PKG_ENERGY_STATUS 0x611 #define MSR_PKG_ENERGY_STATUS 0x611
#define MSR_DRAM_ENERGY_STATUS 0x619 #define MSR_DRAM_ENERGY_STATUS 0x619
#define MSR_PP0_ENERGY_STATUS 0x639 #define MSR_PP0_ENERGY_STATUS 0x639
#define MSR_PP1_ENERGY_STATUS 0x641 #define MSR_PP1_ENERGY_STATUS 0x641
#define MSR_PPERF 0x64e
#define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */ #define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */
#define MSR_IA32_PM_ENABLE 0x770
#define MSR_IA32_HWP_CAPABILITIES 0x771
#define MSR_IA32_HWP_REQUEST_PKG 0x772
#define MSR_IA32_HWP_INTERRUPT 0x773
#define MSR_IA32_HWP_REQUEST 0x774
#define MSR_IA32_HWP_STATUS 0x777
/* /*
* VMX MSRs * VMX MSRs
*/ */
#define MSR_VMX_BASIC 0x480 #define MSR_VMX_BASIC 0x480
#define MSR_VMX_PINBASED_CTLS 0x481 #define MSR_VMX_PINBASED_CTLS 0x481
#define MSR_VMX_PROCBASED_CTLS 0x482 #define MSR_VMX_PROCBASED_CTLS 0x482
#define MSR_VMX_EXIT_CTLS 0x483 #define MSR_VMX_EXIT_CTLS 0x483
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#define IA32_SPEC_CTRL_STIBP 0x00000002 #define IA32_SPEC_CTRL_STIBP 0x00000002
#define IA32_SPEC_CTRL_SSBD 0x00000004 #define IA32_SPEC_CTRL_SSBD 0x00000004
/* MSR IA32_PRED_CMD */ /* MSR IA32_PRED_CMD */
#define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL #define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL
/* MSR IA32_FLUSH_CMD */ /* MSR IA32_FLUSH_CMD */
#define IA32_FLUSH_CMD_L1D 0x00000001 #define IA32_FLUSH_CMD_L1D 0x00000001
/* MSR IA32_HWP_CAPABILITIES */
#define IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x) (((x) >> 0) & 0xff)
#define IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(x) (((x) >> 8) & 0xff)
#define IA32_HWP_CAPABILITIES_EFFICIENT_PERFORMANCE(x) (((x) >> 16) & 0xff)
#define IA32_HWP_CAPABILITIES_LOWEST_PERFORMANCE(x) (((x) >> 24) & 0xff)
/* MSR IA32_HWP_REQUEST */
#define IA32_HWP_REQUEST_MINIMUM_VALID (1ULL << 63)
#define IA32_HWP_REQUEST_MAXIMUM_VALID (1ULL << 62)
#define IA32_HWP_REQUEST_DESIRED_VALID (1ULL << 61)
#define IA32_HWP_REQUEST_EPP_VALID (1ULL << 60)
#define IA32_HWP_REQUEST_ACTIVITY_WINDOW_VALID (1ULL << 59)
#define IA32_HWP_REQUEST_PACKAGE_CONTROL (1ULL << 42)
#define IA32_HWP_ACTIVITY_WINDOW (0x3ffULL << 32)
#define IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE (0xffULL << 24)
#define IA32_HWP_DESIRED_PERFORMANCE (0xffULL << 16)
#define IA32_HWP_REQUEST_MAXIMUM_PERFORMANCE (0xffULL << 8)
#define IA32_HWP_MINIMUM_PERFORMANCE (0xffULL << 0)
/* /*
* PAT modes. * PAT modes.
*/ */
#define PAT_UNCACHEABLE 0x00 #define PAT_UNCACHEABLE 0x00
#define PAT_WRITE_COMBINING 0x01 #define PAT_WRITE_COMBINING 0x01
#define PAT_WRITE_THROUGH 0x04 #define PAT_WRITE_THROUGH 0x04
#define PAT_WRITE_PROTECTED 0x05 #define PAT_WRITE_PROTECTED 0x05
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