Differential D17791 Diff 50586 head/sys/dev/pci/pci_host_generic_acpi.c

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head/sys/dev/pci/pci_host_generic_acpi.c

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#include <dev/pci/pcib_private.h>		#include <dev/pci/pcib_private.h>
#include <dev/pci/pci_host_generic.h>		#include <dev/pci/pci_host_generic.h>

#include <machine/cpu.h>		#include <machine/cpu.h>
#include <machine/bus.h>		#include <machine/bus.h>
#include <machine/intr.h>		#include <machine/intr.h>

#include "pcib_if.h"		#include "pcib_if.h"
		#include "acpi_bus_if.h"

int pci_host_generic_acpi_attach(device_t);

/* Assembling ECAM Configuration Address */		/* Assembling ECAM Configuration Address */
#define PCIE_BUS_SHIFT 20		#define PCIE_BUS_SHIFT 20
#define PCIE_SLOT_SHIFT 15		#define PCIE_SLOT_SHIFT 15
#define PCIE_FUNC_SHIFT 12		#define PCIE_FUNC_SHIFT 12
#define PCIE_BUS_MASK 0xFF		#define PCIE_BUS_MASK 0xFF
#define PCIE_SLOT_MASK 0x1F		#define PCIE_SLOT_MASK 0x1F
#define PCIE_FUNC_MASK 0x07		#define PCIE_FUNC_MASK 0x07
#define PCIE_REG_MASK 0xFFF		#define PCIE_REG_MASK 0xFFF
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};		};

/* Forward prototypes */		/* Forward prototypes */

static int generic_pcie_acpi_probe(device_t dev);		static int generic_pcie_acpi_probe(device_t dev);
static ACPI_STATUS pci_host_generic_acpi_parse_resource(ACPI_RESOURCE , void );		static ACPI_STATUS pci_host_generic_acpi_parse_resource(ACPI_RESOURCE , void );
static int generic_pcie_acpi_read_ivar(device_t, device_t, int, uintptr_t *);		static int generic_pcie_acpi_read_ivar(device_t, device_t, int, uintptr_t *);

		/*
		* generic_pcie_acpi_probe - look for root bridge flag
		*/
static int		static int
generic_pcie_acpi_probe(device_t dev)		generic_pcie_acpi_probe(device_t dev)
{		{
ACPI_DEVICE_INFO *devinfo;		ACPI_DEVICE_INFO *devinfo;
ACPI_HANDLE h;		ACPI_HANDLE h;
int root;		int root;

if (acpi_disabled("pcib") \|\| (h = acpi_get_handle(dev)) == NULL \|\|		if (acpi_disabled("pcib") \|\| (h = acpi_get_handle(dev)) == NULL \|\|
ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo)))		ACPI_FAILURE(AcpiGetObjectInfo(h, &devinfo)))
return (ENXIO);		return (ENXIO);
root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0;		root = (devinfo->Flags & ACPI_PCI_ROOT_BRIDGE) != 0;
AcpiOsFree(devinfo);		AcpiOsFree(devinfo);
if (!root)		if (!root)
return (ENXIO);		return (ENXIO);

device_set_desc(dev, "Generic PCI host controller");		device_set_desc(dev, "Generic PCI host controller");
return (BUS_PROBE_GENERIC);		return (BUS_PROBE_GENERIC);
}		}

int		/*
pci_host_generic_acpi_attach(device_t dev)		* pci_host_generic_acpi_parse_resource - parse PCI memory, IO and bus spaces
		* 'produced' by this bridge
		*/
		static ACPI_STATUS
		pci_host_generic_acpi_parse_resource(ACPI_RESOURCE res, void arg)
{		{
		device_t dev = (device_t)arg;
struct generic_pcie_acpi_softc *sc;		struct generic_pcie_acpi_softc *sc;
		struct rman *rm;
		rman_res_t min, max, off;
		int r;

		rm = NULL;
		sc = device_get_softc(dev);
		r = sc->base.nranges;
		switch (res->Type) {
		case ACPI_RESOURCE_TYPE_ADDRESS16:
		min = res->Data.Address16.Address.Minimum;
		max = res->Data.Address16.Address.Maximum;
		break;
		case ACPI_RESOURCE_TYPE_ADDRESS32:
		min = res->Data.Address32.Address.Minimum;
		max = res->Data.Address32.Address.Maximum;
		off = res->Data.Address32.Address.TranslationOffset;
		break;
		case ACPI_RESOURCE_TYPE_ADDRESS64:
		if (res->Data.Address.ResourceType != ACPI_MEMORY_RANGE)
		break;
		min = res->Data.Address64.Address.Minimum;
		max = res->Data.Address64.Address.Maximum;
		off = res->Data.Address64.Address.TranslationOffset;
		break;
		default:
		return (AE_OK);
		}

		/* Save detected ranges */
		if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE \|\|
		res->Data.Address.ResourceType == ACPI_IO_RANGE) {
		sc->base.ranges[r].pci_base = min;
		sc->base.ranges[r].phys_base = min + off;
		sc->base.ranges[r].size = max - min + 1;
		if (res->Data.Address.ResourceType == ACPI_MEMORY_RANGE)
		sc->base.ranges[r].flags \|= FLAG_MEM;
		else if (res->Data.Address.ResourceType == ACPI_IO_RANGE)
		sc->base.ranges[r].flags \|= FLAG_IO;
		sc->base.nranges++;
		} else if (res->Data.Address.ResourceType == ACPI_BUS_NUMBER_RANGE) {
		sc->base.bus_start = min;
		sc->base.bus_end = max;
		}
		return (AE_OK);
		}

		static int
		pci_host_acpi_get_ecam_resource(device_t dev)
		{
		struct generic_pcie_acpi_softc *sc;
		struct acpi_device *ad;
		struct resource_list *rl;
		ACPI_TABLE_HEADER *hdr;
		ACPI_MCFG_ALLOCATION mcfg_entry, mcfg_end;
ACPI_HANDLE handle;		ACPI_HANDLE handle;
ACPI_STATUS status;		ACPI_STATUS status;
int error, bus_start;		rman_res_t base, start, end;
		int found, val;

sc = device_get_softc(dev);		sc = device_get_softc(dev);

handle = acpi_get_handle(dev);		handle = acpi_get_handle(dev);
if (ACPI_FAILURE(acpi_GetInteger(handle, "_CCA", &sc->base.coherent)))
sc->base.coherent = 0;
if (bootverbose)
device_printf(dev, "Bus is%s cache-coherent\n",
sc->base.coherent ? "" : " not");

if (!ACPI_FAILURE(acpi_GetInteger(handle, "_BBN", &bus_start))) {		/* Try MCFG first */
sc->base.ecam = bus_start >> 7;		status = AcpiGetTable(ACPI_SIG_MCFG, 1, &hdr);
sc->base.bus_start = bus_start & 0x7F;		if (ACPI_SUCCESS(status)) {
		found = FALSE;
		mcfg_end = (ACPI_MCFG_ALLOCATION )((char )hdr + hdr->Length);
		mcfg_entry = (ACPI_MCFG_ALLOCATION )((ACPI_TABLE_MCFG )hdr + 1);
		while (mcfg_entry < mcfg_end && !found) {
		if (mcfg_entry->PciSegment == sc->base.ecam &&
		mcfg_entry->StartBusNumber <= sc->base.bus_start &&
		mcfg_entry->EndBusNumber >= sc->base.bus_start)
		found = TRUE;
		else
		mcfg_entry++;
		}
		if (found) {
		if (mcfg_entry->EndBusNumber < sc->base.bus_end) {
		device_printf(dev, "bus end mismatch! expected %d found %d.\n",
		sc->base.bus_end, (int)mcfg_entry->EndBusNumber);
		sc->base.bus_end = mcfg_entry->EndBusNumber;
		}
		base = mcfg_entry->Address;
} else {		} else {
sc->base.ecam = 0;		device_printf(dev, "MCFG exists, but does not have bus %d-%d\n",
sc->base.bus_start = 0;		sc->base.bus_start, sc->base.bus_end);
		return (ENXIO);
}		}
sc->base.bus_end = 0xFF;		} else {
		status = acpi_GetInteger(handle, "_CBA", &val);
acpi_pcib_fetch_prt(dev, &sc->ap_prt);		if (ACPI_SUCCESS(status))
		base = val;
error = pci_host_generic_core_attach(dev);		else
if (error != 0)
return (error);

status = AcpiWalkResources(handle, "_CRS",
pci_host_generic_acpi_parse_resource, (void *)dev);

if (ACPI_FAILURE(status))
return (ENXIO);		return (ENXIO);
		}

device_add_child(dev, "pci", -1);		/* add as MEM rid 0 */
return (bus_generic_attach(dev));		ad = device_get_ivars(dev);
		rl = &ad->ad_rl;
		start = base + (sc->base.bus_start << PCIE_BUS_SHIFT);
		end = base + ((sc->base.bus_end + 1) << PCIE_BUS_SHIFT) - 1;
		resource_list_add(rl, SYS_RES_MEMORY, 0, start, end, end - start + 1);
		if (bootverbose)
		device_printf(dev, "ECAM for bus %d-%d at mem %jx-%jx\n",
		sc->base.bus_start, sc->base.bus_end, start, end);
		return (0);
}		}

static ACPI_STATUS		static int
pci_host_generic_acpi_parse_resource(ACPI_RESOURCE res, void arg)		pci_host_generic_acpi_attach(device_t dev)
{		{
device_t dev = (device_t)arg;
struct generic_pcie_acpi_softc *sc;		struct generic_pcie_acpi_softc *sc;
rman_res_t min, max;		ACPI_HANDLE handle;
		uint64_t phys_base;
		uint64_t pci_base;
		uint64_t size;
		ACPI_STATUS status;
int error;		int error;
		int tuple;

switch (res->Type) {		sc = device_get_softc(dev);
case ACPI_RESOURCE_TYPE_ADDRESS32:		handle = acpi_get_handle(dev);
min = (rman_res_t)res->Data.Address32.Address.Minimum;
max = (rman_res_t)res->Data.Address32.Address.Maximum;		/* Get Start bus number for the PCI host bus is from _BBN method */
break;		status = acpi_GetInteger(handle, "_BBN", &sc->base.bus_start);
case ACPI_RESOURCE_TYPE_ADDRESS64:		if (ACPI_FAILURE(status)) {
min = (rman_res_t)res->Data.Address64.Address.Minimum;		device_printf(dev, "No _BBN, using start bus 0\n");
max = (rman_res_t)res->Data.Address64.Address.Maximum;		sc->base.bus_start = 0;
break;
default:
return (AE_OK);
}		}
		sc->base.bus_end = 255;

sc = device_get_softc(dev);		/* Get PCI Segment (domain) needed for MCFG lookup */
		status = acpi_GetInteger(handle, "_SEG", &sc->base.ecam);
		if (ACPI_FAILURE(status)) {
		device_printf(dev, "No _SEG for PCI Bus, using segment 0\n");
		sc->base.ecam = 0;
		}

error = rman_manage_region(&sc->base.mem_rman, min, max);		/* Bus decode ranges */
		status = AcpiWalkResources(handle, "_CRS",
		pci_host_generic_acpi_parse_resource, (void *)dev);
		if (ACPI_FAILURE(status))
		return (ENXIO);

		/* Coherency attribute */
		if (ACPI_FAILURE(acpi_GetInteger(handle, "_CCA", &sc->base.coherent)))
		sc->base.coherent = 0;
		if (bootverbose)
		device_printf(dev, "Bus is%s cache-coherent\n",
		sc->base.coherent ? "" : " not");

		/* add config space resource */
		pci_host_acpi_get_ecam_resource(dev);
		acpi_pcib_fetch_prt(dev, &sc->ap_prt);

		error = pci_host_generic_core_attach(dev);
		if (error != 0)
		return (error);

		for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
		phys_base = sc->base.ranges[tuple].phys_base;
		pci_base = sc->base.ranges[tuple].pci_base;
		size = sc->base.ranges[tuple].size;
		if (phys_base == 0 \|\| size == 0)
		continue; /* empty range element */
		if (sc->base.ranges[tuple].flags & FLAG_MEM) {
		error = rman_manage_region(&sc->base.mem_rman,
		phys_base, phys_base + size - 1);
		} else if (sc->base.ranges[tuple].flags & FLAG_IO) {
		error = rman_manage_region(&sc->base.io_rman,
		pci_base + PCI_IO_WINDOW_OFFSET,
		pci_base + PCI_IO_WINDOW_OFFSET + size - 1);
		} else
		continue;
if (error) {		if (error) {
device_printf(dev, "unable to allocate %lx-%lx range\n", min, max);		device_printf(dev, "rman_manage_region() failed."
return (AE_NOT_FOUND);		"error = %d\n", error);
		rman_fini(&sc->base.mem_rman);
		return (error);
}		}
device_printf(dev, "allocating %lx-%lx range\n", min, max);		}

return (AE_OK);		device_add_child(dev, "pci", -1);
		return (bus_generic_attach(dev));
}		}

static int		static int
generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index,		generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index,
uintptr_t *result)		uintptr_t *result)
{		{
struct generic_pcie_acpi_softc *sc;		struct generic_pcie_acpi_softc *sc;

sc = device_get_softc(dev);		sc = device_get_softc(dev);

if (index == PCIB_IVAR_BUS) {		if (index == PCIB_IVAR_BUS) {
result = sc->base.ecam 0x80 + sc->base.bus_start;		*result = sc->base.bus_start;
return (0);		return (0);
}		}

if (index == PCIB_IVAR_DOMAIN) {		if (index == PCIB_IVAR_DOMAIN) {
*result = sc->base.ecam;		*result = sc->base.ecam;
return (0);		return (0);
}		}

if (bootverbose)		if (bootverbose)
device_printf(dev, "ERROR: Unknown index %d.\n", index);		device_printf(dev, "ERROR: Unknown index %d.\n", index);
return (ENOENT);		return (ENOENT);
}		}

static int		static int
generic_pcie_acpi_route_interrupt(device_t bus, device_t dev, int pin)		generic_pcie_acpi_route_interrupt(device_t bus, device_t dev, int pin)
{		{
struct generic_pcie_acpi_softc *sc;		struct generic_pcie_acpi_softc *sc;

sc = device_get_softc(bus);		sc = device_get_softc(bus);

return (acpi_pcib_route_interrupt(bus, dev, pin, &sc->ap_prt));		return (acpi_pcib_route_interrupt(bus, dev, pin, &sc->ap_prt));
}		}

static struct resource *		/*
pci_host_generic_acpi_alloc_resource(device_t dev, device_t child, int type,		* Follow logic of FDT activate
int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)		*/
{
struct resource *res = NULL;

#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
struct generic_pcie_acpi_softc *sc;

if (type == PCI_RES_BUS) {
sc = device_get_softc(dev);
return (pci_domain_alloc_bus(sc->base.ecam, child, rid, start,
end, count, flags));
}
#endif

if (type == SYS_RES_MEMORY)
res = pci_host_generic_core_alloc_resource(dev, child, type,
rid, start, end, count, flags);

if (res == NULL)
res = bus_generic_alloc_resource(dev, child, type, rid, start, end,
count, flags);

return (res);
}

static int		static int
generic_pcie_acpi_activate_resource(device_t dev, device_t child, int type,		generic_pcie_acpi_activate_resource(device_t dev, device_t child, int type,
int rid, struct resource *r)		int rid, struct resource *r)
{		{
struct generic_pcie_acpi_softc *sc;		struct generic_pcie_acpi_softc *sc;
		uint64_t phys_base;
		uint64_t pci_base;
		uint64_t size;
		int found;
int res;		int res;
		int i;

sc = device_get_softc(dev);		sc = device_get_softc(dev);

if ((res = rman_activate_resource(r)) != 0)		if ((res = rman_activate_resource(r)) != 0)
return (res);		return (res);

res = BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child, type, rid,r);		switch (type) {
		case SYS_RES_IOPORT:
		found = 0;
		for (i = 0; i < MAX_RANGES_TUPLES; i++) {
		pci_base = sc->base.ranges[i].pci_base;
		phys_base = sc->base.ranges[i].phys_base;
		size = sc->base.ranges[i].size;

		if ((rid > pci_base) && (rid < (pci_base + size))) {
		found = 1;
		break;
		}
		}
		if (found) {
		rman_set_start(r, rman_get_start(r) + phys_base);
		rman_set_end(r, rman_get_end(r) + phys_base);
		res = BUS_ACTIVATE_RESOURCE(device_get_parent(dev),
		child, type, rid, r);
		} else {
		device_printf(dev,
		"Failed to activate IOPORT resource\n");
		res = 0;
		}
		break;
		case SYS_RES_MEMORY:
		case SYS_RES_IRQ:
		res = BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child,
		type, rid, r);
		break;
		default:
		break;
		}

return (res);		return (res);
}		}

static int		static int
generic_pcie_acpi_deactivate_resource(device_t dev, device_t child, int type,		generic_pcie_acpi_deactivate_resource(device_t dev, device_t child, int type,
int rid, struct resource *r)		int rid, struct resource *r)
{		{
int res;		int res;

if ((res = rman_deactivate_resource(r)) != 0)		if ((res = rman_deactivate_resource(r)) != 0)
return (res);		return (res);

res = BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child, type,		switch (type) {
rid, r);		case SYS_RES_IOPORT:
		case SYS_RES_MEMORY:
		case SYS_RES_IRQ:
		res = BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child,
		type, rid, r);
		break;
		default:
		break;
		}

return (res);		return (res);
}		}

static int		static int
generic_pcie_acpi_alloc_msi(device_t pci, device_t child, int count,		generic_pcie_acpi_alloc_msi(device_t pci, device_t child, int count,
int maxcount, int *irqs)		int maxcount, int *irqs)
{		{

▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines	#else
return (ENXIO);		return (ENXIO);
#endif		#endif
}		}

static int		static int
generic_pcie_acpi_get_id(device_t pci, device_t child, enum pci_id_type type,		generic_pcie_acpi_get_id(device_t pci, device_t child, enum pci_id_type type,
uintptr_t *id)		uintptr_t *id)
{		{
struct generic_pcie_acpi_softc *sc;
int err;

/* Use the PCI RID to find the MSI ID */		/*
if (type == PCI_ID_MSI) {		* Use the PCI RID to find the MSI ID for now, we support only 1:1
sc = device_get_softc(pci);		* mapping
type = PCI_ID_RID;		*
err = pcib_get_id(pci, child, type, id);		* On aarch64, more complex mapping would come from IORT table
if (err != 0)		*/
return (err);		if (type == PCI_ID_MSI)
*id \|= sc->base.ecam << 16;		return (pcib_get_id(pci, child, PCI_ID_RID, id));
return (0);		else
}

return (pcib_get_id(pci, child, type, id));		return (pcib_get_id(pci, child, type, id));
}		}

static device_method_t generic_pcie_acpi_methods[] = {		static device_method_t generic_pcie_acpi_methods[] = {
DEVMETHOD(device_probe, generic_pcie_acpi_probe),		DEVMETHOD(device_probe, generic_pcie_acpi_probe),
DEVMETHOD(device_attach, pci_host_generic_acpi_attach),		DEVMETHOD(device_attach, pci_host_generic_acpi_attach),
DEVMETHOD(bus_alloc_resource, pci_host_generic_acpi_alloc_resource),		DEVMETHOD(bus_read_ivar, generic_pcie_acpi_read_ivar),
DEVMETHOD(bus_activate_resource, generic_pcie_acpi_activate_resource),		DEVMETHOD(bus_activate_resource, generic_pcie_acpi_activate_resource),
DEVMETHOD(bus_deactivate_resource, generic_pcie_acpi_deactivate_resource),		DEVMETHOD(bus_deactivate_resource,generic_pcie_acpi_deactivate_resource),
DEVMETHOD(bus_read_ivar, generic_pcie_acpi_read_ivar),

/* pcib interface */		/* pcib interface */
DEVMETHOD(pcib_route_interrupt, generic_pcie_acpi_route_interrupt),		DEVMETHOD(pcib_route_interrupt, generic_pcie_acpi_route_interrupt),
DEVMETHOD(pcib_alloc_msi, generic_pcie_acpi_alloc_msi),		DEVMETHOD(pcib_alloc_msi, generic_pcie_acpi_alloc_msi),
DEVMETHOD(pcib_release_msi, generic_pcie_acpi_release_msi),		DEVMETHOD(pcib_release_msi, generic_pcie_acpi_release_msi),
DEVMETHOD(pcib_alloc_msix, generic_pcie_acpi_alloc_msix),		DEVMETHOD(pcib_alloc_msix, generic_pcie_acpi_alloc_msix),
DEVMETHOD(pcib_release_msix, generic_pcie_acpi_release_msix),		DEVMETHOD(pcib_release_msix, generic_pcie_acpi_release_msix),
DEVMETHOD(pcib_map_msi, generic_pcie_acpi_map_msi),		DEVMETHOD(pcib_map_msi, generic_pcie_acpi_map_msi),
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