Differential D3184 Diff 7362 sys/arm64/arm64/gic_v3.c

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sys/arm64/arm64/gic_v3.c

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	#include <sys/cpuset.h>			#include <sys/cpuset.h>
	#include <sys/lock.h>			#include <sys/lock.h>
	#include <sys/mutex.h>			#include <sys/mutex.h>

	#include <vm/vm.h>			#include <vm/vm.h>
	#include <vm/pmap.h>			#include <vm/pmap.h>

	#include <machine/bus.h>			#include <machine/bus.h>
				#include <machine/cpu.h>
	#include <machine/intr.h>			#include <machine/intr.h>

	#include "pic_if.h"			#include "pic_if.h"

	#include "gic_v3_reg.h"			#include "gic_v3_reg.h"
	#include "gic_v3_var.h"			#include "gic_v3_var.h"

	/* Device and PIC methods */			/* Device and PIC methods */
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	* PIC interface.			* PIC interface.
	*/			*/
	static void			static void
	gic_v3_dispatch(device_t dev, struct trapframe *frame)			gic_v3_dispatch(device_t dev, struct trapframe *frame)
	{			{
	uint64_t active_irq;			uint64_t active_irq;

	while (1) {			while (1) {
				if (CPU_MATCH(CPU_IMPL_MASK \| CPU_PART_MASK,
				CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, 0)) {
				/*
				* Hardware: Cavium ThunderX
				* Chip revision: Pass 1.0, Pass 1.1
				impUnsubmitted Not Done Inline Actions So both Pass 1.0 and 1.1 have this errata. Is Cavium really going to market with Pass 1.1? that likely means we'd have to keep this around for a long time. If that's just the first wave and there will be a Pass 2.0 which fixes this, that would be better. imp: So both Pass 1.0 and 1.1 have this errata. Is Cavium really going to market with Pass 1.1? that…
				emasteUnsubmitted Not Done Inline Actions As far as we know right now, yes. emaste: As far as we know right now, yes.
				* ERRATUM: 22978, 23154
				*/
				__asm __volatile("nop;nop;nop;nop;nop;nop;nop;nop;\n"
				"mrs %0, ICC_IAR1_EL1\n"
				"nop;nop;nop;nop;dsb sy;" : "=&r" (active_irq));
				} else {
				andrewUnsubmitted Not Done Inline Actions Quoting https://lkml.org/lkml/2015/7/6/247 If you need an instruction sequence to be consecutive, then it _must_ be one single asm(). I would also like a comment explaining why all the nops are needed, and on what hardware the errata applies to. There have been a few places with other architectures where they needed a collection of nops, but nobody can remember why, or knew if they are still needed. andrew: Quoting https://lkml.org/lkml/2015/7/6/247 If you need an instruction sequence to be…
				wma_semihalf.comAuthorUnsubmitted Not Done Inline Actions Fixed, comments added. Unfortunately, these are the only information than can go public. wma_semihalf.com: Fixed, comments added. Unfortunately, these are the only information than can go public.
				emasteUnsubmitted Not Done Inline Actions Is it possible to expand on the meaning of `Pass 1.0/1.1`? emaste: Is it possible to expand on the meaning of `Pass 1.0/1.1`?
	active_irq = gic_icc_read(IAR1);			active_irq = gic_icc_read(IAR1);
				}

	if (__predict_false(active_irq == ICC_IAR1_EL1_SPUR))			if (__predict_false(active_irq == ICC_IAR1_EL1_SPUR))
	break;			break;

	if (__predict_true((active_irq >= GIC_FIRST_PPI &&			if (__predict_true((active_irq >= GIC_FIRST_PPI &&
	active_irq <= GIC_LAST_SPI) \|\| active_irq >= GIC_FIRST_LPI)) {			active_irq <= GIC_LAST_SPI) \|\| active_irq >= GIC_FIRST_LPI)) {
	arm_dispatch_intr(active_irq, frame);			arm_dispatch_intr(active_irq, frame);
	continue;			continue;
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