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	#define MSR_MC3_ADDR 0x40e			#define MSR_MC3_ADDR 0x40e
	#define MSR_MC3_MISC 0x40f			#define MSR_MC3_MISC 0x40f
	#define MSR_MC4_CTL 0x410			#define MSR_MC4_CTL 0x410
	#define MSR_MC4_STATUS 0x411			#define MSR_MC4_STATUS 0x411
	#define MSR_MC4_ADDR 0x412			#define MSR_MC4_ADDR 0x412
	#define MSR_MC4_MISC 0x413			#define MSR_MC4_MISC 0x413

	/*			/*
				* VMX MSRs
				*/
				#define MSR_VMX_BASIC 0x480
				#define MSR_VMX_PINBASED_CTLS 0x481
				#define MSR_VMX_PROCBASED_CTLS 0x482
				#define MSR_VMX_EXIT_CTLS 0x483
				#define MSR_VMX_ENTRY_CTLS 0x484
				#define MSR_VMX_CR0_FIXED0 0x486
				#define MSR_VMX_CR0_FIXED1 0x487
				#define MSR_VMX_CR4_FIXED0 0x488
				#define MSR_VMX_CR4_FIXED1 0x489
				#define MSR_VMX_PROCBASED_CTLS2 0x48b
				#define MSR_VMX_EPT_VPID_CAP 0x48c
				#define MSR_VMX_TRUE_PINBASED_CTLS 0x48d
				#define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e
				#define MSR_VMX_TRUE_EXIT_CTLS 0x48f
				#define MSR_VMX_TRUE_ENTRY_CTLS 0x490

				/*
	* X2APIC MSRs			* X2APIC MSRs
	*/			*/
	#define MSR_APIC_ID 0x802			#define MSR_APIC_ID 0x802
	#define MSR_APIC_VERSION 0x803			#define MSR_APIC_VERSION 0x803
	#define MSR_APIC_TPR 0x808			#define MSR_APIC_TPR 0x808
	#define MSR_APIC_EOI 0x80b			#define MSR_APIC_EOI 0x80b
	#define MSR_APIC_LDR 0x80d			#define MSR_APIC_LDR 0x80d
	#define MSR_APIC_SVR 0x80f			#define MSR_APIC_SVR 0x80f
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