Differential D17414 Diff 49183 head/sys/riscv/riscv/cpufunc_asm.S

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head/sys/riscv/riscv/cpufunc_asm.S

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	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
	* SUCH DAMAGE.			* SUCH DAMAGE.
	*/			*/

	#include <machine/asm.h>			#include <machine/asm.h>
	#include <machine/param.h>
	__FBSDID("$FreeBSD$");			__FBSDID("$FreeBSD$");

	.text			.text
	.align 2			.align 2

	.Lpage_mask:
	.word PAGE_MASK

	ENTRY(riscv_nullop)			ENTRY(riscv_nullop)
	ret			ret
	END(riscv_nullop)			END(riscv_nullop)

	/*
	* Generic functions to read/modify/write the internal coprocessor registers
	*/

	ENTRY(riscv_tlb_flushID)
	sfence.vma
	ret
	END(riscv_tlb_flushID)

	ENTRY(riscv_tlb_flushID_SE)
	sfence.vma
	ret
	END(riscv_tlb_flushID_SE)

	/*
	* void riscv_dcache_wb_range(vm_offset_t, vm_size_t)
	*/
	ENTRY(riscv_dcache_wb_range)
	sfence.vma
	ret
	END(riscv_dcache_wb_range)

	/*
	* void riscv_dcache_wbinv_range(vm_offset_t, vm_size_t)
	*/
	ENTRY(riscv_dcache_wbinv_range)
	sfence.vma
	ret
	END(riscv_dcache_wbinv_range)

	/*
	* void riscv_dcache_inv_range(vm_offset_t, vm_size_t)
	*/
	ENTRY(riscv_dcache_inv_range)
	sfence.vma
	ret
	END(riscv_dcache_inv_range)

	/*
	* void riscv_idcache_wbinv_range(vm_offset_t, vm_size_t)
	*/
	ENTRY(riscv_idcache_wbinv_range)
	fence.i
	sfence.vma
	ret
	END(riscv_idcache_wbinv_range)

	/*
	* void riscv_icache_sync_range(vm_offset_t, vm_size_t)
	*/
	ENTRY(riscv_icache_sync_range)
	fence.i
	ret
	END(riscv_icache_sync_range)