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Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines	u_int quirks;
SDHCI_QUIRK_PRESET_VALUE_BROKEN },		SDHCI_QUIRK_PRESET_VALUE_BROKEN },
{ "80865ACC", 0, "Intel Apollo Lake eMMC 5.0 Controller",		{ "80865ACC", 0, "Intel Apollo Lake eMMC 5.0 Controller",
SDHCI_QUIRK_BROKEN_DMA \| /* APL18 erratum */		SDHCI_QUIRK_BROKEN_DMA \| /* APL18 erratum */
SDHCI_QUIRK_INTEL_POWER_UP_RESET \|		SDHCI_QUIRK_INTEL_POWER_UP_RESET \|
SDHCI_QUIRK_WAIT_WHILE_BUSY \|		SDHCI_QUIRK_WAIT_WHILE_BUSY \|
SDHCI_QUIRK_MMC_DDR52 \|		SDHCI_QUIRK_MMC_DDR52 \|
SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 \|		SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 \|
SDHCI_QUIRK_PRESET_VALUE_BROKEN },		SDHCI_QUIRK_PRESET_VALUE_BROKEN },
		{ "AMDI0040", 0, "AMD eMMC 5.0 Controller",
		SDHCI_QUIRK_32BIT_DMA_SIZE },
{ NULL, 0, NULL, 0}		{ NULL, 0, NULL, 0}
};		};

static char *sdhci_ids[] = {		static char *sdhci_ids[] = {
"80860F14",		"80860F14",
"80860F16",		"80860F16",
"80865ACA",		"80865ACA",
"80865ACC",		"80865ACC",
		"AMDI0040",
NULL		NULL
};		};

struct sdhci_acpi_softc {		struct sdhci_acpi_softc {
u_int quirks; /* Chip specific quirks */		u_int quirks; /* Chip specific quirks */
struct resource irq_res; / IRQ resource */		struct resource irq_res; / IRQ resource */
void intrhand; / Interrupt handle */		void intrhand; / Interrupt handle */

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