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head/sys/x86/iommu/intel_utils.c
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{ | { | ||||
if (DMAR_IS_COHERENT(unit)) | if (DMAR_IS_COHERENT(unit)) | ||||
return; | return; | ||||
/* | /* | ||||
* If DMAR does not snoop paging structures accesses, flush | * If DMAR does not snoop paging structures accesses, flush | ||||
* CPU cache to memory. | * CPU cache to memory. | ||||
*/ | */ | ||||
pmap_invalidate_cache_range((uintptr_t)dst, (uintptr_t)dst + sz, | pmap_force_invalidate_cache_range((uintptr_t)dst, (uintptr_t)dst + sz); | ||||
TRUE); | |||||
} | } | ||||
void | void | ||||
dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst) | dmar_flush_pte_to_ram(struct dmar_unit *unit, dmar_pte_t *dst) | ||||
{ | { | ||||
dmar_flush_transl_to_ram(unit, dst, sizeof(*dst)); | dmar_flush_transl_to_ram(unit, dst, sizeof(*dst)); | ||||
} | } | ||||
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