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head/lib/clang/libllvm/Makefile

# $FreeBSD$ # $FreeBSD$
.include <src.opts.mk> .include <src.opts.mk>
.include "../llvm.pre.mk" .include "../llvm.pre.mk"
LIB= llvm LIB= llvm
INTERNALLIB= INTERNALLIB=
CFLAGS+= -I${.OBJDIR} CFLAGS+= -I${.OBJDIR}
.if ${MK_LLVM_TARGET_AARCH64} == "no" && ${MK_LLVM_TARGET_ARM} == "no" && \ .if ${MK_LLVM_TARGET_AARCH64} == "no" && ${MK_LLVM_TARGET_ARM} == "no" && \
${MK_LLVM_TARGET_MIPS} == "no" && ${MK_LLVM_TARGET_POWERPC} == "no" && \ ${MK_LLVM_TARGET_BPF} == "no" && ${MK_LLVM_TARGET_MIPS} == "no" && \
${MK_LLVM_TARGET_SPARC} == "no" && ${MK_LLVM_TARGET_X86} == "no" ${MK_LLVM_TARGET_POWERPC} == "no" && ${MK_LLVM_TARGET_SPARC} == "no" && \
${MK_LLVM_TARGET_X86} == "no"
.error Please enable at least one of: MK_LLVM_TARGET_AARCH64,\ .error Please enable at least one of: MK_LLVM_TARGET_AARCH64,\
MK_LLVM_TARGET_ARM, MK_LLVM_TARGET_MIPS, MK_LLVM_TARGET_POWERPC,\ MK_LLVM_TARGET_ARM, MK_LLVM_TARGET_BPF, MK_LLVM_TARGET_MIPS, \
MK_LLVM_TARGET_SPARC, or MK_LLVM_TARGET_X86 MK_LLVM_TARGET_POWERPC, MK_LLVM_TARGET_SPARC, or MK_LLVM_TARGET_X86
.endif .endif
.for arch in AArch64 ARM Mips PowerPC Sparc X86 .for arch in AArch64 ARM BPF Mips PowerPC Sparc X86
. if ${MK_LLVM_TARGET_${arch:tu}} != "no" . if ${MK_LLVM_TARGET_${arch:tu}} != "no"
CFLAGS+= -I${LLVM_SRCS}/lib/Target/${arch} CFLAGS+= -I${LLVM_SRCS}/lib/Target/${arch}
. endif . endif
.endfor .endfor
SRCDIR= lib SRCDIR= lib
SRCS_MIN+= Analysis/AliasAnalysis.cpp SRCS_MIN+= Analysis/AliasAnalysis.cpp
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SRCS_MIN+= Target/ARM/Thumb1FrameLowering.cpp SRCS_MIN+= Target/ARM/Thumb1FrameLowering.cpp
SRCS_MIN+= Target/ARM/Thumb1InstrInfo.cpp SRCS_MIN+= Target/ARM/Thumb1InstrInfo.cpp
SRCS_MIN+= Target/ARM/Thumb2ITBlockPass.cpp SRCS_MIN+= Target/ARM/Thumb2ITBlockPass.cpp
SRCS_MIN+= Target/ARM/Thumb2InstrInfo.cpp SRCS_MIN+= Target/ARM/Thumb2InstrInfo.cpp
SRCS_MIN+= Target/ARM/Thumb2SizeReduction.cpp SRCS_MIN+= Target/ARM/Thumb2SizeReduction.cpp
SRCS_MIN+= Target/ARM/ThumbRegisterInfo.cpp SRCS_MIN+= Target/ARM/ThumbRegisterInfo.cpp
SRCS_MIN+= Target/ARM/Utils/ARMBaseInfo.cpp SRCS_MIN+= Target/ARM/Utils/ARMBaseInfo.cpp
.endif # MK_LLVM_TARGET_ARM .endif # MK_LLVM_TARGET_ARM
.if ${MK_LLVM_TARGET_BPF} != "no"
SRCS_MIN+= Target/BPF/AsmParser/BPFAsmParser.cpp
SRCS_MIN+= Target/BPF/BPFAsmPrinter.cpp
SRCS_MIN+= Target/BPF/BPFFrameLowering.cpp
SRCS_MIN+= Target/BPF/BPFISelDAGToDAG.cpp
SRCS_MIN+= Target/BPF/BPFISelLowering.cpp
SRCS_MIN+= Target/BPF/BPFInstrInfo.cpp
SRCS_MIN+= Target/BPF/BPFMCInstLower.cpp
SRCS_MIN+= Target/BPF/BPFRegisterInfo.cpp
SRCS_MIN+= Target/BPF/BPFSubtarget.cpp
SRCS_MIN+= Target/BPF/BPFTargetMachine.cpp
SRCS_MIN+= Target/BPF/Disassembler/BPFDisassembler.cpp
SRCS_MIN+= Target/BPF/InstPrinter/BPFInstPrinter.cpp
SRCS_MIN+= Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
SRCS_MIN+= Target/BPF/MCTargetDesc/BPFELFObjectWriter.cpp
SRCS_MIN+= Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
SRCS_MIN+= Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
SRCS_MIN+= Target/BPF/TargetInfo/BPFTargetInfo.cpp
.endif # MK_LLVM_TARGET_BPF
.if ${MK_LLVM_TARGET_MIPS} != "no" .if ${MK_LLVM_TARGET_MIPS} != "no"
SRCS_MIN+= Target/Mips/AsmParser/MipsAsmParser.cpp SRCS_MIN+= Target/Mips/AsmParser/MipsAsmParser.cpp
SRCS_XDW+= Target/Mips/Disassembler/MipsDisassembler.cpp SRCS_XDW+= Target/Mips/Disassembler/MipsDisassembler.cpp
SRCS_MIN+= Target/Mips/InstPrinter/MipsInstPrinter.cpp SRCS_MIN+= Target/Mips/InstPrinter/MipsInstPrinter.cpp
SRCS_MIN+= Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp SRCS_MIN+= Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp
SRCS_MIN+= Target/Mips/MCTargetDesc/MipsABIInfo.cpp SRCS_MIN+= Target/Mips/MCTargetDesc/MipsABIInfo.cpp
SRCS_MIN+= Target/Mips/MCTargetDesc/MipsAsmBackend.cpp SRCS_MIN+= Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
SRCS_MIN+= Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp SRCS_MIN+= Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
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.if exists(${f}) || exists(${f}.d) .if exists(${f}) || exists(${f}.d)
@echo Removing stale generated ${f} files @echo Removing stale generated ${f} files
@rm -f ${f} ${f}.d @rm -f ${f} ${f}.d
.endif .endif
.endfor .endfor
# Note: some rules are superfluous, not every combination is valid. # Note: some rules are superfluous, not every combination is valid.
.for arch in \ .for arch in \
AArch64/AArch64 ARM/ARM Mips/Mips PowerPC/PPC Sparc/Sparc X86/X86 AArch64/AArch64 ARM/ARM BPF/BPF Mips/Mips PowerPC/PPC Sparc/Sparc X86/X86
. for hdr in \ . for hdr in \
AsmMatcher/-gen-asm-matcher \ AsmMatcher/-gen-asm-matcher \
AsmWriter1/-gen-asm-writer,-asmwriternum=1 \ AsmWriter1/-gen-asm-writer,-asmwriternum=1 \
AsmWriter/-gen-asm-writer \ AsmWriter/-gen-asm-writer \
CallingConv/-gen-callingconv \ CallingConv/-gen-callingconv \
CodeEmitter/-gen-emitter \ CodeEmitter/-gen-emitter \
DAGISel/-gen-dag-isel \ DAGISel/-gen-dag-isel \
DisassemblerTables/-gen-disassembler \ DisassemblerTables/-gen-disassembler \
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TGHDRS+= ARMGenInstrInfo.inc TGHDRS+= ARMGenInstrInfo.inc
TGHDRS+= ARMGenMCCodeEmitter.inc TGHDRS+= ARMGenMCCodeEmitter.inc
TGHDRS+= ARMGenMCPseudoLowering.inc TGHDRS+= ARMGenMCPseudoLowering.inc
TGHDRS+= ARMGenRegisterBank.inc TGHDRS+= ARMGenRegisterBank.inc
TGHDRS+= ARMGenRegisterInfo.inc TGHDRS+= ARMGenRegisterInfo.inc
TGHDRS+= ARMGenSubtargetInfo.inc TGHDRS+= ARMGenSubtargetInfo.inc
TGHDRS+= ARMGenSystemRegister.inc TGHDRS+= ARMGenSystemRegister.inc
.endif # MK_LLVM_TARGET_ARM .endif # MK_LLVM_TARGET_ARM
.if ${MK_LLVM_TARGET_BPF} != "no"
TGHDRS+= BPFGenAsmMatcher.inc
TGHDRS+= BPFGenAsmWriter.inc
TGHDRS+= BPFGenCallingConv.inc
TGHDRS+= BPFGenDAGISel.inc
TGHDRS+= BPFGenDisassemblerTables.inc
TGHDRS+= BPFGenInstrInfo.inc
TGHDRS+= BPFGenMCCodeEmitter.inc
TGHDRS+= BPFGenRegisterInfo.inc
TGHDRS+= BPFGenSubtargetInfo.inc
.endif # MK_LLVM_TARGET_BPF
.if ${MK_LLVM_TARGET_MIPS} != "no" .if ${MK_LLVM_TARGET_MIPS} != "no"
TGHDRS+= MipsGenAsmMatcher.inc TGHDRS+= MipsGenAsmMatcher.inc
TGHDRS+= MipsGenAsmWriter.inc TGHDRS+= MipsGenAsmWriter.inc
TGHDRS+= MipsGenCallingConv.inc TGHDRS+= MipsGenCallingConv.inc
TGHDRS+= MipsGenDAGISel.inc TGHDRS+= MipsGenDAGISel.inc
TGHDRS+= MipsGenDisassemblerTables.inc TGHDRS+= MipsGenDisassemblerTables.inc
TGHDRS+= MipsGenFastISel.inc TGHDRS+= MipsGenFastISel.inc
TGHDRS+= MipsGenInstrInfo.inc TGHDRS+= MipsGenInstrInfo.inc
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