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	.if \el == 0			.if \el == 0
	mrs x18, sp_el0			mrs x18, sp_el0
	.endif			.endif
	str x10, [sp, #(TF_ELR)]			str x10, [sp, #(TF_ELR)]
	stp w11, w12, [sp, #(TF_SPSR)]			stp w11, w12, [sp, #(TF_SPSR)]
	stp x18, lr, [sp, #(TF_SP)]			stp x18, lr, [sp, #(TF_SP)]
	mrs x18, tpidr_el1			mrs x18, tpidr_el1
	add x29, sp, #(TF_SIZE)			add x29, sp, #(TF_SIZE)
				.if \el == 0
				/* Apply the SSBD (CVE-2018-3639) workaround if needed */
				ldr x1, [x18, #PC_SSBD]
				cbz x1, 1f
				mov w0, #1
				blr x1
				1:
				.endif
	.endm			.endm

	.macro restore_registers el			.macro restore_registers el
	.if \el == 1			.if \el == 1
	msr daifset, #2			msr daifset, #2
	/*			/*
	* Disable interrupts, x18 may change in the interrupt exception			* Disable interrupts, x18 may change in the interrupt exception
	* handler. For EL0 exceptions, do_ast already did this.			* handler. For EL0 exceptions, do_ast already did this.
	*/			*/
				.endif
				.if \el == 0
				/* Remove the SSBD (CVE-2018-3639) workaround if needed */
				ldr x1, [x18, #PC_SSBD]
				cbz x1, 1f
				mov w0, #0
				blr x1
				1:
	.endif			.endif
	ldp x18, lr, [sp, #(TF_SP)]			ldp x18, lr, [sp, #(TF_SP)]
	ldp x10, x11, [sp, #(TF_ELR)]			ldp x10, x11, [sp, #(TF_ELR)]
	.if \el == 0			.if \el == 0
	msr sp_el0, x18			msr sp_el0, x18
	.endif			.endif
	msr spsr_el1, x11			msr spsr_el1, x11
	msr elr_el1, x10			msr elr_el1, x10
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