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sys/dev/ichiic/ig4_pci.c
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#define PCI_CHIP_APL_I2C_1 0x5aae8086 | #define PCI_CHIP_APL_I2C_1 0x5aae8086 | ||||
#define PCI_CHIP_APL_I2C_2 0x5ab08086 | #define PCI_CHIP_APL_I2C_2 0x5ab08086 | ||||
#define PCI_CHIP_APL_I2C_3 0x5ab28086 | #define PCI_CHIP_APL_I2C_3 0x5ab28086 | ||||
#define PCI_CHIP_APL_I2C_4 0x5ab48086 | #define PCI_CHIP_APL_I2C_4 0x5ab48086 | ||||
#define PCI_CHIP_APL_I2C_5 0x5ab68086 | #define PCI_CHIP_APL_I2C_5 0x5ab68086 | ||||
#define PCI_CHIP_APL_I2C_6 0x5ab88086 | #define PCI_CHIP_APL_I2C_6 0x5ab88086 | ||||
#define PCI_CHIP_APL_I2C_7 0x5aba8086 | #define PCI_CHIP_APL_I2C_7 0x5aba8086 | ||||
struct ig4iic_pci_device { | |||||
uint32_t devid; | |||||
const char *desc; | |||||
enum ig4_vers version; | |||||
}; | |||||
static struct ig4iic_pci_device ig4iic_pci_devices[] = { | #define PCI_DEVICE_LYNXPT_LP_I2C_1 0x9c61 | ||||
{ PCI_CHIP_LYNXPT_LP_I2C_1, "Intel Lynx Point-LP I2C Controller-1", IG4_HASWELL}, | #define PCI_DEVICE_LYNXPT_LP_I2C_2 0x9c62 | ||||
{ PCI_CHIP_LYNXPT_LP_I2C_2, "Intel Lynx Point-LP I2C Controller-2", IG4_HASWELL}, | #define PCI_DEVICE_BRASWELL_I2C_1 0x22c1 | ||||
{ PCI_CHIP_BRASWELL_I2C_1, "Intel Braswell Serial I/O I2C Port 1", IG4_ATOM}, | #define PCI_DEVICE_BRASWELL_I2C_2 0x22c2 | ||||
{ PCI_CHIP_BRASWELL_I2C_2, "Intel Braswell Serial I/O I2C Port 2", IG4_ATOM}, | #define PCI_DEVICE_BRASWELL_I2C_3 0x22c3 | ||||
{ PCI_CHIP_BRASWELL_I2C_3, "Intel Braswell Serial I/O I2C Port 3", IG4_ATOM}, | #define PCI_DEVICE_BRASWELL_I2C_5 0x22c5 | ||||
{ PCI_CHIP_BRASWELL_I2C_5, "Intel Braswell Serial I/O I2C Port 5", IG4_ATOM}, | #define PCI_DEVICE_BRASWELL_I2C_6 0x22c6 | ||||
{ PCI_CHIP_BRASWELL_I2C_6, "Intel Braswell Serial I/O I2C Port 6", IG4_ATOM}, | #define PCI_DEVICE_BRASWELL_I2C_7 0x22c7 | ||||
{ PCI_CHIP_BRASWELL_I2C_7, "Intel Braswell Serial I/O I2C Port 7", IG4_ATOM}, | #define PCI_DEVICE_SKYLAKE_I2C_0 0x9d60 | ||||
{ PCI_CHIP_SKYLAKE_I2C_0, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE}, | #define PCI_DEVICE_SKYLAKE_I2C_1 0x9d61 | ||||
{ PCI_CHIP_SKYLAKE_I2C_1, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE}, | #define PCI_DEVICE_SKYLAKE_I2C_2 0x9d62 | ||||
{ PCI_CHIP_SKYLAKE_I2C_2, "Intel Sunrise Point-LP I2C Controller-2", IG4_SKYLAKE}, | #define PCI_DEVICE_SKYLAKE_I2C_3 0x9d63 | ||||
{ PCI_CHIP_SKYLAKE_I2C_3, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE}, | #define PCI_DEVICE_SKYLAKE_I2C_4 0x9d64 | ||||
{ PCI_CHIP_SKYLAKE_I2C_4, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE}, | #define PCI_DEVICE_SKYLAKE_I2C_5 0x9d65 | ||||
{ PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE}, | #define PCI_DEVICE_APL_I2C_0 0x5aac | ||||
{ PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL}, | #define PCI_DEVICE_APL_I2C_1 0x5aae | ||||
{ PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL}, | #define PCI_DEVICE_APL_I2C_2 0x5ab0 | ||||
{ PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL}, | #define PCI_DEVICE_APL_I2C_3 0x5ab2 | ||||
{ PCI_CHIP_APL_I2C_3, "Intel Apollo Lake I2C Controller-3", IG4_APL}, | #define PCI_DEVICE_APL_I2C_4 0x5ab4 | ||||
{ PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_APL}, | #define PCI_DEVICE_APL_I2C_5 0x5ab6 | ||||
{ PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_APL}, | #define PCI_DEVICE_APL_I2C_6 0x5ab8 | ||||
{ PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_APL}, | #define PCI_DEVICE_APL_I2C_7 0x5aba | ||||
{ PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL}, | #define INTEL_VENDOR_ID 0x8086 | ||||
{ 0, NULL, 0 }, | |||||
struct pci_device_table ig4iic_pci_devices[] = { | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_LYNXPT_LP_I2C_1), | |||||
PCI_DESCR("Intel Lynx Point-LP I2C Controller-1"), .unused = (1)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_LYNXPT_LP_I2C_2), | |||||
PCI_DESCR("Intel Lynx Point-LP I2C Controller-2"), .unused = (1)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_BRASWELL_I2C_1), | |||||
PCI_DESCR("Intel Braswell Serial I/O I2C Port 1"), .unused = (2)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_BRASWELL_I2C_2), | |||||
PCI_DESCR("Intel Braswell Serial I/O I2C Port 2"), .unused = (2)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_BRASWELL_I2C_3), | |||||
PCI_DESCR("Intel Braswell Serial I/O I2C Port 3"), .unused = (2)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_BRASWELL_I2C_5), | |||||
PCI_DESCR("Intel Braswell Serial I/O I2C Port 5"), .unused = (2)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_BRASWELL_I2C_6), | |||||
PCI_DESCR("Intel Braswell Serial I/O I2C Port 6"), .unused = (2)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_BRASWELL_I2C_7), | |||||
PCI_DESCR("Intel Braswell Serial I/O I2C Port 7"), .unused = (2)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_SKYLAKE_I2C_0), | |||||
PCI_DESCR("Intel Sunrise Point-LP I2C Controller-0"), .unused = (3)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_SKYLAKE_I2C_1), | |||||
PCI_DESCR("Intel Sunrise Point-LP I2C Controller-1"), .unused = (3)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_SKYLAKE_I2C_2), | |||||
PCI_DESCR("Intel Sunrise Point-LP I2C Controller-2"), .unused = (3)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_SKYLAKE_I2C_3), | |||||
PCI_DESCR("Intel Sunrise Point-LP I2C Controller-3"), .unused = (3)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_SKYLAKE_I2C_4), | |||||
PCI_DESCR("Intel Sunrise Point-LP I2C Controller-4"), .unused = (3)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_SKYLAKE_I2C_5), | |||||
PCI_DESCR("Intel Sunrise Point-LP I2C Controller-5"), .unused = (3)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_APL_I2C_0), | |||||
PCI_DESCR("Intel Apollo Lake I2C Controller-0"), .unused = (4)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_APL_I2C_1), | |||||
PCI_DESCR("Intel Apollo Lake I2C Controller-1"), .unused = (4)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_APL_I2C_2), | |||||
PCI_DESCR("Intel Apollo Lake I2C Controller-2"), .unused = (4)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_APL_I2C_3), | |||||
PCI_DESCR("Intel Apollo Lake I2C Controller-3"), .unused = (4)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_APL_I2C_4), | |||||
PCI_DESCR("Intel Apollo Lake I2C Controller-4"), .unused = (4)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_APL_I2C_5), | |||||
PCI_DESCR("Intel Apollo Lake I2C Controller-5"), .unused = (4)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_APL_I2C_6), | |||||
PCI_DESCR("Intel Apollo Lake I2C Controller-6"), .unused = (4)}, | |||||
{PCI_DEV(INTEL_VENDOR_ID, PCI_DEVICE_APL_I2C_7), | |||||
PCI_DESCR("Intel Apollo Lake I2C Controller-7"), .unused = (4)} | |||||
}; | }; | ||||
static int | static int | ||||
ig4iic_pci_probe(device_t dev) | ig4iic_pci_probe(device_t dev) | ||||
{ | { | ||||
ig4iic_softc_t *sc = device_get_softc(dev); | ig4iic_softc_t *sc = device_get_softc(dev); | ||||
uint32_t devid; | struct const pci_device_table *ig4d; | ||||
int i; | |||||
devid = pci_get_devid(dev); | ig4d = PCI_MATCH(dev, ig4iic_pci_devices); | ||||
for (i = 0; ig4iic_pci_devices[i].devid != 0; i++) { | if (ig4d == NULL) | ||||
if (ig4iic_pci_devices[i].devid == devid) { | return (ENXIO); | ||||
device_set_desc(dev, ig4iic_pci_devices[i].desc); | device_set_desc(dev, ig4d->descr); | ||||
sc->version = ig4iic_pci_devices[i].version; | if (ig4d->unused == 1) | ||||
sc->version = IG4_HASWELL; | |||||
else if (ig4d->unused == 2) | |||||
sc->version = IG4_ATOM; | |||||
else if (ig4d->unused == 3) | |||||
sc->version = IG4_SKYLAKE; | |||||
else if (ig4d->unused == 4) | |||||
sc->version = IG4_APL; | |||||
return (BUS_PROBE_DEFAULT); | return (BUS_PROBE_DEFAULT); | ||||
} | } | ||||
} | |||||
return (ENXIO); | |||||
} | |||||
static int | static int | ||||
ig4iic_pci_attach(device_t dev) | ig4iic_pci_attach(device_t dev) | ||||
{ | { | ||||
ig4iic_softc_t *sc = device_get_softc(dev); | ig4iic_softc_t *sc = device_get_softc(dev); | ||||
int error; | int error; | ||||
sc->dev = dev; | sc->dev = dev; | ||||
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines | static driver_t ig4iic_pci_driver = { | ||||
ig4iic_pci_methods, | ig4iic_pci_methods, | ||||
sizeof(struct ig4iic_softc) | sizeof(struct ig4iic_softc) | ||||
}; | }; | ||||
static devclass_t ig4iic_pci_devclass; | static devclass_t ig4iic_pci_devclass; | ||||
DRIVER_MODULE_ORDERED(ig4iic_pci, pci, ig4iic_pci_driver, ig4iic_pci_devclass, 0, 0, | DRIVER_MODULE_ORDERED(ig4iic_pci, pci, ig4iic_pci_driver, ig4iic_pci_devclass, 0, 0, | ||||
SI_ORDER_ANY); | SI_ORDER_ANY); | ||||
PCI_PNP_INFO(ig4iic_pci_devices); | |||||
MODULE_DEPEND(ig4iic_pci, pci, 1, 1, 1); | MODULE_DEPEND(ig4iic_pci, pci, 1, 1, 1); | ||||
MODULE_DEPEND(ig4iic_pci, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); | MODULE_DEPEND(ig4iic_pci, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); | ||||
MODULE_VERSION(ig4iic_pci, 1); | MODULE_VERSION(ig4iic_pci, 1); |