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head/sys/i386/include/counter.h
Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines | if ((cpu_feature & CPUID_CX8) == 0) { | ||||
* The machines without cmpxchg8b are not SMP. | * The machines without cmpxchg8b are not SMP. | ||||
* Disabling the preemption provides atomicity of the | * Disabling the preemption provides atomicity of the | ||||
* counter reading, since update is done in the | * counter reading, since update is done in the | ||||
* critical section as well. | * critical section as well. | ||||
*/ | */ | ||||
critical_enter(); | critical_enter(); | ||||
CPU_FOREACH(i) { | CPU_FOREACH(i) { | ||||
res += *(uint64_t *)((char *)p + | res += *(uint64_t *)((char *)p + | ||||
sizeof(struct pcpu) * i); | UMA_PCPU_ALLOC_SIZE * i); | ||||
} | } | ||||
critical_exit(); | critical_exit(); | ||||
} else { | } else { | ||||
CPU_FOREACH(i) | CPU_FOREACH(i) | ||||
res += counter_u64_read_one_8b((uint64_t *)((char *)p + | res += counter_u64_read_one_8b((uint64_t *)((char *)p + | ||||
sizeof(struct pcpu) * i)); | UMA_PCPU_ALLOC_SIZE * i)); | ||||
} | } | ||||
return (res); | return (res); | ||||
} | } | ||||
static inline void | static inline void | ||||
counter_u64_zero_one_8b(uint64_t *p) | counter_u64_zero_one_8b(uint64_t *p) | ||||
{ | { | ||||
Show All 10 Lines | "1:\n\t" | ||||
: "memory", "cc", "eax", "edx", "ebx", "ecx"); | : "memory", "cc", "eax", "edx", "ebx", "ecx"); | ||||
} | } | ||||
static void | static void | ||||
counter_u64_zero_one_cpu(void *arg) | counter_u64_zero_one_cpu(void *arg) | ||||
{ | { | ||||
uint64_t *p; | uint64_t *p; | ||||
p = (uint64_t *)((char *)arg + sizeof(struct pcpu) * PCPU_GET(cpuid)); | p = (uint64_t *)((char *)arg + UMA_PCPU_ALLOC_SIZE * PCPU_GET(cpuid)); | ||||
counter_u64_zero_one_8b(p); | counter_u64_zero_one_8b(p); | ||||
} | } | ||||
static inline void | static inline void | ||||
counter_u64_zero_inline(counter_u64_t c) | counter_u64_zero_inline(counter_u64_t c) | ||||
{ | { | ||||
int i; | int i; | ||||
if ((cpu_feature & CPUID_CX8) == 0) { | if ((cpu_feature & CPUID_CX8) == 0) { | ||||
critical_enter(); | critical_enter(); | ||||
CPU_FOREACH(i) | CPU_FOREACH(i) | ||||
*(uint64_t *)((char *)c + sizeof(struct pcpu) * i) = 0; | *(uint64_t *)((char *)c + UMA_PCPU_ALLOC_SIZE * i) = 0; | ||||
critical_exit(); | critical_exit(); | ||||
} else { | } else { | ||||
smp_rendezvous(smp_no_rendezvous_barrier, | smp_rendezvous(smp_no_rendezvous_barrier, | ||||
counter_u64_zero_one_cpu, smp_no_rendezvous_barrier, c); | counter_u64_zero_one_cpu, smp_no_rendezvous_barrier, c); | ||||
} | } | ||||
} | } | ||||
#endif | #endif | ||||
Show All 22 Lines |