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	return (EINVAL);	return (EINVAL);
	}	}

	if ((cpu_feature2 & CPUID2_SSE41) == 0) {	if ((cpu_feature & CPUID2_SSE41) == 0 && (cpu_feature2 & CPUID2_SSE41) == 0) {
		jmgUnsubmitted Not Done Inline Actions you're checking for CPUID_CLFSH not CPUID2_SSE41 on cpu_feature, if you're doing that spell it correctly. According to my reading, CLFSH just denotes the presence of SSE2, not the required SSE4 instructions that are now required by GCM... If the need for supporting older, non-SSE4 is desired, then an audit needs to be done, and only enable those algorithms that do not require SSE4. I did an audit of what machines are out there, and the second thread linked, all AES-NI machines have SSE4 support, if this is a bug in ESX/Xen/etc, then we need to special case it only for the respective cases. Please provide a dmesg output showing the features bits requiring this change. I currently don't see a need for this change. jmg: you're checking for CPUID_CLFSH not CPUID2_SSE41 on cpu_feature, if you're doing that spell it…
	device_printf(dev, "No SSE4.1 support.\n");	device_printf(dev, "No SSE4.1 support.\n");
	return (EINVAL);	return (EINVAL);
	}	}
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