Differential D15583 Diff 44442 sys/mips/include/cpuregs.h

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sys/mips/include/cpuregs.h

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	* v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)			* v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
	*			*
	* $FreeBSD$			* $FreeBSD$
	*/			*/

	#ifndef _MIPS_CPUREGS_H_			#ifndef _MIPS_CPUREGS_H_
	#define _MIPS_CPUREGS_H_			#define _MIPS_CPUREGS_H_

				#ifndef _KVM_MINIDUMP
				#include <machine/cca.h>
				#endif

	/*			/*
	* Address space.			* Address space.
	* 32-bit mips CPUS partition their 32-bit address space into four segments:			* 32-bit mips CPUS partition their 32-bit address space into four segments:
	*			*
	* kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped			* kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
	* kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped			* kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
	* kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped			* kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
	* kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped			* kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
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	#define MIPS_IS_KSEG0_ADDR(x) \			#define MIPS_IS_KSEG0_ADDR(x) \
	(((vm_offset_t)(x) >= MIPS_KSEG0_START) && \			(((vm_offset_t)(x) >= MIPS_KSEG0_START) && \
	((vm_offset_t)(x) <= MIPS_KSEG0_END))			((vm_offset_t)(x) <= MIPS_KSEG0_END))
	#define MIPS_IS_KSEG1_ADDR(x) \			#define MIPS_IS_KSEG1_ADDR(x) \
	(((vm_offset_t)(x) >= MIPS_KSEG1_START) && \			(((vm_offset_t)(x) >= MIPS_KSEG1_START) && \
	((vm_offset_t)(x) <= MIPS_KSEG1_END))			((vm_offset_t)(x) <= MIPS_KSEG1_END))
	#define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) \|\| \			#define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) \|\| \
	MIPS_IS_KSEG1_ADDR(x))			MIPS_IS_KSEG1_ADDR(x))

	/*
	* Cache Coherency Attributes:
	* UC: Uncached.
	* UA: Uncached accelerated.
	* C: Cacheable, coherency unspecified.
	* CNC: Cacheable non-coherent.
	* CC: Cacheable coherent.
	* CCS: Cacheable coherent, shared read.
	* CCE: Cacheable coherent, exclusive read.
	* CCEW: Cacheable coherent, exclusive write.
	* CCUOW: Cacheable coherent, update on write.
	*
	* Note that some bits vary in meaning across implementations (and that the
	* listing here is no doubt incomplete) and that the optimal cached mode varies
	* between implementations. 0x02 is required to be UC and 0x03 is required to
	* be a least C.
	*
	* We define the following logical bits:
	* UNCACHED:
	* The optimal uncached mode for the target CPU type. This must
	* be suitable for use in accessing memory-mapped devices.
	* CACHED: The optional cached mode for the target CPU type.
	*/

	#define MIPS_CCA_UC 0x02 /* Uncached. */
	#define MIPS_CCA_C 0x03 /* Cacheable, coherency unspecified. */

	#if defined(CPU_R4000) \|\| defined(CPU_R10000)
	#define MIPS_CCA_CNC 0x03
	#define MIPS_CCA_CCE 0x04
	#define MIPS_CCA_CCEW 0x05

	#ifdef CPU_R4000
	#define MIPS_CCA_CCUOW 0x06
	#endif

	#ifdef CPU_R10000
	#define MIPS_CCA_UA 0x07
	#endif

	#define MIPS_CCA_CACHED MIPS_CCA_CCEW
	#endif /* defined(CPU_R4000) \|\| defined(CPU_R10000) */

	#if defined(CPU_SB1)
	#define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */
	#endif

	#if defined(CPU_MIPS74K)
	#define MIPS_CCA_UNCACHED 0x02
	#define MIPS_CCA_CACHED 0x03
	#endif

	/*
	* 1004K and 1074K cores, as well as interAptiv and proAptiv cores, support
	* Cacheable Coherent CCAs 0x04 and 0x05, as well as Cacheable non-Coherent
	* CCA 0x03 and Uncached Accelerated CCA 0x07
	*/
	#if defined(CPU_MIPS1004K) \|\| defined(CPU_MIPS1074K) \|\| \
	defined(CPU_INTERAPTIV) \|\| defined(CPU_PROAPTIV)
	#define MIPS_CCA_CNC 0x03
	#define MIPS_CCA_CCE 0x04
	#define MIPS_CCA_CCS 0x05
	#define MIPS_CCA_UA 0x07

	/* We use shared read CCA for CACHED CCA */
	#define MIPS_CCA_CACHED MIPS_CCA_CCS
	#endif

	#if defined(CPU_XBURST)
	#define MIPS_CCA_UA 0x01
	#define MIPS_CCA_WC MIPS_CCA_UA
	#endif

	#ifndef MIPS_CCA_UNCACHED
	#define MIPS_CCA_UNCACHED MIPS_CCA_UC
	#endif

	/*
	* If we don't know which cached mode to use and there is a cache coherent
	* mode, use it. If there is not a cache coherent mode, use the required
	* cacheable mode.
	*/
	#ifndef MIPS_CCA_CACHED
	#ifdef MIPS_CCA_CC
	#define MIPS_CCA_CACHED MIPS_CCA_CC
	#else
	#define MIPS_CCA_CACHED MIPS_CCA_C
	#endif
	#endif

	#define MIPS_PHYS_TO_XKPHYS(cca,x) \			#define MIPS_PHYS_TO_XKPHYS(cca,x) \
	((0x2ULL << 62) \| ((unsigned long long)(cca) << 59) \| (x))			((0x2ULL << 62) \| ((unsigned long long)(cca) << 59) \| (x))
	#define MIPS_PHYS_TO_XKPHYS_CACHED(x) \			#define MIPS_PHYS_TO_XKPHYS_CACHED(x) \
	((0x2ULL << 62) \| ((unsigned long long)(MIPS_CCA_CACHED) << 59) \| (x))			((0x2ULL << 62) \| ((unsigned long long)(MIPS_CCA_CACHED) << 59) \| (x))
	#define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \			#define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \
	((0x2ULL << 62) \| ((unsigned long long)(MIPS_CCA_UNCACHED) << 59) \| (x))			((0x2ULL << 62) \| ((unsigned long long)(MIPS_CCA_UNCACHED) << 59) \| (x))

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