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sys/dev/rtwn/rtl8188e/r88e_init.c
Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines | |||||
#include <dev/rtwn/if_rtwn_debug.h> | #include <dev/rtwn/if_rtwn_debug.h> | ||||
#include <dev/rtwn/rtl8192c/r92c.h> | #include <dev/rtwn/rtl8192c/r92c.h> | ||||
#include <dev/rtwn/rtl8192c/r92c_var.h> | #include <dev/rtwn/rtl8192c/r92c_var.h> | ||||
#include <dev/rtwn/rtl8188e/r88e.h> | #include <dev/rtwn/rtl8188e/r88e.h> | ||||
#include <dev/rtwn/rtl8188e/r88e_reg.h> | #include <dev/rtwn/rtl8188e/r88e_reg.h> | ||||
#include <dev/rtwn/rtl8192c/pci/r92ce_reg.h> | |||||
static void | static void | ||||
r88e_crystalcap_write(struct rtwn_softc *sc) | r88e_crystalcap_write(struct rtwn_softc *sc) | ||||
{ | { | ||||
struct r92c_softc *rs = sc->sc_priv; | struct r92c_softc *rs = sc->sc_priv; | ||||
uint32_t reg; | uint32_t reg; | ||||
uint8_t val; | uint8_t val; | ||||
val = rs->crystalcap & 0x3f; | val = rs->crystalcap & 0x3f; | ||||
Show All 20 Lines | r88e_init_bb(struct rtwn_softc *sc) | ||||
r92c_init_bb_common(sc); | r92c_init_bb_common(sc); | ||||
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); | rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); | ||||
rtwn_delay(sc, 1); | rtwn_delay(sc, 1); | ||||
rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); | rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); | ||||
rtwn_delay(sc, 1); | rtwn_delay(sc, 1); | ||||
r88e_crystalcap_write(sc); | r88e_crystalcap_write(sc); | ||||
} | |||||
int | |||||
r88ee_llt_init(struct rtwn_softc *sc) { | |||||
rtwn_write_1(sc, R92C_RQPN_NPQ, 0x01); | |||||
rtwn_write_4(sc, R92C_TRXFF_BNDY, 0x80730d29); | |||||
rtwn_write_4(sc, R92C_TRXFF_BNDY, (0x25FF0000 | sc->pktbuf_count)); | |||||
rtwn_write_1(sc, R92C_TDECTRL + 1, sc->pktbuf_count); | |||||
rtwn_write_1(sc, R88E_TXPKTBUF_BCNQ1_BDNY, sc->pktbuf_count); | |||||
rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, sc->pktbuf_count); | |||||
rtwn_write_1(sc, 0x45D, sc->pktbuf_count); | |||||
rtwn_write_1(sc, R92C_PBP, 0x11); | |||||
rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 0x4); | |||||
return r92c_llt_init(sc); | |||||
} | |||||
void | |||||
r88ee_init_bb(struct rtwn_softc *sc) | |||||
{ | |||||
uint32_t tmp; | |||||
int i, j; | |||||
rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0, | |||||
R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | | |||||
R92C_SYS_FUNC_EN_DIO_RF); | |||||
rtwn_write_1(sc, R92C_RF_CTRL, | |||||
R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); | |||||
rtwn_write_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_PCIEA | | |||||
R92C_SYS_FUNC_EN_DIO_PCIE | | |||||
R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); | |||||
tmp = rtwn_read_4(sc, 0x4c); | |||||
rtwn_write_4(sc, 0x4c, tmp | 0xff7fffff); | |||||
for (i = 0; i < sc->bb_size; i++) { | |||||
const struct rtwn_bb_prog *bb_prog = &sc->bb_prog[i]; | |||||
while(!rtwn_check_condition(sc, bb_prog->cond)) { | |||||
KASSERT(bb_prog->next != NULL, | |||||
("%s: wrong condition value (i %d)\n", | |||||
__func__, i)); | |||||
bb_prog = bb_prog->next; | |||||
} | |||||
for (j = 0; j < bb_prog->count; j++) { | |||||
RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, | |||||
"BB: reg 0x%03x, val 0x%08x\n", | |||||
bb_prog->reg[j], bb_prog->val[j]); | |||||
rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]); | |||||
rtwn_delay(sc, 1); | |||||
} | |||||
} | |||||
for (i = 0; i < sc->agc_size; i++) { | |||||
const struct rtwn_agc_prog *agc_prog = &sc->agc_prog[i]; | |||||
while(!rtwn_check_condition(sc, agc_prog->cond)) { | |||||
KASSERT(agc_prog->next != NULL, | |||||
("%s: wrong condition value (2) (i %d)\n", | |||||
__func__, i)); | |||||
agc_prog = agc_prog->next; | |||||
} | |||||
for(j = 0; j < agc_prog->count; j++) { | |||||
RTWN_DPRINTF(sc, RTWN_DEBUG_RESET, | |||||
"AGC: val 0x%08x\n", agc_prog->val[j]); | |||||
rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, | |||||
agc_prog->val[j]); | |||||
rtwn_delay(sc, 1); | |||||
} | |||||
} | |||||
if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR) | |||||
sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; | |||||
rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0x1000000, 0); | |||||
rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0x2000000, 0); | |||||
} | } | ||||
int | int | ||||
r88e_power_on(struct rtwn_softc *sc) | r88e_power_on(struct rtwn_softc *sc) | ||||
{ | { | ||||
#define RTWN_CHK(res) do { \ | #define RTWN_CHK(res) do { \ | ||||
if (res != 0) \ | if (res != 0) \ | ||||
return (EIO); \ | return (EIO); \ | ||||
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