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sys/dev/rtwn/rtl8188e/pci/r88ee_reg.h
Show All 25 Lines | |||||
#include <dev/rtwn/rtl8192c/r92c_reg.h> | #include <dev/rtwn/rtl8192c/r92c_reg.h> | ||||
#define R88EE_MAX_CHAINS 4 | #define R88EE_MAX_CHAINS 4 | ||||
/* | /* | ||||
* MAC registers. | * MAC registers. | ||||
*/ | */ | ||||
/* System Configuration. */ | |||||
#define R88EE_PCIE_MIO_INTF 0x0e4 | |||||
#define R88EE_PCIE_MIO_INTD 0x0e8 | |||||
/* PCIe Configuration. */ | |||||
#define R88EE_PCIE_CTRL_REG 0x300 | |||||
#define R88EE_INT_MIG 0x304 | |||||
#define R88EE_BCNQ_DESA 0x308 | |||||
#define R88EE_HQ_DESA 0x310 | |||||
#define R88EE_MGQ_DESA 0x318 | |||||
#define R88EE_VOQ_DESA 0x320 | |||||
#define R88EE_VIQ_DESA 0x328 | |||||
#define R88EE_BEQ_DESA 0x330 | |||||
#define R88EE_BKQ_DESA 0x338 | |||||
#define R88EE_RX_DESA 0x340 | |||||
#define R88EE_DBI 0x348 | |||||
#define R88EE_MDIO 0x354 | |||||
#define R88EE_DBG_SEL 0x360 | |||||
#define R88EE_PCIE_HRPWM 0x361 | |||||
#define R88EE_PCIE_HCPWM 0x363 | |||||
#define R88EE_UART_CTRL 0x364 | |||||
#define R88EE_UART_TX_DES 0x370 | |||||
#define R88EE_UART_RX_DES 0x378 | |||||
/* EDCA Registers */ | /* EDCA Registers */ | ||||
#define R88EE_SIFS_CTX 0x0514 | |||||
#define R88EE_SIFS_TRX 0x0516 | #define R88EE_SIFS_TRX 0x0516 | ||||
#define R88EE_SIFS_SPEC 0x0428 | #define R88EE_SIFS_SPEC 0x0428 | ||||
#define R88EE_SIFS_SPEC_MAC 0x063A | #define R88EE_SIFS_SPEC_MAC 0x063A | ||||
#define R88EE_SIFS_RESP_OFDM 0x063E | #define R88EE_SIFS_RESP_OFDM 0x063E | ||||
/* Bits for R88EE_GPIO_MUXCFG. */ | |||||
#define R88EE_GPIO_MUXCFG_RFKILL 0x0008 | |||||
/* Bits for R88EE_GPIO_IO_SEL. */ | /* Bits for R88EE_GPIO_IO_SEL. */ | ||||
#define R88EE_GPIO_IO_SEL_2 0x0062 | #define R88EE_GPIO_IO_SEL_2 0x0062 | ||||
#define R88EE_GPIO_IO_SEL_RFKILL 0x0008 | |||||
/* Bits for R88EE_LEDCFG2. */ | |||||
#define R88EE_LEDCFG2_EN 0x60 | |||||
#define R88EE_LEDCFG2_DIS 0x68 | |||||
/* Bits for R88EE_HIMR. */ | /* Bits for R88EE_HIMR. */ | ||||
#define R88EE_IMR_ROK 0x00000001 /* receive DMA OK */ | #define R88EE_ISR 0x00B4 | ||||
#define R88EE_IMR_VODOK 0x00000002 /* AC_VO DMA OK */ | #define R88EE_HISRE 0x00BC | ||||
#define R88EE_IMR_VIDOK 0x00000004 /* AC_VI DMA OK */ | |||||
#define R88EE_IMR_BEDOK 0x00000008 /* AC_BE DMA OK */ | |||||
#define R88EE_IMR_BKDOK 0x00000010 /* AC_BK DMA OK */ | |||||
#define R88EE_IMR_TXBDER 0x00000020 /* beacon transmit error */ | |||||
#define R88EE_IMR_MGNTDOK 0x00000040 /* management queue DMA OK */ | |||||
#define R88EE_IMR_TBDOK 0x00000080 /* beacon transmit OK */ | |||||
#define R88EE_IMR_HIGHDOK 0x00000100 /* high queue DMA OK */ | |||||
#define R88EE_IMR_BDOK 0x00000200 /* beacon queue DMA OK */ | |||||
#define R88EE_IMR_ATIMEND 0x00000400 /* ATIM window end interrupt */ | |||||
#define R88EE_IMR_RDU 0x00000800 /* Rx descriptor unavailable */ | |||||
#define R88EE_IMR_RXFOVW 0x00001000 /* receive FIFO overflow */ | |||||
#define R88EE_IMR_BCNINT 0x00002000 /* beacon DMA interrupt 0 */ | |||||
#define R88EE_IMR_PSTIMEOUT 0x00004000 /* powersave timeout */ | |||||
#define R88EE_IMR_TXFOVW 0x00008000 /* transmit FIFO overflow */ | |||||
#define R88EE_IMR_TIMEOUT1 0x00010000 /* timeout interrupt 1 */ | |||||
#define R88EE_IMR_TIMEOUT2 0x00020000 /* timeout interrupt 2 */ | |||||
#define R88EE_IMR_BCNDOK1 0x00040000 /* beacon queue DMA OK (1) */ | |||||
#define R88EE_IMR_BCNDOK2 0x00080000 /* beacon queue DMA OK (2) */ | |||||
#define R88EE_IMR_BCNDOK3 0x00100000 /* beacon queue DMA OK (3) */ | |||||
#define R88EE_IMR_BCNDOK4 0x00200000 /* beacon queue DMA OK (4) */ | |||||
#define R88EE_IMR_BCNDOK5 0x00400000 /* beacon queue DMA OK (5) */ | |||||
#define R88EE_IMR_BCNDOK6 0x00800000 /* beacon queue DMA OK (6) */ | |||||
#define R88EE_IMR_BCNDOK7 0x01000000 /* beacon queue DMA OK (7) */ | |||||
#define R88EE_IMR_BCNDOK8 0x02000000 /* beacon queue DMA OK (8) */ | |||||
#define R88EE_IMR_BCNDMAINT1 0x04000000 /* beacon DMA interrupt 1 */ | |||||
#define R88EE_IMR_BCNDMAINT2 0x08000000 /* beacon DMA interrupt 2 */ | |||||
#define R88EE_IMR_BCNDMAINT3 0x10000000 /* beacon DMA interrupt 3 */ | |||||
#define R88EE_IMR_BCNDMAINT4 0x20000000 /* beacon DMA interrupt 4 */ | |||||
#define R88EE_IMR_BCNDMAINT5 0x40000000 /* beacon DMA interrupt 5 */ | |||||
#define R88EE_IMR_BCNDMAINT6 0x80000000 /* beacon DMA interrupt 6 */ | |||||
#define R88EE_HIMR 0xb0 | |||||
#define R88EE_ISR 0xb4 | |||||
#define R88EE_HIMRE 0xb8 | |||||
#define R88EE_HISRE 0xbc | |||||
/* Shortcut. */ | |||||
#define R88EE_IBSS_INT_MASK \ | |||||
(R88EE_IMR_BCNINT | R88EE_IMR_TBDOK | R88EE_IMR_TBDER) | |||||
/* Power On/Off DMA */ | /* Power On/Off DMA */ | ||||
#define R88EE_RXDMA_CONTROL 0x0286 | #define R88EE_RXDMA_CTRL 0x0286 | ||||
#define R88EE_TRXDMA_CTRL 0x010C | #define R88EE_TRXDMA_CTRL 0x0010 | ||||
#endif /* R99EE_REG_H */ | #endif /* R99EE_REG_H */ |