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sys/net/iflib.c
/*- | /*- | ||||
* Copyright (c) 2014-2016, Matthew Macy <mmacy@nextbsd.org> | * Copyright (c) 2014-2017, Matthew Macy <mmacy@nextbsd.org> | ||||
* All rights reserved. | * All rights reserved. | ||||
* | * | ||||
* Redistribution and use in source and binary forms, with or without | * Redistribution and use in source and binary forms, with or without | ||||
* modification, are permitted provided that the following conditions are met: | * modification, are permitted provided that the following conditions are met: | ||||
* | * | ||||
* 1. Redistributions of source code must retain the above copyright notice, | * 1. Redistributions of source code must retain the above copyright notice, | ||||
* this list of conditions and the following disclaimer. | * this list of conditions and the following disclaimer. | ||||
* | * | ||||
Show All 15 Lines | |||||
*/ | */ | ||||
#include <sys/cdefs.h> | #include <sys/cdefs.h> | ||||
__FBSDID("$FreeBSD$"); | __FBSDID("$FreeBSD$"); | ||||
#include "opt_inet.h" | #include "opt_inet.h" | ||||
#include "opt_inet6.h" | #include "opt_inet6.h" | ||||
#include "opt_acpi.h" | #include "opt_acpi.h" | ||||
#include "opt_sched.h" | |||||
#include <sys/param.h> | #include <sys/param.h> | ||||
#include <sys/types.h> | #include <sys/types.h> | ||||
#include <sys/bus.h> | #include <sys/bus.h> | ||||
#include <sys/eventhandler.h> | #include <sys/eventhandler.h> | ||||
#include <sys/sockio.h> | #include <sys/sockio.h> | ||||
#include <sys/kernel.h> | #include <sys/kernel.h> | ||||
#include <sys/lock.h> | #include <sys/lock.h> | ||||
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#include <net/if.h> | #include <net/if.h> | ||||
#include <net/if_var.h> | #include <net/if_var.h> | ||||
#include <net/if_types.h> | #include <net/if_types.h> | ||||
#include <net/if_media.h> | #include <net/if_media.h> | ||||
#include <net/bpf.h> | #include <net/bpf.h> | ||||
#include <net/ethernet.h> | #include <net/ethernet.h> | ||||
#include <net/mp_ring.h> | #include <net/mp_ring.h> | ||||
#include <net/vnet.h> | |||||
#include <netinet/in.h> | #include <netinet/in.h> | ||||
#include <netinet/in_pcb.h> | #include <netinet/in_pcb.h> | ||||
#include <netinet/tcp_lro.h> | #include <netinet/tcp_lro.h> | ||||
#include <netinet/in_systm.h> | #include <netinet/in_systm.h> | ||||
#include <netinet/if_ether.h> | #include <netinet/if_ether.h> | ||||
#include <netinet/ip.h> | #include <netinet/ip.h> | ||||
#include <netinet/ip6.h> | #include <netinet/ip6.h> | ||||
#include <netinet/tcp.h> | #include <netinet/tcp.h> | ||||
#include <netinet/ip_var.h> | |||||
#include <netinet6/ip6_var.h> | |||||
#include <machine/bus.h> | #include <machine/bus.h> | ||||
#include <machine/in_cksum.h> | #include <machine/in_cksum.h> | ||||
#include <vm/vm.h> | #include <vm/vm.h> | ||||
#include <vm/pmap.h> | #include <vm/pmap.h> | ||||
#include <dev/led/led.h> | #include <dev/led/led.h> | ||||
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#include <sys/memdesc.h> | #include <sys/memdesc.h> | ||||
#include <machine/bus.h> | #include <machine/bus.h> | ||||
#include <machine/md_var.h> | #include <machine/md_var.h> | ||||
#include <machine/specialreg.h> | #include <machine/specialreg.h> | ||||
#include <x86/include/busdma_impl.h> | #include <x86/include/busdma_impl.h> | ||||
#include <x86/iommu/busdma_dmar.h> | #include <x86/iommu/busdma_dmar.h> | ||||
#endif | #endif | ||||
#include <sys/bitstring.h> | |||||
/* | /* | ||||
* enable accounting of every mbuf as it comes in to and goes out of iflib's software descriptor references | * enable accounting of every mbuf as it comes in to and goes out of | ||||
* iflib's software descriptor references | |||||
*/ | */ | ||||
#define MEMORY_LOGGING 0 | #define MEMORY_LOGGING 0 | ||||
/* | /* | ||||
* Enable mbuf vectors for compressing long mbuf chains | * Enable mbuf vectors for compressing long mbuf chains | ||||
*/ | */ | ||||
/* | /* | ||||
* NB: | * NB: | ||||
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struct iflib_txq; | struct iflib_txq; | ||||
typedef struct iflib_txq *iflib_txq_t; | typedef struct iflib_txq *iflib_txq_t; | ||||
struct iflib_rxq; | struct iflib_rxq; | ||||
typedef struct iflib_rxq *iflib_rxq_t; | typedef struct iflib_rxq *iflib_rxq_t; | ||||
struct iflib_fl; | struct iflib_fl; | ||||
typedef struct iflib_fl *iflib_fl_t; | typedef struct iflib_fl *iflib_fl_t; | ||||
static void iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid); | |||||
typedef struct iflib_filter_info { | typedef struct iflib_filter_info { | ||||
driver_filter_t *ifi_filter; | driver_filter_t *ifi_filter; | ||||
void *ifi_filter_arg; | void *ifi_filter_arg; | ||||
struct grouptask *ifi_task; | struct grouptask *ifi_task; | ||||
void *ifi_ctx; | |||||
} *iflib_filter_info_t; | } *iflib_filter_info_t; | ||||
struct iflib_ctx { | struct iflib_ctx { | ||||
KOBJ_FIELDS; | KOBJ_FIELDS; | ||||
/* | /* | ||||
* Pointer to hardware driver's softc | * Pointer to hardware driver's softc | ||||
*/ | */ | ||||
void *ifc_softc; | void *ifc_softc; | ||||
device_t ifc_dev; | device_t ifc_dev; | ||||
if_t ifc_ifp; | if_t ifc_ifp; | ||||
cpuset_t ifc_cpus; | cpuset_t ifc_cpus; | ||||
if_shared_ctx_t ifc_sctx; | if_shared_ctx_t ifc_sctx; | ||||
struct if_softc_ctx ifc_softc_ctx; | struct if_softc_ctx ifc_softc_ctx; | ||||
struct mtx ifc_mtx; | struct mtx ifc_mtx; | ||||
uint16_t ifc_nhwtxqs; | uint16_t ifc_nhwtxqs; | ||||
uint16_t ifc_nhwrxqs; | |||||
iflib_txq_t ifc_txqs; | iflib_txq_t ifc_txqs; | ||||
iflib_rxq_t ifc_rxqs; | iflib_rxq_t ifc_rxqs; | ||||
uint32_t ifc_if_flags; | uint32_t ifc_if_flags; | ||||
uint32_t ifc_flags; | uint32_t ifc_flags; | ||||
uint32_t ifc_max_fl_buf_size; | uint32_t ifc_max_fl_buf_size; | ||||
int ifc_in_detach; | int ifc_in_detach; | ||||
int ifc_link_state; | int ifc_link_state; | ||||
int ifc_link_irq; | int ifc_link_irq; | ||||
int ifc_pause_frames; | |||||
int ifc_watchdog_events; | int ifc_watchdog_events; | ||||
struct cdev *ifc_led_dev; | struct cdev *ifc_led_dev; | ||||
struct resource *ifc_msix_mem; | struct resource *ifc_msix_mem; | ||||
struct if_irq ifc_legacy_irq; | struct if_irq ifc_legacy_irq; | ||||
struct grouptask ifc_admin_task; | struct grouptask ifc_admin_task; | ||||
struct grouptask ifc_vflr_task; | struct grouptask ifc_vflr_task; | ||||
struct iflib_filter_info ifc_filter_info; | struct iflib_filter_info ifc_filter_info; | ||||
struct ifmedia ifc_media; | struct ifmedia ifc_media; | ||||
struct sysctl_oid *ifc_sysctl_node; | struct sysctl_oid *ifc_sysctl_node; | ||||
uint16_t ifc_sysctl_ntxqs; | uint16_t ifc_sysctl_ntxqs; | ||||
uint16_t ifc_sysctl_nrxqs; | uint16_t ifc_sysctl_nrxqs; | ||||
uint16_t ifc_sysctl_qs_eq_override; | uint16_t ifc_sysctl_qs_eq_override; | ||||
uint16_t ifc_sysctl_rx_budget; | |||||
uint16_t ifc_sysctl_ntxds[8]; | qidx_t ifc_sysctl_ntxds[8]; | ||||
uint16_t ifc_sysctl_nrxds[8]; | qidx_t ifc_sysctl_nrxds[8]; | ||||
struct if_txrx ifc_txrx; | struct if_txrx ifc_txrx; | ||||
#define isc_txd_encap ifc_txrx.ift_txd_encap | #define isc_txd_encap ifc_txrx.ift_txd_encap | ||||
#define isc_txd_flush ifc_txrx.ift_txd_flush | #define isc_txd_flush ifc_txrx.ift_txd_flush | ||||
#define isc_txd_credits_update ifc_txrx.ift_txd_credits_update | #define isc_txd_credits_update ifc_txrx.ift_txd_credits_update | ||||
#define isc_rxd_available ifc_txrx.ift_rxd_available | #define isc_rxd_available ifc_txrx.ift_rxd_available | ||||
#define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get | #define isc_rxd_pkt_get ifc_txrx.ift_rxd_pkt_get | ||||
#define isc_rxd_refill ifc_txrx.ift_rxd_refill | #define isc_rxd_refill ifc_txrx.ift_rxd_refill | ||||
#define isc_rxd_flush ifc_txrx.ift_rxd_flush | #define isc_rxd_flush ifc_txrx.ift_rxd_flush | ||||
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines | |||||
if_shared_ctx_t | if_shared_ctx_t | ||||
iflib_get_sctx(if_ctx_t ctx) | iflib_get_sctx(if_ctx_t ctx) | ||||
{ | { | ||||
return (ctx->ifc_sctx); | return (ctx->ifc_sctx); | ||||
} | } | ||||
#define IP_ALIGNED(m) ((((uintptr_t)(m)->m_data) & 0x3) == 0x2) | |||||
#define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) | #define CACHE_PTR_INCREMENT (CACHE_LINE_SIZE/sizeof(void*)) | ||||
#define CACHE_PTR_NEXT(ptr) ((void *)(((uintptr_t)(ptr)+CACHE_LINE_SIZE-1) & (CACHE_LINE_SIZE-1))) | |||||
#define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) | #define LINK_ACTIVE(ctx) ((ctx)->ifc_link_state == LINK_STATE_UP) | ||||
#define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) | #define CTX_IS_VF(ctx) ((ctx)->ifc_sctx->isc_flags & IFLIB_IS_VF) | ||||
#define RX_SW_DESC_MAP_CREATED (1 << 0) | #define RX_SW_DESC_MAP_CREATED (1 << 0) | ||||
#define TX_SW_DESC_MAP_CREATED (1 << 1) | #define TX_SW_DESC_MAP_CREATED (1 << 1) | ||||
#define RX_SW_DESC_INUSE (1 << 3) | #define RX_SW_DESC_INUSE (1 << 3) | ||||
#define TX_SW_DESC_MAPPED (1 << 4) | #define TX_SW_DESC_MAPPED (1 << 4) | ||||
typedef struct iflib_sw_rx_desc { | #define M_TOOBIG M_PROTO1 | ||||
bus_dmamap_t ifsd_map; /* bus_dma map for packet */ | |||||
struct mbuf *ifsd_m; /* rx: uninitialized mbuf */ | |||||
caddr_t ifsd_cl; /* direct cluster pointer for rx */ | |||||
uint16_t ifsd_flags; | |||||
} *iflib_rxsd_t; | |||||
typedef struct iflib_sw_tx_desc_val { | typedef struct iflib_sw_rx_desc_array { | ||||
bus_dmamap_t ifsd_map; /* bus_dma map for packet */ | bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ | ||||
struct mbuf *ifsd_m; /* pkthdr mbuf */ | struct mbuf **ifsd_m; /* pkthdr mbufs */ | ||||
uint8_t ifsd_flags; | caddr_t *ifsd_cl; /* direct cluster pointer for rx */ | ||||
} *iflib_txsd_val_t; | uint8_t *ifsd_flags; | ||||
} iflib_rxsd_array_t; | |||||
typedef struct iflib_sw_tx_desc_array { | typedef struct iflib_sw_tx_desc_array { | ||||
bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ | bus_dmamap_t *ifsd_map; /* bus_dma maps for packet */ | ||||
struct mbuf **ifsd_m; /* pkthdr mbufs */ | struct mbuf **ifsd_m; /* pkthdr mbufs */ | ||||
uint8_t *ifsd_flags; | uint8_t *ifsd_flags; | ||||
} iflib_txsd_array_t; | } if_txsd_vec_t; | ||||
/* magic number that should be high enough for any hardware */ | /* magic number that should be high enough for any hardware */ | ||||
#define IFLIB_MAX_TX_SEGS 128 | #define IFLIB_MAX_TX_SEGS 128 | ||||
#define IFLIB_MAX_RX_SEGS 32 | /* bnxt supports 64 with hardware LRO enabled */ | ||||
#define IFLIB_MAX_RX_SEGS 64 | |||||
#define IFLIB_RX_COPY_THRESH 128 | #define IFLIB_RX_COPY_THRESH 128 | ||||
#define IFLIB_MAX_RX_REFRESH 32 | #define IFLIB_MAX_RX_REFRESH 32 | ||||
/* The minimum descriptors per second before we start coalescing */ | |||||
#define IFLIB_MIN_DESC_SEC 16384 | |||||
#define IFLIB_DEFAULT_TX_UPDATE_FREQ 16 | |||||
#define IFLIB_QUEUE_IDLE 0 | #define IFLIB_QUEUE_IDLE 0 | ||||
#define IFLIB_QUEUE_HUNG 1 | #define IFLIB_QUEUE_HUNG 1 | ||||
#define IFLIB_QUEUE_WORKING 2 | #define IFLIB_QUEUE_WORKING 2 | ||||
/* maximum number of txqs that can share an rx interrupt */ | |||||
#define IFLIB_MAX_TX_SHARED_INTR 4 | |||||
/* this should really scale with ring size - 32 is a fairly arbitrary value for this */ | /* this should really scale with ring size - this is a fairly arbitrary value */ | ||||
#define TX_BATCH_SIZE 16 | #define TX_BATCH_SIZE 32 | ||||
#define IFLIB_RESTART_BUDGET 8 | #define IFLIB_RESTART_BUDGET 8 | ||||
#define IFC_LEGACY 0x01 | #define IFC_LEGACY 0x001 | ||||
#define IFC_QFLUSH 0x02 | #define IFC_QFLUSH 0x002 | ||||
#define IFC_MULTISEG 0x04 | #define IFC_MULTISEG 0x004 | ||||
#define IFC_DMAR 0x08 | #define IFC_DMAR 0x008 | ||||
#define IFC_SC_ALLOCATED 0x10 | #define IFC_SC_ALLOCATED 0x010 | ||||
#define IFC_INIT_DONE 0x020 | |||||
#define IFC_PREFETCH 0x040 | |||||
#define IFC_DO_RESET 0x080 | |||||
#define IFC_CHECK_HUNG 0x100 | |||||
#define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ | #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ | ||||
CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ | CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ | ||||
CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) | CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) | ||||
struct iflib_txq { | struct iflib_txq { | ||||
uint16_t ift_in_use; | qidx_t ift_in_use; | ||||
uint16_t ift_cidx; | qidx_t ift_cidx; | ||||
uint16_t ift_cidx_processed; | qidx_t ift_cidx_processed; | ||||
uint16_t ift_pidx; | qidx_t ift_pidx; | ||||
uint8_t ift_gen; | uint8_t ift_gen; | ||||
uint8_t ift_db_pending; | |||||
uint8_t ift_db_pending_queued; | |||||
uint8_t ift_npending; | |||||
uint8_t ift_br_offset; | uint8_t ift_br_offset; | ||||
uint16_t ift_npending; | |||||
uint16_t ift_db_pending; | |||||
uint16_t ift_rs_pending; | |||||
/* implicit pad */ | /* implicit pad */ | ||||
uint8_t ift_txd_size[8]; | |||||
uint64_t ift_processed; | uint64_t ift_processed; | ||||
uint64_t ift_cleaned; | uint64_t ift_cleaned; | ||||
uint64_t ift_cleaned_prev; | |||||
#if MEMORY_LOGGING | #if MEMORY_LOGGING | ||||
uint64_t ift_enqueued; | uint64_t ift_enqueued; | ||||
uint64_t ift_dequeued; | uint64_t ift_dequeued; | ||||
#endif | #endif | ||||
uint64_t ift_no_tx_dma_setup; | uint64_t ift_no_tx_dma_setup; | ||||
uint64_t ift_no_desc_avail; | uint64_t ift_no_desc_avail; | ||||
uint64_t ift_mbuf_defrag_failed; | uint64_t ift_mbuf_defrag_failed; | ||||
uint64_t ift_mbuf_defrag; | uint64_t ift_mbuf_defrag; | ||||
uint64_t ift_map_failed; | uint64_t ift_map_failed; | ||||
uint64_t ift_txd_encap_efbig; | uint64_t ift_txd_encap_efbig; | ||||
uint64_t ift_pullups; | uint64_t ift_pullups; | ||||
struct mtx ift_mtx; | struct mtx ift_mtx; | ||||
struct mtx ift_db_mtx; | struct mtx ift_db_mtx; | ||||
/* constant values */ | /* constant values */ | ||||
if_ctx_t ift_ctx; | if_ctx_t ift_ctx; | ||||
struct ifmp_ring **ift_br; | struct ifmp_ring *ift_br; | ||||
struct grouptask ift_task; | struct grouptask ift_task; | ||||
uint16_t ift_size; | qidx_t ift_size; | ||||
uint16_t ift_id; | uint16_t ift_id; | ||||
struct callout ift_timer; | struct callout ift_timer; | ||||
struct callout ift_db_check; | |||||
iflib_txsd_array_t ift_sds; | if_txsd_vec_t ift_sds; | ||||
uint8_t ift_nbr; | |||||
uint8_t ift_qstatus; | uint8_t ift_qstatus; | ||||
uint8_t ift_active; | |||||
uint8_t ift_closed; | uint8_t ift_closed; | ||||
int ift_watchdog_time; | uint8_t ift_update_freq; | ||||
struct iflib_filter_info ift_filter_info; | struct iflib_filter_info ift_filter_info; | ||||
bus_dma_tag_t ift_desc_tag; | bus_dma_tag_t ift_desc_tag; | ||||
bus_dma_tag_t ift_tso_desc_tag; | bus_dma_tag_t ift_tso_desc_tag; | ||||
iflib_dma_info_t ift_ifdi; | iflib_dma_info_t ift_ifdi; | ||||
#define MTX_NAME_LEN 16 | #define MTX_NAME_LEN 16 | ||||
char ift_mtx_name[MTX_NAME_LEN]; | char ift_mtx_name[MTX_NAME_LEN]; | ||||
char ift_db_mtx_name[MTX_NAME_LEN]; | char ift_db_mtx_name[MTX_NAME_LEN]; | ||||
bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); | bus_dma_segment_t ift_segs[IFLIB_MAX_TX_SEGS] __aligned(CACHE_LINE_SIZE); | ||||
#ifdef IFLIB_DIAGNOSTICS | |||||
uint64_t ift_cpu_exec_count[256]; | |||||
#endif | |||||
} __aligned(CACHE_LINE_SIZE); | } __aligned(CACHE_LINE_SIZE); | ||||
struct iflib_fl { | struct iflib_fl { | ||||
uint16_t ifl_cidx; | qidx_t ifl_cidx; | ||||
uint16_t ifl_pidx; | qidx_t ifl_pidx; | ||||
uint16_t ifl_credits; | qidx_t ifl_credits; | ||||
uint8_t ifl_gen; | uint8_t ifl_gen; | ||||
uint8_t ifl_rxd_size; | |||||
#if MEMORY_LOGGING | #if MEMORY_LOGGING | ||||
uint64_t ifl_m_enqueued; | uint64_t ifl_m_enqueued; | ||||
uint64_t ifl_m_dequeued; | uint64_t ifl_m_dequeued; | ||||
uint64_t ifl_cl_enqueued; | uint64_t ifl_cl_enqueued; | ||||
uint64_t ifl_cl_dequeued; | uint64_t ifl_cl_dequeued; | ||||
#endif | #endif | ||||
/* implicit pad */ | /* implicit pad */ | ||||
bitstr_t *ifl_rx_bitmap; | |||||
qidx_t ifl_fragidx; | |||||
/* constant */ | /* constant */ | ||||
uint16_t ifl_size; | qidx_t ifl_size; | ||||
uint16_t ifl_buf_size; | uint16_t ifl_buf_size; | ||||
uint16_t ifl_cltype; | uint16_t ifl_cltype; | ||||
uma_zone_t ifl_zone; | uma_zone_t ifl_zone; | ||||
iflib_rxsd_t ifl_sds; | iflib_rxsd_array_t ifl_sds; | ||||
iflib_rxq_t ifl_rxq; | iflib_rxq_t ifl_rxq; | ||||
uint8_t ifl_id; | uint8_t ifl_id; | ||||
bus_dma_tag_t ifl_desc_tag; | bus_dma_tag_t ifl_desc_tag; | ||||
iflib_dma_info_t ifl_ifdi; | iflib_dma_info_t ifl_ifdi; | ||||
uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); | uint64_t ifl_bus_addrs[IFLIB_MAX_RX_REFRESH] __aligned(CACHE_LINE_SIZE); | ||||
caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; | caddr_t ifl_vm_addrs[IFLIB_MAX_RX_REFRESH]; | ||||
qidx_t ifl_rxd_idxs[IFLIB_MAX_RX_REFRESH]; | |||||
} __aligned(CACHE_LINE_SIZE); | } __aligned(CACHE_LINE_SIZE); | ||||
static inline int | static inline qidx_t | ||||
get_inuse(int size, int cidx, int pidx, int gen) | get_inuse(int size, qidx_t cidx, qidx_t pidx, uint8_t gen) | ||||
{ | { | ||||
int used; | qidx_t used; | ||||
if (pidx > cidx) | if (pidx > cidx) | ||||
used = pidx - cidx; | used = pidx - cidx; | ||||
else if (pidx < cidx) | else if (pidx < cidx) | ||||
used = size - cidx + pidx; | used = size - cidx + pidx; | ||||
else if (gen == 0 && pidx == cidx) | else if (gen == 0 && pidx == cidx) | ||||
used = 0; | used = 0; | ||||
else if (gen == 1 && pidx == cidx) | else if (gen == 1 && pidx == cidx) | ||||
Show All 9 Lines | |||||
#define IDXDIFF(head, tail, wrap) \ | #define IDXDIFF(head, tail, wrap) \ | ||||
((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) | ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) | ||||
struct iflib_rxq { | struct iflib_rxq { | ||||
/* If there is a separate completion queue - | /* If there is a separate completion queue - | ||||
* these are the cq cidx and pidx. Otherwise | * these are the cq cidx and pidx. Otherwise | ||||
* these are unused. | * these are unused. | ||||
*/ | */ | ||||
uint16_t ifr_size; | qidx_t ifr_size; | ||||
uint16_t ifr_cq_cidx; | qidx_t ifr_cq_cidx; | ||||
uint16_t ifr_cq_pidx; | qidx_t ifr_cq_pidx; | ||||
uint8_t ifr_cq_gen; | uint8_t ifr_cq_gen; | ||||
uint8_t ifr_fl_offset; | uint8_t ifr_fl_offset; | ||||
if_ctx_t ifr_ctx; | if_ctx_t ifr_ctx; | ||||
iflib_fl_t ifr_fl; | iflib_fl_t ifr_fl; | ||||
uint64_t ifr_rx_irq; | uint64_t ifr_rx_irq; | ||||
uint16_t ifr_id; | uint16_t ifr_id; | ||||
uint8_t ifr_lro_enabled; | uint8_t ifr_lro_enabled; | ||||
uint8_t ifr_nfl; | uint8_t ifr_nfl; | ||||
uint8_t ifr_ntxqirq; | |||||
uint8_t ifr_txqid[IFLIB_MAX_TX_SHARED_INTR]; | |||||
struct lro_ctrl ifr_lc; | struct lro_ctrl ifr_lc; | ||||
struct grouptask ifr_task; | struct grouptask ifr_task; | ||||
struct iflib_filter_info ifr_filter_info; | struct iflib_filter_info ifr_filter_info; | ||||
iflib_dma_info_t ifr_ifdi; | iflib_dma_info_t ifr_ifdi; | ||||
/* dynamically allocate if any drivers need a value substantially larger than this */ | /* dynamically allocate if any drivers need a value substantially larger than this */ | ||||
struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); | struct if_rxd_frag ifr_frags[IFLIB_MAX_RX_SEGS] __aligned(CACHE_LINE_SIZE); | ||||
#ifdef IFLIB_DIAGNOSTICS | |||||
uint64_t ifr_cpu_exec_count[256]; | |||||
#endif | |||||
} __aligned(CACHE_LINE_SIZE); | } __aligned(CACHE_LINE_SIZE); | ||||
typedef struct if_rxsd { | |||||
caddr_t *ifsd_cl; | |||||
struct mbuf **ifsd_m; | |||||
iflib_fl_t ifsd_fl; | |||||
qidx_t ifsd_cidx; | |||||
} *if_rxsd_t; | |||||
/* multiple of word size */ | |||||
#ifdef __LP64__ | |||||
#define PKT_INFO_SIZE 6 | |||||
#define RXD_INFO_SIZE 5 | |||||
#define PKT_TYPE uint64_t | |||||
#else | |||||
#define PKT_INFO_SIZE 11 | |||||
#define RXD_INFO_SIZE 8 | |||||
#define PKT_TYPE uint32_t | |||||
#endif | |||||
#define PKT_LOOP_BOUND ((PKT_INFO_SIZE/3)*3) | |||||
#define RXD_LOOP_BOUND ((RXD_INFO_SIZE/4)*4) | |||||
typedef struct if_pkt_info_pad { | |||||
PKT_TYPE pkt_val[PKT_INFO_SIZE]; | |||||
} *if_pkt_info_pad_t; | |||||
typedef struct if_rxd_info_pad { | |||||
PKT_TYPE rxd_val[RXD_INFO_SIZE]; | |||||
} *if_rxd_info_pad_t; | |||||
CTASSERT(sizeof(struct if_pkt_info_pad) == sizeof(struct if_pkt_info)); | |||||
CTASSERT(sizeof(struct if_rxd_info_pad) == sizeof(struct if_rxd_info)); | |||||
static inline void | |||||
pkt_info_zero(if_pkt_info_t pi) | |||||
{ | |||||
if_pkt_info_pad_t pi_pad; | |||||
pi_pad = (if_pkt_info_pad_t)pi; | |||||
pi_pad->pkt_val[0] = 0; pi_pad->pkt_val[1] = 0; pi_pad->pkt_val[2] = 0; | |||||
pi_pad->pkt_val[3] = 0; pi_pad->pkt_val[4] = 0; pi_pad->pkt_val[5] = 0; | |||||
#ifndef __LP64__ | |||||
pi_pad->pkt_val[6] = 0; pi_pad->pkt_val[7] = 0; pi_pad->pkt_val[8] = 0; | |||||
pi_pad->pkt_val[9] = 0; pi_pad->pkt_val[10] = 0; | |||||
#endif | |||||
} | |||||
static inline void | |||||
rxd_info_zero(if_rxd_info_t ri) | |||||
{ | |||||
if_rxd_info_pad_t ri_pad; | |||||
int i; | |||||
ri_pad = (if_rxd_info_pad_t)ri; | |||||
for (i = 0; i < RXD_LOOP_BOUND; i += 4) { | |||||
ri_pad->rxd_val[i] = 0; | |||||
ri_pad->rxd_val[i+1] = 0; | |||||
ri_pad->rxd_val[i+2] = 0; | |||||
ri_pad->rxd_val[i+3] = 0; | |||||
} | |||||
#ifdef __LP64__ | |||||
ri_pad->rxd_val[RXD_INFO_SIZE-1] = 0; | |||||
#endif | |||||
} | |||||
/* | /* | ||||
* Only allow a single packet to take up most 1/nth of the tx ring | * Only allow a single packet to take up most 1/nth of the tx ring | ||||
*/ | */ | ||||
#define MAX_SINGLE_PACKET_FRACTION 12 | #define MAX_SINGLE_PACKET_FRACTION 12 | ||||
#define IF_BAD_DMA (bus_addr_t)-1 | #define IF_BAD_DMA (bus_addr_t)-1 | ||||
static int enable_msix = 1; | |||||
#define mtx_held(m) (((m)->mtx_lock & ~MTX_FLAGMASK) != (uintptr_t)0) | |||||
#define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) | #define CTX_ACTIVE(ctx) ((if_getdrvflags((ctx)->ifc_ifp) & IFF_DRV_RUNNING)) | ||||
#define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF) | #define CTX_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->ifc_mtx, _name, "iflib ctx lock", MTX_DEF) | ||||
#define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx) | #define CTX_LOCK(ctx) mtx_lock(&(ctx)->ifc_mtx) | ||||
#define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx) | #define CTX_UNLOCK(ctx) mtx_unlock(&(ctx)->ifc_mtx) | ||||
#define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx) | #define CTX_LOCK_DESTROY(ctx) mtx_destroy(&(ctx)->ifc_mtx) | ||||
#define TXDB_LOCK_INIT(txq) mtx_init(&(txq)->ift_db_mtx, (txq)->ift_db_mtx_name, NULL, MTX_DEF) | |||||
#define TXDB_TRYLOCK(txq) mtx_trylock(&(txq)->ift_db_mtx) | |||||
#define TXDB_LOCK(txq) mtx_lock(&(txq)->ift_db_mtx) | |||||
#define TXDB_UNLOCK(txq) mtx_unlock(&(txq)->ift_db_mtx) | |||||
#define TXDB_LOCK_DESTROY(txq) mtx_destroy(&(txq)->ift_db_mtx) | |||||
#define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) | #define CALLOUT_LOCK(txq) mtx_lock(&txq->ift_mtx) | ||||
#define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) | #define CALLOUT_UNLOCK(txq) mtx_unlock(&txq->ift_mtx) | ||||
/* Our boot-time initialization hook */ | /* Our boot-time initialization hook */ | ||||
static int iflib_module_event_handler(module_t, int, void *); | static int iflib_module_event_handler(module_t, int, void *); | ||||
static moduledata_t iflib_moduledata = { | static moduledata_t iflib_moduledata = { | ||||
"iflib", | "iflib", | ||||
iflib_module_event_handler, | iflib_module_event_handler, | ||||
NULL | NULL | ||||
}; | }; | ||||
DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); | DECLARE_MODULE(iflib, iflib_moduledata, SI_SUB_INIT_IF, SI_ORDER_ANY); | ||||
MODULE_VERSION(iflib, 1); | MODULE_VERSION(iflib, 1); | ||||
MODULE_DEPEND(iflib, pci, 1, 1, 1); | MODULE_DEPEND(iflib, pci, 1, 1, 1); | ||||
MODULE_DEPEND(iflib, ether, 1, 1, 1); | MODULE_DEPEND(iflib, ether, 1, 1, 1); | ||||
TASKQGROUP_DEFINE(if_io_tqg, mp_ncpus, 1); | |||||
TASKQGROUP_DEFINE(if_config_tqg, 1, 1); | TASKQGROUP_DEFINE(if_config_tqg, 1, 1); | ||||
#ifndef IFLIB_DEBUG_COUNTERS | #ifndef IFLIB_DEBUG_COUNTERS | ||||
#ifdef INVARIANTS | #ifdef INVARIANTS | ||||
#define IFLIB_DEBUG_COUNTERS 1 | #define IFLIB_DEBUG_COUNTERS 1 | ||||
#else | #else | ||||
#define IFLIB_DEBUG_COUNTERS 0 | #define IFLIB_DEBUG_COUNTERS 0 | ||||
#endif /* !INVARIANTS */ | #endif /* !INVARIANTS */ | ||||
#endif | #endif | ||||
static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, | static SYSCTL_NODE(_net, OID_AUTO, iflib, CTLFLAG_RD, 0, | ||||
"iflib driver parameters"); | "iflib driver parameters"); | ||||
/* | /* | ||||
* XXX need to ensure that this can't accidentally cause the head to be moved backwards | * XXX need to ensure that this can't accidentally cause the head to be moved backwards | ||||
*/ | */ | ||||
static int iflib_min_tx_latency = 0; | static int iflib_min_tx_latency = 0; | ||||
SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, | SYSCTL_INT(_net_iflib, OID_AUTO, min_tx_latency, CTLFLAG_RW, | ||||
&iflib_min_tx_latency, 0, "minimize transmit latency at the possibel expense of throughput"); | &iflib_min_tx_latency, 0, "minimize transmit latency at the possible expense of throughput"); | ||||
static int iflib_no_tx_batch = 0; | |||||
SYSCTL_INT(_net_iflib, OID_AUTO, no_tx_batch, CTLFLAG_RW, | |||||
&iflib_no_tx_batch, 0, "minimize transmit latency at the possible expense of throughput"); | |||||
#if IFLIB_DEBUG_COUNTERS | #if IFLIB_DEBUG_COUNTERS | ||||
static int iflib_tx_seen; | static int iflib_tx_seen; | ||||
static int iflib_tx_sent; | static int iflib_tx_sent; | ||||
static int iflib_tx_encap; | static int iflib_tx_encap; | ||||
static int iflib_rx_allocs; | static int iflib_rx_allocs; | ||||
Show All 28 Lines | SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_oactive, CTLFLAG_RD, | ||||
&iflib_txq_drain_oactive, 0, "# drain oactives"); | &iflib_txq_drain_oactive, 0, "# drain oactives"); | ||||
SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, | SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_notready, CTLFLAG_RD, | ||||
&iflib_txq_drain_notready, 0, "# drain notready"); | &iflib_txq_drain_notready, 0, "# drain notready"); | ||||
SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, | SYSCTL_INT(_net_iflib, OID_AUTO, txq_drain_encapfail, CTLFLAG_RD, | ||||
&iflib_txq_drain_encapfail, 0, "# drain encap fails"); | &iflib_txq_drain_encapfail, 0, "# drain encap fails"); | ||||
static int iflib_encap_load_mbuf_fail; | static int iflib_encap_load_mbuf_fail; | ||||
static int iflib_encap_pad_mbuf_fail; | |||||
static int iflib_encap_txq_avail_fail; | static int iflib_encap_txq_avail_fail; | ||||
static int iflib_encap_txd_encap_fail; | static int iflib_encap_txd_encap_fail; | ||||
SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, | SYSCTL_INT(_net_iflib, OID_AUTO, encap_load_mbuf_fail, CTLFLAG_RD, | ||||
&iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); | &iflib_encap_load_mbuf_fail, 0, "# busdma load failures"); | ||||
SYSCTL_INT(_net_iflib, OID_AUTO, encap_pad_mbuf_fail, CTLFLAG_RD, | |||||
&iflib_encap_pad_mbuf_fail, 0, "# runt frame pad failures"); | |||||
SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, | SYSCTL_INT(_net_iflib, OID_AUTO, encap_txq_avail_fail, CTLFLAG_RD, | ||||
&iflib_encap_txq_avail_fail, 0, "# txq avail failures"); | &iflib_encap_txq_avail_fail, 0, "# txq avail failures"); | ||||
SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, | SYSCTL_INT(_net_iflib, OID_AUTO, encap_txd_encap_fail, CTLFLAG_RD, | ||||
&iflib_encap_txd_encap_fail, 0, "# driver encap failures"); | &iflib_encap_txd_encap_fail, 0, "# driver encap failures"); | ||||
static int iflib_task_fn_rxs; | static int iflib_task_fn_rxs; | ||||
static int iflib_rx_intr_enables; | static int iflib_rx_intr_enables; | ||||
static int iflib_fast_intrs; | static int iflib_fast_intrs; | ||||
Show All 29 Lines | |||||
SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, | SYSCTL_INT(_net_iflib, OID_AUTO, rx_mbuf_null, CTLFLAG_RD, | ||||
&iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); | &iflib_rx_mbuf_null, 0, "# times rxeof got null mbuf"); | ||||
SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, | SYSCTL_INT(_net_iflib, OID_AUTO, rxd_flush, CTLFLAG_RD, | ||||
&iflib_rxd_flush, 0, "# times rxd_flush called"); | &iflib_rxd_flush, 0, "# times rxd_flush called"); | ||||
SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, | SYSCTL_INT(_net_iflib, OID_AUTO, verbose_debug, CTLFLAG_RW, | ||||
&iflib_verbose_debug, 0, "enable verbose debugging"); | &iflib_verbose_debug, 0, "enable verbose debugging"); | ||||
#define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) | #define DBG_COUNTER_INC(name) atomic_add_int(&(iflib_ ## name), 1) | ||||
static void | |||||
iflib_debug_reset(void) | |||||
{ | |||||
iflib_tx_seen = iflib_tx_sent = iflib_tx_encap = iflib_rx_allocs = | |||||
iflib_fl_refills = iflib_fl_refills_large = iflib_tx_frees = | |||||
iflib_txq_drain_flushing = iflib_txq_drain_oactive = | |||||
iflib_txq_drain_notready = iflib_txq_drain_encapfail = | |||||
iflib_encap_load_mbuf_fail = iflib_encap_pad_mbuf_fail = | |||||
iflib_encap_txq_avail_fail = iflib_encap_txd_encap_fail = | |||||
iflib_task_fn_rxs = iflib_rx_intr_enables = iflib_fast_intrs = | |||||
iflib_intr_link = iflib_intr_msix = iflib_rx_unavail = | |||||
iflib_rx_ctx_inactive = iflib_rx_zero_len = iflib_rx_if_input = | |||||
iflib_rx_mbuf_null = iflib_rxd_flush = 0; | |||||
} | |||||
#else | #else | ||||
#define DBG_COUNTER_INC(name) | #define DBG_COUNTER_INC(name) | ||||
static void iflib_debug_reset(void) {} | |||||
#endif | #endif | ||||
#define IFLIB_DEBUG 0 | #define IFLIB_DEBUG 0 | ||||
static void iflib_tx_structures_free(if_ctx_t ctx); | static void iflib_tx_structures_free(if_ctx_t ctx); | ||||
static void iflib_rx_structures_free(if_ctx_t ctx); | static void iflib_rx_structures_free(if_ctx_t ctx); | ||||
static int iflib_queues_alloc(if_ctx_t ctx); | static int iflib_queues_alloc(if_ctx_t ctx); | ||||
static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); | static int iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq); | ||||
static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, int cidx, int budget); | static int iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget); | ||||
static int iflib_qset_structures_setup(if_ctx_t ctx); | static int iflib_qset_structures_setup(if_ctx_t ctx); | ||||
static int iflib_msix_init(if_ctx_t ctx); | static int iflib_msix_init(if_ctx_t ctx); | ||||
static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); | static int iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filterarg, int *rid, char *str); | ||||
static void iflib_txq_check_drain(iflib_txq_t txq, int budget); | static void iflib_txq_check_drain(iflib_txq_t txq, int budget); | ||||
static uint32_t iflib_txq_can_drain(struct ifmp_ring *); | static uint32_t iflib_txq_can_drain(struct ifmp_ring *); | ||||
static int iflib_register(if_ctx_t); | static int iflib_register(if_ctx_t); | ||||
static void iflib_init_locked(if_ctx_t ctx); | static void iflib_init_locked(if_ctx_t ctx); | ||||
static void iflib_add_device_sysctl_pre(if_ctx_t ctx); | static void iflib_add_device_sysctl_pre(if_ctx_t ctx); | ||||
static void iflib_add_device_sysctl_post(if_ctx_t ctx); | static void iflib_add_device_sysctl_post(if_ctx_t ctx); | ||||
static void iflib_ifmp_purge(iflib_txq_t txq); | |||||
static void _iflib_pre_assert(if_softc_ctx_t scctx); | |||||
static void iflib_stop(if_ctx_t ctx); | |||||
static void iflib_if_init_locked(if_ctx_t ctx); | |||||
#ifndef __NO_STRICT_ALIGNMENT | |||||
static struct mbuf * iflib_fixup_rx(struct mbuf *m); | |||||
#endif | |||||
#ifdef DEV_NETMAP | #ifdef DEV_NETMAP | ||||
#include <sys/selinfo.h> | #include <sys/selinfo.h> | ||||
#include <net/netmap.h> | #include <net/netmap.h> | ||||
#include <dev/netmap/netmap_kern.h> | #include <dev/netmap/netmap_kern.h> | ||||
MODULE_DEPEND(iflib, netmap, 1, 1, 1); | MODULE_DEPEND(iflib, netmap, 1, 1, 1); | ||||
static int netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init); | |||||
/* | /* | ||||
* device-specific sysctl variables: | * device-specific sysctl variables: | ||||
* | * | ||||
* iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. | * iflib_crcstrip: 0: keep CRC in rx frames (default), 1: strip it. | ||||
* During regular operations the CRC is stripped, but on some | * During regular operations the CRC is stripped, but on some | ||||
* hardware reception of frames not multiple of 64 is slower, | * hardware reception of frames not multiple of 64 is slower, | ||||
* so using crcstrip=0 helps in benchmarks. | * so using crcstrip=0 helps in benchmarks. | ||||
* | * | ||||
Show All 19 Lines | |||||
* Register/unregister. We are already under netmap lock. | * Register/unregister. We are already under netmap lock. | ||||
* Only called on the first register or the last unregister. | * Only called on the first register or the last unregister. | ||||
*/ | */ | ||||
static int | static int | ||||
iflib_netmap_register(struct netmap_adapter *na, int onoff) | iflib_netmap_register(struct netmap_adapter *na, int onoff) | ||||
{ | { | ||||
struct ifnet *ifp = na->ifp; | struct ifnet *ifp = na->ifp; | ||||
if_ctx_t ctx = ifp->if_softc; | if_ctx_t ctx = ifp->if_softc; | ||||
int status; | |||||
CTX_LOCK(ctx); | CTX_LOCK(ctx); | ||||
IFDI_INTR_DISABLE(ctx); | IFDI_INTR_DISABLE(ctx); | ||||
/* Tell the stack that the interface is no longer active */ | /* Tell the stack that the interface is no longer active */ | ||||
ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); | ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); | ||||
if (!CTX_IS_VF(ctx)) | if (!CTX_IS_VF(ctx)) | ||||
IFDI_CRCSTRIP_SET(ctx, onoff); | IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); | ||||
/* enable or disable flags and callbacks in na and ifp */ | /* enable or disable flags and callbacks in na and ifp */ | ||||
if (onoff) { | if (onoff) { | ||||
nm_set_native_flags(na); | nm_set_native_flags(na); | ||||
} else { | } else { | ||||
nm_clear_native_flags(na); | nm_clear_native_flags(na); | ||||
} | } | ||||
IFDI_INIT(ctx); | iflib_stop(ctx); | ||||
IFDI_CRCSTRIP_SET(ctx, onoff); // XXX why twice ? | iflib_init_locked(ctx); | ||||
IFDI_CRCSTRIP_SET(ctx, onoff, iflib_crcstrip); // XXX why twice ? | |||||
status = ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1; | |||||
if (status) | |||||
nm_clear_native_flags(na); | |||||
CTX_UNLOCK(ctx); | CTX_UNLOCK(ctx); | ||||
return (ifp->if_drv_flags & IFF_DRV_RUNNING ? 0 : 1); | return (status); | ||||
} | } | ||||
static int | |||||
netmap_fl_refill(iflib_rxq_t rxq, struct netmap_kring *kring, uint32_t nm_i, bool init) | |||||
{ | |||||
struct netmap_adapter *na = kring->na; | |||||
u_int const lim = kring->nkr_num_slots - 1; | |||||
u_int head = kring->rhead; | |||||
struct netmap_ring *ring = kring->ring; | |||||
bus_dmamap_t *map; | |||||
struct if_rxd_update iru; | |||||
if_ctx_t ctx = rxq->ifr_ctx; | |||||
iflib_fl_t fl = &rxq->ifr_fl[0]; | |||||
uint32_t refill_pidx, nic_i; | |||||
if (nm_i == head && __predict_true(!init)) | |||||
return 0; | |||||
iru_init(&iru, rxq, 0 /* flid */); | |||||
map = fl->ifl_sds.ifsd_map; | |||||
refill_pidx = netmap_idx_k2n(kring, nm_i); | |||||
/* | /* | ||||
* IMPORTANT: we must leave one free slot in the ring, | |||||
* so move head back by one unit | |||||
*/ | |||||
head = nm_prev(head, lim); | |||||
while (nm_i != head) { | |||||
for (int tmp_pidx = 0; tmp_pidx < IFLIB_MAX_RX_REFRESH && nm_i != head; tmp_pidx++) { | |||||
struct netmap_slot *slot = &ring->slot[nm_i]; | |||||
void *addr = PNMB(na, slot, &fl->ifl_bus_addrs[tmp_pidx]); | |||||
uint32_t nic_i_dma = refill_pidx; | |||||
nic_i = netmap_idx_k2n(kring, nm_i); | |||||
MPASS(tmp_pidx < IFLIB_MAX_RX_REFRESH); | |||||
if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ | |||||
return netmap_ring_reinit(kring); | |||||
fl->ifl_vm_addrs[tmp_pidx] = addr; | |||||
if (__predict_false(init) && map) { | |||||
netmap_load_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); | |||||
} else if (map && (slot->flags & NS_BUF_CHANGED)) { | |||||
/* buffer has changed, reload map */ | |||||
netmap_reload_map(na, fl->ifl_ifdi->idi_tag, map[nic_i], addr); | |||||
} | |||||
slot->flags &= ~NS_BUF_CHANGED; | |||||
nm_i = nm_next(nm_i, lim); | |||||
fl->ifl_rxd_idxs[tmp_pidx] = nic_i = nm_next(nic_i, lim); | |||||
if (nm_i != head && tmp_pidx < IFLIB_MAX_RX_REFRESH-1) | |||||
continue; | |||||
iru.iru_pidx = refill_pidx; | |||||
iru.iru_count = tmp_pidx+1; | |||||
ctx->isc_rxd_refill(ctx->ifc_softc, &iru); | |||||
refill_pidx = nic_i; | |||||
if (map == NULL) | |||||
continue; | |||||
for (int n = 0; n < iru.iru_count; n++) { | |||||
bus_dmamap_sync(fl->ifl_ifdi->idi_tag, map[nic_i_dma], | |||||
BUS_DMASYNC_PREREAD); | |||||
/* XXX - change this to not use the netmap func*/ | |||||
nic_i_dma = nm_next(nic_i_dma, lim); | |||||
} | |||||
} | |||||
} | |||||
kring->nr_hwcur = head; | |||||
if (map) | |||||
bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, | |||||
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); | |||||
ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); | |||||
return (0); | |||||
} | |||||
/* | |||||
* Reconcile kernel and user view of the transmit ring. | * Reconcile kernel and user view of the transmit ring. | ||||
* | * | ||||
* All information is in the kring. | * All information is in the kring. | ||||
* Userspace wants to send packets up to the one before kring->rhead, | * Userspace wants to send packets up to the one before kring->rhead, | ||||
* kernel knows kring->nr_hwcur is the first unsent packet. | * kernel knows kring->nr_hwcur is the first unsent packet. | ||||
* | * | ||||
* Here we push packets out (as many as possible), and possibly | * Here we push packets out (as many as possible), and possibly | ||||
* reclaim buffers from previously completed transmission. | * reclaim buffers from previously completed transmission. | ||||
Show All 19 Lines | iflib_netmap_txsync(struct netmap_kring *kring, int flags) | ||||
* interrupts on every tx packet are expensive so request | * interrupts on every tx packet are expensive so request | ||||
* them every half ring, or where NS_REPORT is set | * them every half ring, or where NS_REPORT is set | ||||
*/ | */ | ||||
u_int report_frequency = kring->nkr_num_slots >> 1; | u_int report_frequency = kring->nkr_num_slots >> 1; | ||||
/* device-specific */ | /* device-specific */ | ||||
if_ctx_t ctx = ifp->if_softc; | if_ctx_t ctx = ifp->if_softc; | ||||
iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; | iflib_txq_t txq = &ctx->ifc_txqs[kring->ring_id]; | ||||
pi.ipi_segs = txq->ift_segs; | if (txq->ift_sds.ifsd_map) | ||||
pi.ipi_qsidx = kring->ring_id; | |||||
pi.ipi_ndescs = 0; | |||||
bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, | bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, | ||||
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); | BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); | ||||
/* | /* | ||||
* First part: process new packets to send. | * First part: process new packets to send. | ||||
* nm_i is the current index in the netmap ring, | * nm_i is the current index in the netmap ring, | ||||
* nic_i is the corresponding index in the NIC ring. | * nic_i is the corresponding index in the NIC ring. | ||||
* | * | ||||
* If we have packets to send (nm_i != head) | * If we have packets to send (nm_i != head) | ||||
* iterate over the netmap ring, fetch length and update | * iterate over the netmap ring, fetch length and update | ||||
* the corresponding slot in the NIC ring. Some drivers also | * the corresponding slot in the NIC ring. Some drivers also | ||||
* need to update the buffer's physical address in the NIC slot | * need to update the buffer's physical address in the NIC slot | ||||
* even NS_BUF_CHANGED is not set (PNMB computes the addresses). | * even NS_BUF_CHANGED is not set (PNMB computes the addresses). | ||||
* | * | ||||
* The netmap_reload_map() calls is especially expensive, | * The netmap_reload_map() calls is especially expensive, | ||||
* even when (as in this case) the tag is 0, so do only | * even when (as in this case) the tag is 0, so do only | ||||
* when the buffer has actually changed. | * when the buffer has actually changed. | ||||
* | * | ||||
* If possible do not set the report/intr bit on all slots, | * If possible do not set the report/intr bit on all slots, | ||||
* but only a few times per ring or when NS_REPORT is set. | * but only a few times per ring or when NS_REPORT is set. | ||||
* | * | ||||
* Finally, on 10G and faster drivers, it might be useful | * Finally, on 10G and faster drivers, it might be useful | ||||
* to prefetch the next slot and txr entry. | * to prefetch the next slot and txr entry. | ||||
*/ | */ | ||||
nm_i = kring->nr_hwcur; | nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); | ||||
pkt_info_zero(&pi); | |||||
pi.ipi_segs = txq->ift_segs; | |||||
pi.ipi_qsidx = kring->ring_id; | |||||
if (nm_i != head) { /* we have new packets to send */ | if (nm_i != head) { /* we have new packets to send */ | ||||
nic_i = netmap_idx_k2n(kring, nm_i); | nic_i = netmap_idx_k2n(kring, nm_i); | ||||
__builtin_prefetch(&ring->slot[nm_i]); | __builtin_prefetch(&ring->slot[nm_i]); | ||||
__builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); | __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i]); | ||||
if (txq->ift_sds.ifsd_map) | |||||
__builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); | __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i]); | ||||
for (n = 0; nm_i != head; n++) { | for (n = 0; nm_i != head; n++) { | ||||
struct netmap_slot *slot = &ring->slot[nm_i]; | struct netmap_slot *slot = &ring->slot[nm_i]; | ||||
u_int len = slot->len; | u_int len = slot->len; | ||||
uint64_t paddr; | uint64_t paddr; | ||||
void *addr = PNMB(na, slot, &paddr); | void *addr = PNMB(na, slot, &paddr); | ||||
int flags = (slot->flags & NS_REPORT || | int flags = (slot->flags & NS_REPORT || | ||||
nic_i == 0 || nic_i == report_frequency) ? | nic_i == 0 || nic_i == report_frequency) ? | ||||
IPI_TX_INTR : 0; | IPI_TX_INTR : 0; | ||||
/* device-specific */ | /* device-specific */ | ||||
pi.ipi_len = len; | |||||
pi.ipi_segs[0].ds_addr = paddr; | |||||
pi.ipi_segs[0].ds_len = len; | |||||
pi.ipi_nsegs = 1; | |||||
pi.ipi_ndescs = 0; | |||||
pi.ipi_pidx = nic_i; | pi.ipi_pidx = nic_i; | ||||
pi.ipi_flags = flags; | pi.ipi_flags = flags; | ||||
/* Fill the slot in the NIC ring. */ | /* Fill the slot in the NIC ring. */ | ||||
ctx->isc_txd_encap(ctx->ifc_softc, &pi); | ctx->isc_txd_encap(ctx->ifc_softc, &pi); | ||||
/* prefetch for next round */ | /* prefetch for next round */ | ||||
__builtin_prefetch(&ring->slot[nm_i + 1]); | __builtin_prefetch(&ring->slot[nm_i + 1]); | ||||
__builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); | __builtin_prefetch(&txq->ift_sds.ifsd_m[nic_i + 1]); | ||||
if (txq->ift_sds.ifsd_map) { | |||||
__builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); | __builtin_prefetch(&txq->ift_sds.ifsd_map[nic_i + 1]); | ||||
NM_CHECK_ADDR_LEN(na, addr, len); | NM_CHECK_ADDR_LEN(na, addr, len); | ||||
if (slot->flags & NS_BUF_CHANGED) { | if (slot->flags & NS_BUF_CHANGED) { | ||||
/* buffer has changed, reload map */ | /* buffer has changed, reload map */ | ||||
netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); | netmap_reload_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[nic_i], addr); | ||||
} | } | ||||
slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); | |||||
/* make sure changes to the buffer are synced */ | /* make sure changes to the buffer are synced */ | ||||
bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], | bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_sds.ifsd_map[nic_i], | ||||
BUS_DMASYNC_PREWRITE); | BUS_DMASYNC_PREWRITE); | ||||
} | |||||
slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); | |||||
nm_i = nm_next(nm_i, lim); | nm_i = nm_next(nm_i, lim); | ||||
nic_i = nm_next(nic_i, lim); | nic_i = nm_next(nic_i, lim); | ||||
} | } | ||||
kring->nr_hwcur = head; | kring->nr_hwcur = head; | ||||
/* synchronize the NIC ring */ | /* synchronize the NIC ring */ | ||||
if (txq->ift_sds.ifsd_map) | |||||
bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, | bus_dmamap_sync(txq->ift_desc_tag, txq->ift_ifdi->idi_map, | ||||
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); | BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); | ||||
/* (re)start the tx unit up to slot nic_i (excluded) */ | /* (re)start the tx unit up to slot nic_i (excluded) */ | ||||
ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); | ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, nic_i); | ||||
} | } | ||||
/* | /* | ||||
* Second part: reclaim buffers for completed transmissions. | * Second part: reclaim buffers for completed transmissions. | ||||
Show All 18 Lines | |||||
* | * | ||||
* If (flags & NAF_FORCE_READ) also check for incoming packets irrespective | * If (flags & NAF_FORCE_READ) also check for incoming packets irrespective | ||||
* of whether or not we received an interrupt. | * of whether or not we received an interrupt. | ||||
*/ | */ | ||||
static int | static int | ||||
iflib_netmap_rxsync(struct netmap_kring *kring, int flags) | iflib_netmap_rxsync(struct netmap_kring *kring, int flags) | ||||
{ | { | ||||
struct netmap_adapter *na = kring->na; | struct netmap_adapter *na = kring->na; | ||||
struct ifnet *ifp = na->ifp; | |||||
struct netmap_ring *ring = kring->ring; | struct netmap_ring *ring = kring->ring; | ||||
u_int nm_i; /* index into the netmap ring */ | uint32_t nm_i; /* index into the netmap ring */ | ||||
u_int nic_i; /* index into the NIC ring */ | uint32_t nic_i; /* index into the NIC ring */ | ||||
u_int i, n; | u_int i, n; | ||||
u_int const lim = kring->nkr_num_slots - 1; | u_int const lim = kring->nkr_num_slots - 1; | ||||
u_int const head = kring->rhead; | u_int const head = netmap_idx_n2k(kring, kring->rhead); | ||||
int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; | int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; | ||||
struct if_rxd_info ri; | struct if_rxd_info ri; | ||||
/* device-specific */ | |||||
struct ifnet *ifp = na->ifp; | |||||
if_ctx_t ctx = ifp->if_softc; | if_ctx_t ctx = ifp->if_softc; | ||||
iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; | iflib_rxq_t rxq = &ctx->ifc_rxqs[kring->ring_id]; | ||||
iflib_fl_t fl = rxq->ifr_fl; | iflib_fl_t fl = rxq->ifr_fl; | ||||
if (head > lim) | if (head > lim) | ||||
return netmap_ring_reinit(kring); | return netmap_ring_reinit(kring); | ||||
bzero(&ri, sizeof(ri)); | |||||
ri.iri_qsidx = kring->ring_id; | |||||
ri.iri_ifp = ctx->ifc_ifp; | |||||
/* XXX check sync modes */ | /* XXX check sync modes */ | ||||
for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) | for (i = 0, fl = rxq->ifr_fl; i < rxq->ifr_nfl; i++, fl++) { | ||||
if (fl->ifl_sds.ifsd_map == NULL) | |||||
continue; | |||||
bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, | bus_dmamap_sync(rxq->ifr_fl[i].ifl_desc_tag, fl->ifl_ifdi->idi_map, | ||||
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); | BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); | ||||
} | |||||
/* | /* | ||||
* First part: import newly received packets. | * First part: import newly received packets. | ||||
* | * | ||||
* nm_i is the index of the next free slot in the netmap ring, | * nm_i is the index of the next free slot in the netmap ring, | ||||
* nic_i is the index of the next received packet in the NIC ring, | * nic_i is the index of the next received packet in the NIC ring, | ||||
* and they may differ in case if_init() has been called while | * and they may differ in case if_init() has been called while | ||||
* in netmap mode. For the receive ring we have | * in netmap mode. For the receive ring we have | ||||
* | * | ||||
* nic_i = rxr->next_check; | * nic_i = rxr->next_check; | ||||
* nm_i = kring->nr_hwtail (previous) | * nm_i = kring->nr_hwtail (previous) | ||||
* and | * and | ||||
* nm_i == (nic_i + kring->nkr_hwofs) % ring_size | * nm_i == (nic_i + kring->nkr_hwofs) % ring_size | ||||
* | * | ||||
* rxr->next_check is set to 0 on a ring reinit | * rxr->next_check is set to 0 on a ring reinit | ||||
*/ | */ | ||||
if (netmap_no_pendintr || force_update) { | if (netmap_no_pendintr || force_update) { | ||||
int crclen = iflib_crcstrip ? 0 : 4; | int crclen = iflib_crcstrip ? 0 : 4; | ||||
int error, avail; | int error, avail; | ||||
uint16_t slot_flags = kring->nkr_slot_flags; | uint16_t slot_flags = kring->nkr_slot_flags; | ||||
for (fl = rxq->ifr_fl, i = 0; i < rxq->ifr_nfl; i++, fl++) { | for (i = 0; i < rxq->ifr_nfl; i++) { | ||||
fl = &rxq->ifr_fl[i]; | |||||
nic_i = fl->ifl_cidx; | nic_i = fl->ifl_cidx; | ||||
nm_i = netmap_idx_n2k(kring, nic_i); | nm_i = netmap_idx_n2k(kring, nic_i); | ||||
avail = ctx->isc_rxd_available(ctx->ifc_softc, kring->ring_id, nic_i, INT_MAX); | avail = iflib_rxd_avail(ctx, rxq, nic_i, USHRT_MAX); | ||||
for (n = 0; avail > 0; n++, avail--) { | for (n = 0; avail > 0; n++, avail--) { | ||||
rxd_info_zero(&ri); | |||||
ri.iri_frags = rxq->ifr_frags; | |||||
ri.iri_qsidx = kring->ring_id; | |||||
ri.iri_ifp = ctx->ifc_ifp; | |||||
ri.iri_cidx = nic_i; | |||||
error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); | error = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); | ||||
if (error) | ring->slot[nm_i].len = error ? 0 : ri.iri_len - crclen; | ||||
ring->slot[nm_i].len = 0; | |||||
else | |||||
ring->slot[nm_i].len = ri.iri_len - crclen; | |||||
ring->slot[nm_i].flags = slot_flags; | ring->slot[nm_i].flags = slot_flags; | ||||
if (fl->ifl_sds.ifsd_map) | |||||
bus_dmamap_sync(fl->ifl_ifdi->idi_tag, | bus_dmamap_sync(fl->ifl_ifdi->idi_tag, | ||||
fl->ifl_sds[nic_i].ifsd_map, BUS_DMASYNC_POSTREAD); | fl->ifl_sds.ifsd_map[nic_i], BUS_DMASYNC_POSTREAD); | ||||
nm_i = nm_next(nm_i, lim); | nm_i = nm_next(nm_i, lim); | ||||
nic_i = nm_next(nic_i, lim); | nic_i = nm_next(nic_i, lim); | ||||
} | } | ||||
if (n) { /* update the state variables */ | if (n) { /* update the state variables */ | ||||
if (netmap_no_pendintr && !force_update) { | if (netmap_no_pendintr && !force_update) { | ||||
/* diagnostics */ | /* diagnostics */ | ||||
iflib_rx_miss ++; | iflib_rx_miss ++; | ||||
iflib_rx_miss_bufs += n; | iflib_rx_miss_bufs += n; | ||||
} | } | ||||
fl->ifl_cidx = nic_i; | fl->ifl_cidx = nic_i; | ||||
kring->nr_hwtail = nm_i; | kring->nr_hwtail = netmap_idx_k2n(kring, nm_i); | ||||
} | } | ||||
kring->nr_kflags &= ~NKR_PENDINTR; | kring->nr_kflags &= ~NKR_PENDINTR; | ||||
} | } | ||||
} | } | ||||
/* | /* | ||||
* Second part: skip past packets that userspace has released. | * Second part: skip past packets that userspace has released. | ||||
* (kring->nr_hwcur to head excluded), | * (kring->nr_hwcur to head excluded), | ||||
* and make the buffers available for reception. | * and make the buffers available for reception. | ||||
* As usual nm_i is the index in the netmap ring, | * As usual nm_i is the index in the netmap ring, | ||||
* nic_i is the index in the NIC ring, and | * nic_i is the index in the NIC ring, and | ||||
* nm_i == (nic_i + kring->nkr_hwofs) % ring_size | * nm_i == (nic_i + kring->nkr_hwofs) % ring_size | ||||
*/ | */ | ||||
/* XXX not sure how this will work with multiple free lists */ | /* XXX not sure how this will work with multiple free lists */ | ||||
nm_i = kring->nr_hwcur; | nm_i = netmap_idx_n2k(kring, kring->nr_hwcur); | ||||
if (nm_i != head) { | |||||
nic_i = netmap_idx_k2n(kring, nm_i); | |||||
for (n = 0; nm_i != head; n++) { | |||||
struct netmap_slot *slot = &ring->slot[nm_i]; | |||||
uint64_t paddr; | |||||
caddr_t vaddr; | |||||
void *addr = PNMB(na, slot, &paddr); | |||||
if (addr == NETMAP_BUF_BASE(na)) /* bad buf */ | return (netmap_fl_refill(rxq, kring, nm_i, false)); | ||||
goto ring_reset; | |||||
vaddr = addr; | |||||
if (slot->flags & NS_BUF_CHANGED) { | |||||
/* buffer has changed, reload map */ | |||||
netmap_reload_map(na, fl->ifl_ifdi->idi_tag, fl->ifl_sds[nic_i].ifsd_map, addr); | |||||
slot->flags &= ~NS_BUF_CHANGED; | |||||
} | } | ||||
/* | |||||
* XXX we should be batching this operation - TODO | |||||
*/ | |||||
ctx->isc_rxd_refill(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i, &paddr, &vaddr, 1, fl->ifl_buf_size); | |||||
bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_sds[nic_i].ifsd_map, | |||||
BUS_DMASYNC_PREREAD); | |||||
nm_i = nm_next(nm_i, lim); | |||||
nic_i = nm_next(nic_i, lim); | |||||
} | |||||
kring->nr_hwcur = head; | |||||
bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, | |||||
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); | |||||
/* | |||||
* IMPORTANT: we must leave one free slot in the ring, | |||||
* so move nic_i back by one unit | |||||
*/ | |||||
nic_i = nm_prev(nic_i, lim); | |||||
ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, fl->ifl_id, nic_i); | |||||
} | |||||
return 0; | |||||
ring_reset: | |||||
return netmap_ring_reinit(kring); | |||||
} | |||||
static int | static int | ||||
iflib_netmap_attach(if_ctx_t ctx) | iflib_netmap_attach(if_ctx_t ctx) | ||||
{ | { | ||||
struct netmap_adapter na; | struct netmap_adapter na; | ||||
if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; | if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; | ||||
bzero(&na, sizeof(na)); | bzero(&na, sizeof(na)); | ||||
Show All 16 Lines | |||||
iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) | iflib_netmap_txq_init(if_ctx_t ctx, iflib_txq_t txq) | ||||
{ | { | ||||
struct netmap_adapter *na = NA(ctx->ifc_ifp); | struct netmap_adapter *na = NA(ctx->ifc_ifp); | ||||
struct netmap_slot *slot; | struct netmap_slot *slot; | ||||
slot = netmap_reset(na, NR_TX, txq->ift_id, 0); | slot = netmap_reset(na, NR_TX, txq->ift_id, 0); | ||||
if (slot == NULL) | if (slot == NULL) | ||||
return; | return; | ||||
if (txq->ift_sds.ifsd_map == NULL) | |||||
return; | |||||
for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { | for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxd[0]; i++) { | ||||
/* | /* | ||||
* In netmap mode, set the map for the packet buffer. | * In netmap mode, set the map for the packet buffer. | ||||
* NOTE: Some drivers (not this one) also need to set | * NOTE: Some drivers (not this one) also need to set | ||||
* the physical buffer address in the NIC ring. | * the physical buffer address in the NIC ring. | ||||
* netmap_idx_n2k() maps a nic index, i, into the corresponding | * netmap_idx_n2k() maps a nic index, i, into the corresponding | ||||
* netmap slot index, si | * netmap slot index, si | ||||
*/ | */ | ||||
int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i); | int si = netmap_idx_n2k(&na->tx_rings[txq->ift_id], i); | ||||
netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); | netmap_load_map(na, txq->ift_desc_tag, txq->ift_sds.ifsd_map[i], NMB(na, slot + si)); | ||||
} | } | ||||
} | } | ||||
static void | static void | ||||
iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) | iflib_netmap_rxq_init(if_ctx_t ctx, iflib_rxq_t rxq) | ||||
{ | { | ||||
struct netmap_adapter *na = NA(ctx->ifc_ifp); | struct netmap_adapter *na = NA(ctx->ifc_ifp); | ||||
struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id]; | |||||
struct netmap_slot *slot; | struct netmap_slot *slot; | ||||
iflib_rxsd_t sd; | uint32_t nm_i; | ||||
int nrxd; | |||||
slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); | slot = netmap_reset(na, NR_RX, rxq->ifr_id, 0); | ||||
if (slot == NULL) | if (slot == NULL) | ||||
return; | return; | ||||
sd = rxq->ifr_fl[0].ifl_sds; | nm_i = netmap_idx_n2k(kring, 0); | ||||
nrxd = ctx->ifc_softc_ctx.isc_nrxd[0]; | netmap_fl_refill(rxq, kring, nm_i, true); | ||||
for (int i = 0; i < nrxd; i++, sd++) { | |||||
int sj = netmap_idx_n2k(&na->rx_rings[rxq->ifr_id], i); | |||||
uint64_t paddr; | |||||
void *addr; | |||||
caddr_t vaddr; | |||||
vaddr = addr = PNMB(na, slot + sj, &paddr); | |||||
netmap_load_map(na, rxq->ifr_fl[0].ifl_ifdi->idi_tag, sd->ifsd_map, addr); | |||||
/* Update descriptor and the cached value */ | |||||
ctx->isc_rxd_refill(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, i, &paddr, &vaddr, 1, rxq->ifr_fl[0].ifl_buf_size); | |||||
} | } | ||||
/* preserve queue */ | |||||
if (ctx->ifc_ifp->if_capenable & IFCAP_NETMAP) { | |||||
struct netmap_kring *kring = &na->rx_rings[rxq->ifr_id]; | |||||
int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring); | |||||
ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, t); | |||||
} else | |||||
ctx->isc_rxd_flush(ctx->ifc_softc, rxq->ifr_id, 0 /* fl_id */, nrxd-1); | |||||
} | |||||
#define iflib_netmap_detach(ifp) netmap_detach(ifp) | #define iflib_netmap_detach(ifp) netmap_detach(ifp) | ||||
#else | #else | ||||
#define iflib_netmap_txq_init(ctx, txq) | #define iflib_netmap_txq_init(ctx, txq) | ||||
#define iflib_netmap_rxq_init(ctx, rxq) | #define iflib_netmap_rxq_init(ctx, rxq) | ||||
#define iflib_netmap_detach(ifp) | #define iflib_netmap_detach(ifp) | ||||
#define iflib_netmap_attach(ctx) (0) | #define iflib_netmap_attach(ctx) (0) | ||||
#define netmap_rx_irq(ifp, qid, budget) (0) | #define netmap_rx_irq(ifp, qid, budget) (0) | ||||
#define netmap_tx_irq(ifp, qid) do {} while (0) | |||||
#endif | #endif | ||||
#if defined(__i386__) || defined(__amd64__) | #if defined(__i386__) || defined(__amd64__) | ||||
static __inline void | static __inline void | ||||
prefetch(void *x) | prefetch(void *x) | ||||
{ | { | ||||
__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); | __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); | ||||
} | } | ||||
static __inline void | |||||
prefetch2cachelines(void *x) | |||||
{ | |||||
__asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); | |||||
#if (CACHE_LINE_SIZE < 128) | |||||
__asm volatile("prefetcht0 %0" :: "m" (*(((unsigned long *)x)+CACHE_LINE_SIZE/(sizeof(unsigned long))))); | |||||
#endif | |||||
} | |||||
#else | #else | ||||
#define prefetch(x) | #define prefetch(x) | ||||
#define prefetch2cachelines(x) | |||||
#endif | #endif | ||||
static void | static void | ||||
iru_init(if_rxd_update_t iru, iflib_rxq_t rxq, uint8_t flid) | |||||
{ | |||||
iflib_fl_t fl; | |||||
fl = &rxq->ifr_fl[flid]; | |||||
iru->iru_paddrs = fl->ifl_bus_addrs; | |||||
iru->iru_vaddrs = &fl->ifl_vm_addrs[0]; | |||||
iru->iru_idxs = fl->ifl_rxd_idxs; | |||||
iru->iru_qsidx = rxq->ifr_id; | |||||
iru->iru_buf_size = fl->ifl_buf_size; | |||||
iru->iru_flidx = fl->ifl_id; | |||||
} | |||||
static void | |||||
_iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) | _iflib_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) | ||||
{ | { | ||||
if (err) | if (err) | ||||
return; | return; | ||||
*(bus_addr_t *) arg = segs[0].ds_addr; | *(bus_addr_t *) arg = segs[0].ds_addr; | ||||
} | } | ||||
int | int | ||||
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines | |||||
{ | { | ||||
int i; | int i; | ||||
iflib_dma_info_t *dmaiter = dmalist; | iflib_dma_info_t *dmaiter = dmalist; | ||||
for (i = 0; i < count; i++, dmaiter++) | for (i = 0; i < count; i++, dmaiter++) | ||||
iflib_dma_free(*dmaiter); | iflib_dma_free(*dmaiter); | ||||
} | } | ||||
#ifdef EARLY_AP_STARTUP | |||||
static const int iflib_started = 1; | |||||
#else | |||||
/* | |||||
* We used to abuse the smp_started flag to decide if the queues have been | |||||
* fully initialized (by late taskqgroup_adjust() calls in a SYSINIT()). | |||||
* That gave bad races, since the SYSINIT() runs strictly after smp_started | |||||
* is set. Run a SYSINIT() strictly after that to just set a usable | |||||
* completion flag. | |||||
*/ | |||||
static int iflib_started; | |||||
static void | |||||
iflib_record_started(void *arg) | |||||
{ | |||||
iflib_started = 1; | |||||
} | |||||
SYSINIT(iflib_record_started, SI_SUB_SMP + 1, SI_ORDER_FIRST, | |||||
iflib_record_started, NULL); | |||||
#endif | |||||
static int | static int | ||||
iflib_fast_intr(void *arg) | iflib_fast_intr(void *arg) | ||||
{ | { | ||||
iflib_filter_info_t info = arg; | iflib_filter_info_t info = arg; | ||||
struct grouptask *gtask = info->ifi_task; | struct grouptask *gtask = info->ifi_task; | ||||
if (!iflib_started) | |||||
return (FILTER_HANDLED); | |||||
DBG_COUNTER_INC(fast_intrs); | DBG_COUNTER_INC(fast_intrs); | ||||
if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) | if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) | ||||
return (FILTER_HANDLED); | return (FILTER_HANDLED); | ||||
GROUPTASK_ENQUEUE(gtask); | GROUPTASK_ENQUEUE(gtask); | ||||
return (FILTER_HANDLED); | return (FILTER_HANDLED); | ||||
} | } | ||||
static int | static int | ||||
iflib_fast_intr_rxtx(void *arg) | |||||
{ | |||||
iflib_filter_info_t info = arg; | |||||
struct grouptask *gtask = info->ifi_task; | |||||
iflib_rxq_t rxq = (iflib_rxq_t)info->ifi_ctx; | |||||
if_ctx_t ctx; | |||||
int i, cidx; | |||||
if (!iflib_started) | |||||
return (FILTER_HANDLED); | |||||
DBG_COUNTER_INC(fast_intrs); | |||||
if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) | |||||
return (FILTER_HANDLED); | |||||
for (i = 0; i < rxq->ifr_ntxqirq; i++) { | |||||
qidx_t txqid = rxq->ifr_txqid[i]; | |||||
ctx = rxq->ifr_ctx; | |||||
if (!ctx->isc_txd_credits_update(ctx->ifc_softc, txqid, false)) { | |||||
IFDI_TX_QUEUE_INTR_ENABLE(ctx, txqid); | |||||
continue; | |||||
} | |||||
GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); | |||||
} | |||||
if (ctx->ifc_sctx->isc_flags & IFLIB_HAS_RXCQ) | |||||
cidx = rxq->ifr_cq_cidx; | |||||
else | |||||
cidx = rxq->ifr_fl[0].ifl_cidx; | |||||
if (iflib_rxd_avail(ctx, rxq, cidx, 1)) | |||||
GROUPTASK_ENQUEUE(gtask); | |||||
else | |||||
IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); | |||||
return (FILTER_HANDLED); | |||||
} | |||||
static int | |||||
iflib_fast_intr_ctx(void *arg) | |||||
{ | |||||
iflib_filter_info_t info = arg; | |||||
struct grouptask *gtask = info->ifi_task; | |||||
if (!iflib_started) | |||||
return (FILTER_HANDLED); | |||||
DBG_COUNTER_INC(fast_intrs); | |||||
if (info->ifi_filter != NULL && info->ifi_filter(info->ifi_filter_arg) == FILTER_HANDLED) | |||||
return (FILTER_HANDLED); | |||||
GROUPTASK_ENQUEUE(gtask); | |||||
return (FILTER_HANDLED); | |||||
} | |||||
static int | |||||
_iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, | _iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, | ||||
driver_filter_t filter, driver_intr_t handler, void *arg, | driver_filter_t filter, driver_intr_t handler, void *arg, | ||||
char *name) | char *name) | ||||
{ | { | ||||
int rc; | int rc, flags; | ||||
struct resource *res; | struct resource *res; | ||||
void *tag; | void *tag = NULL; | ||||
device_t dev = ctx->ifc_dev; | device_t dev = ctx->ifc_dev; | ||||
flags = RF_ACTIVE; | |||||
if (ctx->ifc_flags & IFC_LEGACY) | |||||
flags |= RF_SHAREABLE; | |||||
MPASS(rid < 512); | MPASS(rid < 512); | ||||
irq->ii_rid = rid; | irq->ii_rid = rid; | ||||
res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, | res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq->ii_rid, flags); | ||||
RF_SHAREABLE | RF_ACTIVE); | |||||
if (res == NULL) { | if (res == NULL) { | ||||
device_printf(dev, | device_printf(dev, | ||||
"failed to allocate IRQ for rid %d, name %s.\n", rid, name); | "failed to allocate IRQ for rid %d, name %s.\n", rid, name); | ||||
return (ENOMEM); | return (ENOMEM); | ||||
} | } | ||||
irq->ii_res = res; | irq->ii_res = res; | ||||
KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); | KASSERT(filter == NULL || handler == NULL, ("filter and handler can't both be non-NULL")); | ||||
rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, | rc = bus_setup_intr(dev, res, INTR_MPSAFE | INTR_TYPE_NET, | ||||
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines | if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), | ||||
NULL, /* lockfunc */ | NULL, /* lockfunc */ | ||||
NULL, /* lockfuncarg */ | NULL, /* lockfuncarg */ | ||||
&txq->ift_desc_tag))) { | &txq->ift_desc_tag))) { | ||||
device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); | device_printf(dev,"Unable to allocate TX DMA tag: %d\n", err); | ||||
device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", | device_printf(dev,"maxsize: %ju nsegments: %d maxsegsize: %ju\n", | ||||
(uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); | (uintmax_t)sctx->isc_tx_maxsize, nsegments, (uintmax_t)sctx->isc_tx_maxsegsize); | ||||
goto fail; | goto fail; | ||||
} | } | ||||
#ifdef IFLIB_DIAGNOSTICS | |||||
device_printf(dev,"maxsize: %zd nsegments: %d maxsegsize: %zd\n", | |||||
sctx->isc_tx_maxsize, nsegments, sctx->isc_tx_maxsegsize); | |||||
#endif | |||||
if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), | if ((err = bus_dma_tag_create(bus_get_dma_tag(dev), | ||||
1, 0, /* alignment, bounds */ | 1, 0, /* alignment, bounds */ | ||||
BUS_SPACE_MAXADDR, /* lowaddr */ | BUS_SPACE_MAXADDR, /* lowaddr */ | ||||
BUS_SPACE_MAXADDR, /* highaddr */ | BUS_SPACE_MAXADDR, /* highaddr */ | ||||
NULL, NULL, /* filter, filterarg */ | NULL, NULL, /* filter, filterarg */ | ||||
scctx->isc_tx_tso_size_max, /* maxsize */ | scctx->isc_tx_tso_size_max, /* maxsize */ | ||||
ntsosegments, /* nsegments */ | ntsosegments, /* nsegments */ | ||||
scctx->isc_tx_tso_segsize_max, /* maxsegsize */ | scctx->isc_tx_tso_segsize_max, /* maxsegsize */ | ||||
0, /* flags */ | 0, /* flags */ | ||||
NULL, /* lockfunc */ | NULL, /* lockfunc */ | ||||
NULL, /* lockfuncarg */ | NULL, /* lockfuncarg */ | ||||
&txq->ift_tso_desc_tag))) { | &txq->ift_tso_desc_tag))) { | ||||
device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); | device_printf(dev,"Unable to allocate TX TSO DMA tag: %d\n", err); | ||||
goto fail; | goto fail; | ||||
} | } | ||||
#ifdef IFLIB_DIAGNOSTICS | |||||
device_printf(dev,"TSO maxsize: %d ntsosegments: %d maxsegsize: %d\n", | |||||
scctx->isc_tx_tso_size_max, ntsosegments, | |||||
scctx->isc_tx_tso_segsize_max); | |||||
#endif | |||||
if (!(txq->ift_sds.ifsd_flags = | if (!(txq->ift_sds.ifsd_flags = | ||||
(uint8_t *) malloc(sizeof(uint8_t) * | (uint8_t *) malloc(sizeof(uint8_t) * | ||||
scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { | scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { | ||||
device_printf(dev, "Unable to allocate tx_buffer memory\n"); | device_printf(dev, "Unable to allocate tx_buffer memory\n"); | ||||
err = ENOMEM; | err = ENOMEM; | ||||
goto fail; | goto fail; | ||||
} | } | ||||
if (!(txq->ift_sds.ifsd_m = | if (!(txq->ift_sds.ifsd_m = | ||||
(struct mbuf **) malloc(sizeof(struct mbuf *) * | (struct mbuf **) malloc(sizeof(struct mbuf *) * | ||||
scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { | scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { | ||||
device_printf(dev, "Unable to allocate tx_buffer memory\n"); | device_printf(dev, "Unable to allocate tx_buffer memory\n"); | ||||
err = ENOMEM; | err = ENOMEM; | ||||
goto fail; | goto fail; | ||||
} | } | ||||
/* Create the descriptor buffer dma maps */ | /* Create the descriptor buffer dma maps */ | ||||
#if defined(ACPI_DMAR) || (!(defined(__i386__) && !defined(__amd64__))) | #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) | ||||
if ((ctx->ifc_flags & IFC_DMAR) == 0) | if ((ctx->ifc_flags & IFC_DMAR) == 0) | ||||
return (0); | return (0); | ||||
if (!(txq->ift_sds.ifsd_map = | if (!(txq->ift_sds.ifsd_map = | ||||
(bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { | (bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_ntxd[txq->ift_br_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { | ||||
device_printf(dev, "Unable to allocate tx_buffer map memory\n"); | device_printf(dev, "Unable to allocate tx_buffer map memory\n"); | ||||
err = ENOMEM; | err = ENOMEM; | ||||
goto fail; | goto fail; | ||||
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines | |||||
static int | static int | ||||
iflib_txq_setup(iflib_txq_t txq) | iflib_txq_setup(iflib_txq_t txq) | ||||
{ | { | ||||
if_ctx_t ctx = txq->ift_ctx; | if_ctx_t ctx = txq->ift_ctx; | ||||
if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; | if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; | ||||
iflib_dma_info_t di; | iflib_dma_info_t di; | ||||
int i; | int i; | ||||
/* Set number of descriptors available */ | /* Set number of descriptors available */ | ||||
txq->ift_qstatus = IFLIB_QUEUE_IDLE; | txq->ift_qstatus = IFLIB_QUEUE_IDLE; | ||||
/* XXX make configurable */ | |||||
txq->ift_update_freq = IFLIB_DEFAULT_TX_UPDATE_FREQ; | |||||
/* Reset indices */ | /* Reset indices */ | ||||
txq->ift_cidx_processed = txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; | txq->ift_cidx_processed = 0; | ||||
txq->ift_pidx = txq->ift_cidx = txq->ift_npending = 0; | |||||
txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; | txq->ift_size = scctx->isc_ntxd[txq->ift_br_offset]; | ||||
for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) | for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) | ||||
bzero((void *)di->idi_vaddr, di->idi_size); | bzero((void *)di->idi_vaddr, di->idi_size); | ||||
IFDI_TXQ_SETUP(ctx, txq->ift_id); | IFDI_TXQ_SETUP(ctx, txq->ift_id); | ||||
for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) | for (i = 0, di = txq->ift_ifdi; i < ctx->ifc_nhwtxqs; i++, di++) | ||||
bus_dmamap_sync(di->idi_tag, di->idi_map, | bus_dmamap_sync(di->idi_tag, di->idi_map, | ||||
Show All 12 Lines | |||||
static int | static int | ||||
iflib_rxsd_alloc(iflib_rxq_t rxq) | iflib_rxsd_alloc(iflib_rxq_t rxq) | ||||
{ | { | ||||
if_ctx_t ctx = rxq->ifr_ctx; | if_ctx_t ctx = rxq->ifr_ctx; | ||||
if_shared_ctx_t sctx = ctx->ifc_sctx; | if_shared_ctx_t sctx = ctx->ifc_sctx; | ||||
if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; | if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; | ||||
device_t dev = ctx->ifc_dev; | device_t dev = ctx->ifc_dev; | ||||
iflib_fl_t fl; | iflib_fl_t fl; | ||||
iflib_rxsd_t rxsd; | |||||
int err; | int err; | ||||
MPASS(scctx->isc_nrxd[0] > 0); | MPASS(scctx->isc_nrxd[0] > 0); | ||||
MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); | MPASS(scctx->isc_nrxd[rxq->ifr_fl_offset] > 0); | ||||
fl = rxq->ifr_fl; | fl = rxq->ifr_fl; | ||||
for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { | for (int i = 0; i < rxq->ifr_nfl; i++, fl++) { | ||||
fl->ifl_sds = malloc(sizeof(struct iflib_sw_rx_desc) * | |||||
scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, | |||||
M_WAITOK | M_ZERO); | |||||
if (fl->ifl_sds == NULL) { | |||||
device_printf(dev, "Unable to allocate rx sw desc memory\n"); | |||||
return (ENOMEM); | |||||
} | |||||
fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ | fl->ifl_size = scctx->isc_nrxd[rxq->ifr_fl_offset]; /* this isn't necessarily the same */ | ||||
err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ | err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ | ||||
1, 0, /* alignment, bounds */ | 1, 0, /* alignment, bounds */ | ||||
BUS_SPACE_MAXADDR, /* lowaddr */ | BUS_SPACE_MAXADDR, /* lowaddr */ | ||||
BUS_SPACE_MAXADDR, /* highaddr */ | BUS_SPACE_MAXADDR, /* highaddr */ | ||||
NULL, NULL, /* filter, filterarg */ | NULL, NULL, /* filter, filterarg */ | ||||
sctx->isc_rx_maxsize, /* maxsize */ | sctx->isc_rx_maxsize, /* maxsize */ | ||||
sctx->isc_rx_nsegments, /* nsegments */ | sctx->isc_rx_nsegments, /* nsegments */ | ||||
sctx->isc_rx_maxsegsize, /* maxsegsize */ | sctx->isc_rx_maxsegsize, /* maxsegsize */ | ||||
0, /* flags */ | 0, /* flags */ | ||||
NULL, /* lockfunc */ | NULL, /* lockfunc */ | ||||
NULL, /* lockarg */ | NULL, /* lockarg */ | ||||
&fl->ifl_desc_tag); | &fl->ifl_desc_tag); | ||||
if (err) { | if (err) { | ||||
device_printf(dev, "%s: bus_dma_tag_create failed %d\n", | device_printf(dev, "%s: bus_dma_tag_create failed %d\n", | ||||
__func__, err); | __func__, err); | ||||
goto fail; | goto fail; | ||||
} | } | ||||
if (!(fl->ifl_sds.ifsd_flags = | |||||
(uint8_t *) malloc(sizeof(uint8_t) * | |||||
scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { | |||||
device_printf(dev, "Unable to allocate tx_buffer memory\n"); | |||||
err = ENOMEM; | |||||
goto fail; | |||||
} | |||||
if (!(fl->ifl_sds.ifsd_m = | |||||
(struct mbuf **) malloc(sizeof(struct mbuf *) * | |||||
scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { | |||||
device_printf(dev, "Unable to allocate tx_buffer memory\n"); | |||||
err = ENOMEM; | |||||
goto fail; | |||||
} | |||||
if (!(fl->ifl_sds.ifsd_cl = | |||||
(caddr_t *) malloc(sizeof(caddr_t) * | |||||
scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { | |||||
device_printf(dev, "Unable to allocate tx_buffer memory\n"); | |||||
err = ENOMEM; | |||||
goto fail; | |||||
} | |||||
rxsd = fl->ifl_sds; | /* Create the descriptor buffer dma maps */ | ||||
for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++, rxsd++) { | #if defined(ACPI_DMAR) || (! (defined(__i386__) || defined(__amd64__))) | ||||
err = bus_dmamap_create(fl->ifl_desc_tag, 0, &rxsd->ifsd_map); | if ((ctx->ifc_flags & IFC_DMAR) == 0) | ||||
if (err) { | continue; | ||||
device_printf(dev, "%s: bus_dmamap_create failed: %d\n", | |||||
__func__, err); | if (!(fl->ifl_sds.ifsd_map = | ||||
(bus_dmamap_t *) malloc(sizeof(bus_dmamap_t) * scctx->isc_nrxd[rxq->ifr_fl_offset], M_IFLIB, M_NOWAIT | M_ZERO))) { | |||||
device_printf(dev, "Unable to allocate tx_buffer map memory\n"); | |||||
err = ENOMEM; | |||||
goto fail; | goto fail; | ||||
} | } | ||||
for (int i = 0; i < scctx->isc_nrxd[rxq->ifr_fl_offset]; i++) { | |||||
err = bus_dmamap_create(fl->ifl_desc_tag, 0, &fl->ifl_sds.ifsd_map[i]); | |||||
if (err != 0) { | |||||
device_printf(dev, "Unable to create RX buffer DMA map\n"); | |||||
goto fail; | |||||
} | } | ||||
} | } | ||||
#endif | |||||
} | |||||
return (0); | return (0); | ||||
fail: | fail: | ||||
iflib_rx_structures_free(ctx); | iflib_rx_structures_free(ctx); | ||||
return (err); | return (err); | ||||
} | } | ||||
Show All 32 Lines | |||||
* | * | ||||
* (Re)populate an rxq free-buffer list with up to @n new packet buffers. | * (Re)populate an rxq free-buffer list with up to @n new packet buffers. | ||||
* The caller must assure that @n does not exceed the queue's capacity. | * The caller must assure that @n does not exceed the queue's capacity. | ||||
*/ | */ | ||||
static void | static void | ||||
_iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) | _iflib_fl_refill(if_ctx_t ctx, iflib_fl_t fl, int count) | ||||
{ | { | ||||
struct mbuf *m; | struct mbuf *m; | ||||
int idx, frag_idx = fl->ifl_fragidx; | |||||
int pidx = fl->ifl_pidx; | int pidx = fl->ifl_pidx; | ||||
iflib_rxsd_t rxsd = &fl->ifl_sds[pidx]; | caddr_t cl, *sd_cl; | ||||
caddr_t cl; | struct mbuf **sd_m; | ||||
uint8_t *sd_flags; | |||||
struct if_rxd_update iru; | |||||
bus_dmamap_t *sd_map; | |||||
int n, i = 0; | int n, i = 0; | ||||
uint64_t bus_addr; | uint64_t bus_addr; | ||||
int err; | int err; | ||||
qidx_t credits; | |||||
sd_m = fl->ifl_sds.ifsd_m; | |||||
sd_map = fl->ifl_sds.ifsd_map; | |||||
sd_cl = fl->ifl_sds.ifsd_cl; | |||||
sd_flags = fl->ifl_sds.ifsd_flags; | |||||
idx = pidx; | |||||
credits = fl->ifl_credits; | |||||
n = count; | n = count; | ||||
MPASS(n > 0); | MPASS(n > 0); | ||||
MPASS(fl->ifl_credits + n <= fl->ifl_size); | MPASS(credits + n <= fl->ifl_size); | ||||
if (pidx < fl->ifl_cidx) | if (pidx < fl->ifl_cidx) | ||||
MPASS(pidx + n <= fl->ifl_cidx); | MPASS(pidx + n <= fl->ifl_cidx); | ||||
if (pidx == fl->ifl_cidx && (fl->ifl_credits < fl->ifl_size)) | if (pidx == fl->ifl_cidx && (credits < fl->ifl_size)) | ||||
MPASS(fl->ifl_gen == 0); | MPASS(fl->ifl_gen == 0); | ||||
if (pidx > fl->ifl_cidx) | if (pidx > fl->ifl_cidx) | ||||
MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); | MPASS(n <= fl->ifl_size - pidx + fl->ifl_cidx); | ||||
DBG_COUNTER_INC(fl_refills); | DBG_COUNTER_INC(fl_refills); | ||||
if (n > 8) | if (n > 8) | ||||
DBG_COUNTER_INC(fl_refills_large); | DBG_COUNTER_INC(fl_refills_large); | ||||
iru_init(&iru, fl->ifl_rxq, fl->ifl_id); | |||||
while (n--) { | while (n--) { | ||||
/* | /* | ||||
* We allocate an uninitialized mbuf + cluster, mbuf is | * We allocate an uninitialized mbuf + cluster, mbuf is | ||||
* initialized after rx. | * initialized after rx. | ||||
* | * | ||||
* If the cluster is still set then we know a minimum sized packet was received | * If the cluster is still set then we know a minimum sized packet was received | ||||
*/ | */ | ||||
if ((cl = rxsd->ifsd_cl) == NULL) { | bit_ffc_at(fl->ifl_rx_bitmap, frag_idx, fl->ifl_size, &frag_idx); | ||||
if ((cl = rxsd->ifsd_cl = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) | if ((frag_idx < 0) || (frag_idx >= fl->ifl_size)) | ||||
bit_ffc(fl->ifl_rx_bitmap, fl->ifl_size, &frag_idx); | |||||
if ((cl = sd_cl[frag_idx]) == NULL) { | |||||
if ((cl = sd_cl[frag_idx] = m_cljget(NULL, M_NOWAIT, fl->ifl_buf_size)) == NULL) | |||||
break; | break; | ||||
#if MEMORY_LOGGING | #if MEMORY_LOGGING | ||||
fl->ifl_cl_enqueued++; | fl->ifl_cl_enqueued++; | ||||
#endif | #endif | ||||
} | } | ||||
if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { | if ((m = m_gethdr(M_NOWAIT, MT_NOINIT)) == NULL) { | ||||
break; | break; | ||||
} | } | ||||
#if MEMORY_LOGGING | #if MEMORY_LOGGING | ||||
fl->ifl_m_enqueued++; | fl->ifl_m_enqueued++; | ||||
#endif | #endif | ||||
DBG_COUNTER_INC(rx_allocs); | DBG_COUNTER_INC(rx_allocs); | ||||
#ifdef notyet | |||||
if ((rxsd->ifsd_flags & RX_SW_DESC_MAP_CREATED) == 0) { | |||||
int err; | |||||
if ((err = bus_dmamap_create(fl->ifl_ifdi->idi_tag, 0, &rxsd->ifsd_map))) { | |||||
log(LOG_WARNING, "bus_dmamap_create failed %d\n", err); | |||||
uma_zfree(fl->ifl_zone, cl); | |||||
n = 0; | |||||
goto done; | |||||
} | |||||
rxsd->ifsd_flags |= RX_SW_DESC_MAP_CREATED; | |||||
} | |||||
#endif | |||||
#if defined(__i386__) || defined(__amd64__) | #if defined(__i386__) || defined(__amd64__) | ||||
if (!IS_DMAR(ctx)) { | if (!IS_DMAR(ctx)) { | ||||
bus_addr = pmap_kextract((vm_offset_t)cl); | bus_addr = pmap_kextract((vm_offset_t)cl); | ||||
} else | } else | ||||
#endif | #endif | ||||
{ | { | ||||
struct rxq_refill_cb_arg cb_arg; | struct rxq_refill_cb_arg cb_arg; | ||||
iflib_rxq_t q; | iflib_rxq_t q; | ||||
cb_arg.error = 0; | cb_arg.error = 0; | ||||
q = fl->ifl_rxq; | q = fl->ifl_rxq; | ||||
err = bus_dmamap_load(fl->ifl_desc_tag, rxsd->ifsd_map, | MPASS(sd_map != NULL); | ||||
MPASS(sd_map[frag_idx] != NULL); | |||||
err = bus_dmamap_load(fl->ifl_desc_tag, sd_map[frag_idx], | |||||
cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); | cl, fl->ifl_buf_size, _rxq_refill_cb, &cb_arg, 0); | ||||
bus_dmamap_sync(fl->ifl_desc_tag, sd_map[frag_idx], | |||||
BUS_DMASYNC_PREREAD); | |||||
if (err != 0 || cb_arg.error) { | if (err != 0 || cb_arg.error) { | ||||
/* | /* | ||||
* !zone_pack ? | * !zone_pack ? | ||||
*/ | */ | ||||
if (fl->ifl_zone == zone_pack) | if (fl->ifl_zone == zone_pack) | ||||
uma_zfree(fl->ifl_zone, cl); | uma_zfree(fl->ifl_zone, cl); | ||||
m_free(m); | m_free(m); | ||||
n = 0; | n = 0; | ||||
goto done; | goto done; | ||||
} | } | ||||
bus_addr = cb_arg.seg.ds_addr; | bus_addr = cb_arg.seg.ds_addr; | ||||
} | } | ||||
rxsd->ifsd_flags |= RX_SW_DESC_INUSE; | bit_set(fl->ifl_rx_bitmap, frag_idx); | ||||
sd_flags[frag_idx] |= RX_SW_DESC_INUSE; | |||||
MPASS(rxsd->ifsd_m == NULL); | MPASS(sd_m[frag_idx] == NULL); | ||||
rxsd->ifsd_cl = cl; | sd_cl[frag_idx] = cl; | ||||
rxsd->ifsd_m = m; | sd_m[frag_idx] = m; | ||||
fl->ifl_rxd_idxs[i] = frag_idx; | |||||
fl->ifl_bus_addrs[i] = bus_addr; | fl->ifl_bus_addrs[i] = bus_addr; | ||||
fl->ifl_vm_addrs[i] = cl; | fl->ifl_vm_addrs[i] = cl; | ||||
rxsd++; | credits++; | ||||
fl->ifl_credits++; | |||||
i++; | i++; | ||||
MPASS(fl->ifl_credits <= fl->ifl_size); | MPASS(credits <= fl->ifl_size); | ||||
if (++fl->ifl_pidx == fl->ifl_size) { | if (++idx == fl->ifl_size) { | ||||
fl->ifl_pidx = 0; | |||||
fl->ifl_gen = 1; | fl->ifl_gen = 1; | ||||
rxsd = fl->ifl_sds; | idx = 0; | ||||
} | } | ||||
if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { | if (n == 0 || i == IFLIB_MAX_RX_REFRESH) { | ||||
ctx->isc_rxd_refill(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx, | iru.iru_pidx = pidx; | ||||
fl->ifl_bus_addrs, fl->ifl_vm_addrs, i, fl->ifl_buf_size); | iru.iru_count = i; | ||||
ctx->isc_rxd_refill(ctx->ifc_softc, &iru); | |||||
i = 0; | i = 0; | ||||
pidx = fl->ifl_pidx; | pidx = idx; | ||||
fl->ifl_pidx = idx; | |||||
fl->ifl_credits = credits; | |||||
} | } | ||||
} | } | ||||
done: | done: | ||||
if (i) { | |||||
iru.iru_pidx = pidx; | |||||
iru.iru_count = i; | |||||
ctx->isc_rxd_refill(ctx->ifc_softc, &iru); | |||||
fl->ifl_pidx = idx; | |||||
fl->ifl_credits = credits; | |||||
} | |||||
DBG_COUNTER_INC(rxd_flush); | DBG_COUNTER_INC(rxd_flush); | ||||
if (fl->ifl_pidx == 0) | if (fl->ifl_pidx == 0) | ||||
pidx = fl->ifl_size - 1; | pidx = fl->ifl_size - 1; | ||||
else | else | ||||
pidx = fl->ifl_pidx - 1; | pidx = fl->ifl_pidx - 1; | ||||
if (sd_map) | |||||
bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, | |||||
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); | |||||
ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); | ctx->isc_rxd_flush(ctx->ifc_softc, fl->ifl_rxq->ifr_id, fl->ifl_id, pidx); | ||||
fl->ifl_fragidx = frag_idx; | |||||
} | } | ||||
static __inline void | static __inline void | ||||
__iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) | __iflib_fl_refill_lt(if_ctx_t ctx, iflib_fl_t fl, int max) | ||||
{ | { | ||||
/* we avoid allowing pidx to catch up with cidx as it confuses ixl */ | /* we avoid allowing pidx to catch up with cidx as it confuses ixl */ | ||||
int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; | int32_t reclaimable = fl->ifl_size - fl->ifl_credits - 1; | ||||
#ifdef INVARIANTS | #ifdef INVARIANTS | ||||
Show All 9 Lines | |||||
static void | static void | ||||
iflib_fl_bufs_free(iflib_fl_t fl) | iflib_fl_bufs_free(iflib_fl_t fl) | ||||
{ | { | ||||
iflib_dma_info_t idi = fl->ifl_ifdi; | iflib_dma_info_t idi = fl->ifl_ifdi; | ||||
uint32_t i; | uint32_t i; | ||||
for (i = 0; i < fl->ifl_size; i++) { | for (i = 0; i < fl->ifl_size; i++) { | ||||
iflib_rxsd_t d = &fl->ifl_sds[i]; | struct mbuf **sd_m = &fl->ifl_sds.ifsd_m[i]; | ||||
uint8_t *sd_flags = &fl->ifl_sds.ifsd_flags[i]; | |||||
caddr_t *sd_cl = &fl->ifl_sds.ifsd_cl[i]; | |||||
if (d->ifsd_flags & RX_SW_DESC_INUSE) { | if (*sd_flags & RX_SW_DESC_INUSE) { | ||||
bus_dmamap_unload(fl->ifl_desc_tag, d->ifsd_map); | if (fl->ifl_sds.ifsd_map != NULL) { | ||||
bus_dmamap_destroy(fl->ifl_desc_tag, d->ifsd_map); | bus_dmamap_t sd_map = fl->ifl_sds.ifsd_map[i]; | ||||
if (d->ifsd_m != NULL) { | bus_dmamap_unload(fl->ifl_desc_tag, sd_map); | ||||
m_init(d->ifsd_m, M_NOWAIT, MT_DATA, 0); | if (fl->ifl_rxq->ifr_ctx->ifc_in_detach) | ||||
uma_zfree(zone_mbuf, d->ifsd_m); | bus_dmamap_destroy(fl->ifl_desc_tag, sd_map); | ||||
} | } | ||||
if (d->ifsd_cl != NULL) | if (*sd_m != NULL) { | ||||
uma_zfree(fl->ifl_zone, d->ifsd_cl); | m_init(*sd_m, M_NOWAIT, MT_DATA, 0); | ||||
d->ifsd_flags = 0; | uma_zfree(zone_mbuf, *sd_m); | ||||
} | |||||
if (*sd_cl != NULL) | |||||
uma_zfree(fl->ifl_zone, *sd_cl); | |||||
*sd_flags = 0; | |||||
} else { | } else { | ||||
MPASS(d->ifsd_cl == NULL); | MPASS(*sd_cl == NULL); | ||||
MPASS(d->ifsd_m == NULL); | MPASS(*sd_m == NULL); | ||||
} | } | ||||
#if MEMORY_LOGGING | #if MEMORY_LOGGING | ||||
fl->ifl_m_dequeued++; | fl->ifl_m_dequeued++; | ||||
fl->ifl_cl_dequeued++; | fl->ifl_cl_dequeued++; | ||||
#endif | #endif | ||||
d->ifsd_cl = NULL; | *sd_cl = NULL; | ||||
d->ifsd_m = NULL; | *sd_m = NULL; | ||||
} | } | ||||
#ifdef INVARIANTS | |||||
for (i = 0; i < fl->ifl_size; i++) { | |||||
MPASS(fl->ifl_sds.ifsd_flags[i] == 0); | |||||
MPASS(fl->ifl_sds.ifsd_cl[i] == NULL); | |||||
MPASS(fl->ifl_sds.ifsd_m[i] == NULL); | |||||
} | |||||
#endif | |||||
/* | /* | ||||
* Reset free list values | * Reset free list values | ||||
*/ | */ | ||||
fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = 0;; | fl->ifl_credits = fl->ifl_cidx = fl->ifl_pidx = fl->ifl_gen = fl->ifl_fragidx = 0; | ||||
bzero(idi->idi_vaddr, idi->idi_size); | bzero(idi->idi_vaddr, idi->idi_size); | ||||
} | } | ||||
/********************************************************************* | /********************************************************************* | ||||
* | * | ||||
* Initialize a receive ring and its buffers. | * Initialize a receive ring and its buffers. | ||||
* | * | ||||
**********************************************************************/ | **********************************************************************/ | ||||
static int | static int | ||||
iflib_fl_setup(iflib_fl_t fl) | iflib_fl_setup(iflib_fl_t fl) | ||||
{ | { | ||||
iflib_rxq_t rxq = fl->ifl_rxq; | iflib_rxq_t rxq = fl->ifl_rxq; | ||||
if_ctx_t ctx = rxq->ifr_ctx; | if_ctx_t ctx = rxq->ifr_ctx; | ||||
if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; | if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; | ||||
bit_nclear(fl->ifl_rx_bitmap, 0, fl->ifl_size - 1); | |||||
/* | /* | ||||
** Free current RX buffer structs and their mbufs | ** Free current RX buffer structs and their mbufs | ||||
*/ | */ | ||||
iflib_fl_bufs_free(fl); | iflib_fl_bufs_free(fl); | ||||
/* Now replenish the mbufs */ | /* Now replenish the mbufs */ | ||||
MPASS(fl->ifl_credits == 0); | MPASS(fl->ifl_credits == 0); | ||||
/* | /* | ||||
* XXX don't set the max_frame_size to larger | * XXX don't set the max_frame_size to larger | ||||
* than the hardware can handle | * than the hardware can handle | ||||
*/ | */ | ||||
if (sctx->isc_max_frame_size <= 2048) | if (sctx->isc_max_frame_size <= 2048) | ||||
fl->ifl_buf_size = MCLBYTES; | fl->ifl_buf_size = MCLBYTES; | ||||
#ifndef CONTIGMALLOC_WORKS | |||||
else | |||||
fl->ifl_buf_size = MJUMPAGESIZE; | |||||
#else | |||||
else if (sctx->isc_max_frame_size <= 4096) | else if (sctx->isc_max_frame_size <= 4096) | ||||
fl->ifl_buf_size = MJUMPAGESIZE; | fl->ifl_buf_size = MJUMPAGESIZE; | ||||
else if (sctx->isc_max_frame_size <= 9216) | else if (sctx->isc_max_frame_size <= 9216) | ||||
fl->ifl_buf_size = MJUM9BYTES; | fl->ifl_buf_size = MJUM9BYTES; | ||||
else | else | ||||
fl->ifl_buf_size = MJUM16BYTES; | fl->ifl_buf_size = MJUM16BYTES; | ||||
#endif | |||||
if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) | if (fl->ifl_buf_size > ctx->ifc_max_fl_buf_size) | ||||
ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; | ctx->ifc_max_fl_buf_size = fl->ifl_buf_size; | ||||
fl->ifl_cltype = m_gettype(fl->ifl_buf_size); | fl->ifl_cltype = m_gettype(fl->ifl_buf_size); | ||||
fl->ifl_zone = m_getzone(fl->ifl_buf_size); | fl->ifl_zone = m_getzone(fl->ifl_buf_size); | ||||
/* avoid pre-allocating zillions of clusters to an idle card | /* avoid pre-allocating zillions of clusters to an idle card | ||||
* potentially speeding up attach | * potentially speeding up attach | ||||
Show All 25 Lines | iflib_rx_sds_free(iflib_rxq_t rxq) | ||||
if (rxq->ifr_fl != NULL) { | if (rxq->ifr_fl != NULL) { | ||||
for (i = 0; i < rxq->ifr_nfl; i++) { | for (i = 0; i < rxq->ifr_nfl; i++) { | ||||
fl = &rxq->ifr_fl[i]; | fl = &rxq->ifr_fl[i]; | ||||
if (fl->ifl_desc_tag != NULL) { | if (fl->ifl_desc_tag != NULL) { | ||||
bus_dma_tag_destroy(fl->ifl_desc_tag); | bus_dma_tag_destroy(fl->ifl_desc_tag); | ||||
fl->ifl_desc_tag = NULL; | fl->ifl_desc_tag = NULL; | ||||
} | } | ||||
free(fl->ifl_sds.ifsd_m, M_IFLIB); | |||||
free(fl->ifl_sds.ifsd_cl, M_IFLIB); | |||||
/* XXX destroy maps first */ | |||||
free(fl->ifl_sds.ifsd_map, M_IFLIB); | |||||
fl->ifl_sds.ifsd_m = NULL; | |||||
fl->ifl_sds.ifsd_cl = NULL; | |||||
fl->ifl_sds.ifsd_map = NULL; | |||||
} | } | ||||
if (rxq->ifr_fl->ifl_sds != NULL) | |||||
free(rxq->ifr_fl->ifl_sds, M_IFLIB); | |||||
free(rxq->ifr_fl, M_IFLIB); | free(rxq->ifr_fl, M_IFLIB); | ||||
rxq->ifr_fl = NULL; | rxq->ifr_fl = NULL; | ||||
rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; | rxq->ifr_cq_gen = rxq->ifr_cq_cidx = rxq->ifr_cq_pidx = 0; | ||||
} | } | ||||
} | } | ||||
/* | /* | ||||
* MI independent logic | * MI independent logic | ||||
* | * | ||||
*/ | */ | ||||
static void | static void | ||||
iflib_timer(void *arg) | iflib_timer(void *arg) | ||||
{ | { | ||||
iflib_txq_t txq = arg; | iflib_txq_t txq = arg; | ||||
if_ctx_t ctx = txq->ift_ctx; | if_ctx_t ctx = txq->ift_ctx; | ||||
if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; | if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; | ||||
if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) | if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) | ||||
return; | return; | ||||
/* | /* | ||||
** Check on the state of the TX queue(s), this | ** Check on the state of the TX queue(s), this | ||||
** can be done without the lock because its RO | ** can be done without the lock because its RO | ||||
** and the HUNG state will be static if set. | ** and the HUNG state will be static if set. | ||||
*/ | */ | ||||
IFDI_TIMER(ctx, txq->ift_id); | IFDI_TIMER(ctx, txq->ift_id); | ||||
if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && | if ((txq->ift_qstatus == IFLIB_QUEUE_HUNG) && | ||||
(ctx->ifc_pause_frames == 0)) | ((txq->ift_cleaned_prev == txq->ift_cleaned) || | ||||
(sctx->isc_pause_frames == 0))) | |||||
goto hung; | goto hung; | ||||
if (TXQ_AVAIL(txq) <= 2*scctx->isc_tx_nsegments || | if (ifmp_ring_is_stalled(txq->ift_br)) | ||||
ifmp_ring_is_stalled(txq->ift_br[0])) | txq->ift_qstatus = IFLIB_QUEUE_HUNG; | ||||
txq->ift_cleaned_prev = txq->ift_cleaned; | |||||
/* handle any laggards */ | |||||
if (txq->ift_db_pending) | |||||
GROUPTASK_ENQUEUE(&txq->ift_task); | GROUPTASK_ENQUEUE(&txq->ift_task); | ||||
ctx->ifc_pause_frames = 0; | sctx->isc_pause_frames = 0; | ||||
if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) | if (if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING) | ||||
callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); | callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); | ||||
return; | return; | ||||
hung: | hung: | ||||
CTX_LOCK(ctx); | CTX_LOCK(ctx); | ||||
if_setdrvflagbits(ctx->ifc_ifp, 0, IFF_DRV_RUNNING); | if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); | ||||
device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", | device_printf(ctx->ifc_dev, "TX(%d) desc avail = %d, pidx = %d\n", | ||||
txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); | txq->ift_id, TXQ_AVAIL(txq), txq->ift_pidx); | ||||
IFDI_WATCHDOG_RESET(ctx); | IFDI_WATCHDOG_RESET(ctx); | ||||
ctx->ifc_watchdog_events++; | ctx->ifc_watchdog_events++; | ||||
ctx->ifc_pause_frames = 0; | |||||
iflib_init_locked(ctx); | ctx->ifc_flags |= IFC_DO_RESET; | ||||
iflib_admin_intr_deferred(ctx); | |||||
CTX_UNLOCK(ctx); | CTX_UNLOCK(ctx); | ||||
} | } | ||||
static void | static void | ||||
iflib_init_locked(if_ctx_t ctx) | iflib_init_locked(if_ctx_t ctx) | ||||
{ | { | ||||
if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; | if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; | ||||
if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; | |||||
if_t ifp = ctx->ifc_ifp; | if_t ifp = ctx->ifc_ifp; | ||||
iflib_fl_t fl; | iflib_fl_t fl; | ||||
iflib_txq_t txq; | iflib_txq_t txq; | ||||
iflib_rxq_t rxq; | iflib_rxq_t rxq; | ||||
int i, j; | int i, j, tx_ip_csum_flags, tx_ip6_csum_flags; | ||||
if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); | if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); | ||||
IFDI_INTR_DISABLE(ctx); | IFDI_INTR_DISABLE(ctx); | ||||
tx_ip_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP); | |||||
tx_ip6_csum_flags = scctx->isc_tx_csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_SCTP); | |||||
/* Set hardware offload abilities */ | /* Set hardware offload abilities */ | ||||
if_clearhwassist(ifp); | if_clearhwassist(ifp); | ||||
if (if_getcapenable(ifp) & IFCAP_TXCSUM) | if (if_getcapenable(ifp) & IFCAP_TXCSUM) | ||||
if_sethwassistbits(ifp, CSUM_IP | CSUM_TCP | CSUM_UDP, 0); | if_sethwassistbits(ifp, tx_ip_csum_flags, 0); | ||||
if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) | if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6) | ||||
if_sethwassistbits(ifp, (CSUM_TCP_IPV6 | CSUM_UDP_IPV6), 0); | if_sethwassistbits(ifp, tx_ip6_csum_flags, 0); | ||||
if (if_getcapenable(ifp) & IFCAP_TSO4) | if (if_getcapenable(ifp) & IFCAP_TSO4) | ||||
if_sethwassistbits(ifp, CSUM_IP_TSO, 0); | if_sethwassistbits(ifp, CSUM_IP_TSO, 0); | ||||
if (if_getcapenable(ifp) & IFCAP_TSO6) | if (if_getcapenable(ifp) & IFCAP_TSO6) | ||||
if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); | if_sethwassistbits(ifp, CSUM_IP6_TSO, 0); | ||||
for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { | for (i = 0, txq = ctx->ifc_txqs; i < sctx->isc_ntxqsets; i++, txq++) { | ||||
CALLOUT_LOCK(txq); | CALLOUT_LOCK(txq); | ||||
callout_stop(&txq->ift_timer); | callout_stop(&txq->ift_timer); | ||||
callout_stop(&txq->ift_db_check); | |||||
CALLOUT_UNLOCK(txq); | CALLOUT_UNLOCK(txq); | ||||
iflib_netmap_txq_init(ctx, txq); | iflib_netmap_txq_init(ctx, txq); | ||||
} | } | ||||
for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { | |||||
iflib_netmap_rxq_init(ctx, rxq); | |||||
} | |||||
#ifdef INVARIANTS | #ifdef INVARIANTS | ||||
i = if_getdrvflags(ifp); | i = if_getdrvflags(ifp); | ||||
#endif | #endif | ||||
IFDI_INIT(ctx); | IFDI_INIT(ctx); | ||||
MPASS(if_getdrvflags(ifp) == i); | MPASS(if_getdrvflags(ifp) == i); | ||||
for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { | for (i = 0, rxq = ctx->ifc_rxqs; i < sctx->isc_nrxqsets; i++, rxq++) { | ||||
/* XXX this should really be done on a per-queue basis */ | |||||
if (if_getcapenable(ifp) & IFCAP_NETMAP) { | |||||
MPASS(rxq->ifr_id == i); | |||||
iflib_netmap_rxq_init(ctx, rxq); | |||||
continue; | |||||
} | |||||
for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { | for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { | ||||
if (iflib_fl_setup(fl)) { | if (iflib_fl_setup(fl)) { | ||||
device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); | device_printf(ctx->ifc_dev, "freelist setup failed - check cluster settings\n"); | ||||
goto done; | goto done; | ||||
} | } | ||||
} | } | ||||
} | } | ||||
done: | done: | ||||
Show All 38 Lines | iflib_stop(if_ctx_t ctx) | ||||
iflib_dma_info_t di; | iflib_dma_info_t di; | ||||
iflib_fl_t fl; | iflib_fl_t fl; | ||||
int i, j; | int i, j; | ||||
/* Tell the stack that the interface is no longer active */ | /* Tell the stack that the interface is no longer active */ | ||||
if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); | if_setdrvflagbits(ctx->ifc_ifp, IFF_DRV_OACTIVE, IFF_DRV_RUNNING); | ||||
IFDI_INTR_DISABLE(ctx); | IFDI_INTR_DISABLE(ctx); | ||||
msleep(ctx, &ctx->ifc_mtx, PUSER, "iflib_init", hz); | DELAY(1000); | ||||
IFDI_STOP(ctx); | |||||
DELAY(1000); | |||||
iflib_debug_reset(); | |||||
/* Wait for current tx queue users to exit to disarm watchdog timer. */ | /* Wait for current tx queue users to exit to disarm watchdog timer. */ | ||||
for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { | for (i = 0; i < scctx->isc_ntxqsets; i++, txq++) { | ||||
/* make sure all transmitters have completed before proceeding XXX */ | /* make sure all transmitters have completed before proceeding XXX */ | ||||
CALLOUT_LOCK(txq); | |||||
callout_stop(&txq->ift_timer); | |||||
CALLOUT_UNLOCK(txq); | |||||
/* clean any enqueued buffers */ | /* clean any enqueued buffers */ | ||||
iflib_txq_check_drain(txq, 0); | iflib_ifmp_purge(txq); | ||||
/* Free any existing tx buffers. */ | /* Free any existing tx buffers. */ | ||||
for (j = 0; j < txq->ift_size; j++) { | for (j = 0; j < txq->ift_size; j++) { | ||||
iflib_txsd_free(ctx, txq, j); | iflib_txsd_free(ctx, txq, j); | ||||
} | } | ||||
txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; | txq->ift_processed = txq->ift_cleaned = txq->ift_cidx_processed = 0; | ||||
txq->ift_in_use = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; | txq->ift_in_use = txq->ift_gen = txq->ift_cidx = txq->ift_pidx = txq->ift_no_desc_avail = 0; | ||||
txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; | txq->ift_closed = txq->ift_mbuf_defrag = txq->ift_mbuf_defrag_failed = 0; | ||||
txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; | txq->ift_no_tx_dma_setup = txq->ift_txd_encap_efbig = txq->ift_map_failed = 0; | ||||
txq->ift_pullups = 0; | txq->ift_pullups = 0; | ||||
ifmp_ring_reset_stats(txq->ift_br[0]); | ifmp_ring_reset_stats(txq->ift_br); | ||||
for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) | for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwtxqs; j++, di++) | ||||
bzero((void *)di->idi_vaddr, di->idi_size); | bzero((void *)di->idi_vaddr, di->idi_size); | ||||
} | } | ||||
for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { | for (i = 0; i < scctx->isc_nrxqsets; i++, rxq++) { | ||||
/* make sure all transmitters have completed before proceeding XXX */ | /* make sure all transmitters have completed before proceeding XXX */ | ||||
for (j = 0, di = txq->ift_ifdi; j < ctx->ifc_nhwrxqs; j++, di++) | for (j = 0, di = rxq->ifr_ifdi; j < rxq->ifr_nfl; j++, di++) | ||||
bzero((void *)di->idi_vaddr, di->idi_size); | bzero((void *)di->idi_vaddr, di->idi_size); | ||||
/* also resets the free lists pidx/cidx */ | /* also resets the free lists pidx/cidx */ | ||||
for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) | for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) | ||||
iflib_fl_bufs_free(fl); | iflib_fl_bufs_free(fl); | ||||
} | } | ||||
IFDI_STOP(ctx); | |||||
} | } | ||||
static iflib_rxsd_t | static inline caddr_t | ||||
rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int *cltype, int unload) | calc_next_rxd(iflib_fl_t fl, int cidx) | ||||
{ | { | ||||
qidx_t size; | |||||
int nrxd; | |||||
caddr_t start, end, cur, next; | |||||
nrxd = fl->ifl_size; | |||||
size = fl->ifl_rxd_size; | |||||
start = fl->ifl_ifdi->idi_vaddr; | |||||
if (__predict_false(size == 0)) | |||||
return (start); | |||||
cur = start + size*cidx; | |||||
end = start + size*nrxd; | |||||
next = CACHE_PTR_NEXT(cur); | |||||
return (next < end ? next : start); | |||||
} | |||||
static inline void | |||||
prefetch_pkts(iflib_fl_t fl, int cidx) | |||||
{ | |||||
int nextptr; | |||||
int nrxd = fl->ifl_size; | |||||
caddr_t next_rxd; | |||||
nextptr = (cidx + CACHE_PTR_INCREMENT) & (nrxd-1); | |||||
prefetch(&fl->ifl_sds.ifsd_m[nextptr]); | |||||
prefetch(&fl->ifl_sds.ifsd_cl[nextptr]); | |||||
next_rxd = calc_next_rxd(fl, cidx); | |||||
prefetch(next_rxd); | |||||
prefetch(fl->ifl_sds.ifsd_m[(cidx + 1) & (nrxd-1)]); | |||||
prefetch(fl->ifl_sds.ifsd_m[(cidx + 2) & (nrxd-1)]); | |||||
prefetch(fl->ifl_sds.ifsd_m[(cidx + 3) & (nrxd-1)]); | |||||
prefetch(fl->ifl_sds.ifsd_m[(cidx + 4) & (nrxd-1)]); | |||||
prefetch(fl->ifl_sds.ifsd_cl[(cidx + 1) & (nrxd-1)]); | |||||
prefetch(fl->ifl_sds.ifsd_cl[(cidx + 2) & (nrxd-1)]); | |||||
prefetch(fl->ifl_sds.ifsd_cl[(cidx + 3) & (nrxd-1)]); | |||||
prefetch(fl->ifl_sds.ifsd_cl[(cidx + 4) & (nrxd-1)]); | |||||
} | |||||
static void | |||||
rxd_frag_to_sd(iflib_rxq_t rxq, if_rxd_frag_t irf, int unload, if_rxsd_t sd) | |||||
{ | |||||
int flid, cidx; | int flid, cidx; | ||||
iflib_rxsd_t sd; | bus_dmamap_t map; | ||||
iflib_fl_t fl; | iflib_fl_t fl; | ||||
iflib_dma_info_t di; | iflib_dma_info_t di; | ||||
int next; | |||||
map = NULL; | |||||
flid = irf->irf_flid; | flid = irf->irf_flid; | ||||
cidx = irf->irf_idx; | cidx = irf->irf_idx; | ||||
fl = &rxq->ifr_fl[flid]; | fl = &rxq->ifr_fl[flid]; | ||||
sd->ifsd_fl = fl; | |||||
sd->ifsd_cidx = cidx; | |||||
sd->ifsd_m = &fl->ifl_sds.ifsd_m[cidx]; | |||||
sd->ifsd_cl = &fl->ifl_sds.ifsd_cl[cidx]; | |||||
fl->ifl_credits--; | fl->ifl_credits--; | ||||
#if MEMORY_LOGGING | #if MEMORY_LOGGING | ||||
fl->ifl_m_dequeued++; | fl->ifl_m_dequeued++; | ||||
if (cltype) | |||||
fl->ifl_cl_dequeued++; | |||||
#endif | #endif | ||||
sd = &fl->ifl_sds[cidx]; | if (rxq->ifr_ctx->ifc_flags & IFC_PREFETCH) | ||||
prefetch_pkts(fl, cidx); | |||||
if (fl->ifl_sds.ifsd_map != NULL) { | |||||
next = (cidx + CACHE_PTR_INCREMENT) & (fl->ifl_size-1); | |||||
prefetch(&fl->ifl_sds.ifsd_map[next]); | |||||
map = fl->ifl_sds.ifsd_map[cidx]; | |||||
di = fl->ifl_ifdi; | di = fl->ifl_ifdi; | ||||
next = (cidx + CACHE_LINE_SIZE) & (fl->ifl_size-1); | |||||
prefetch(&fl->ifl_sds.ifsd_flags[next]); | |||||
bus_dmamap_sync(di->idi_tag, di->idi_map, | bus_dmamap_sync(di->idi_tag, di->idi_map, | ||||
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); | BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); | ||||
/* not valid assert if bxe really does SGE from non-contiguous elements */ | /* not valid assert if bxe really does SGE from non-contiguous elements */ | ||||
MPASS(fl->ifl_cidx == cidx); | MPASS(fl->ifl_cidx == cidx); | ||||
if (unload) | if (unload) | ||||
bus_dmamap_unload(fl->ifl_desc_tag, sd->ifsd_map); | bus_dmamap_unload(fl->ifl_desc_tag, map); | ||||
} | |||||
if (__predict_false(++fl->ifl_cidx == fl->ifl_size)) { | fl->ifl_cidx = (fl->ifl_cidx + 1) & (fl->ifl_size-1); | ||||
fl->ifl_cidx = 0; | if (__predict_false(fl->ifl_cidx == 0)) | ||||
fl->ifl_gen = 0; | fl->ifl_gen = 0; | ||||
if (map != NULL) | |||||
bus_dmamap_sync(fl->ifl_ifdi->idi_tag, fl->ifl_ifdi->idi_map, | |||||
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); | |||||
bit_clear(fl->ifl_rx_bitmap, cidx); | |||||
} | } | ||||
/* YES ick */ | |||||
if (cltype) | |||||
*cltype = fl->ifl_cltype; | |||||
return (sd); | |||||
} | |||||
static struct mbuf * | static struct mbuf * | ||||
assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri) | assemble_segments(iflib_rxq_t rxq, if_rxd_info_t ri, if_rxsd_t sd) | ||||
{ | { | ||||
int i, padlen , flags, cltype; | int i, padlen , flags; | ||||
struct mbuf *m, *mh, *mt; | struct mbuf *m, *mh, *mt; | ||||
iflib_rxsd_t sd; | |||||
caddr_t cl; | caddr_t cl; | ||||
i = 0; | i = 0; | ||||
mh = NULL; | mh = NULL; | ||||
do { | do { | ||||
sd = rxd_frag_to_sd(rxq, &ri->iri_frags[i], &cltype, TRUE); | rxd_frag_to_sd(rxq, &ri->iri_frags[i], TRUE, sd); | ||||
MPASS(sd->ifsd_cl != NULL); | MPASS(*sd->ifsd_cl != NULL); | ||||
MPASS(sd->ifsd_m != NULL); | MPASS(*sd->ifsd_m != NULL); | ||||
/* Don't include zero-length frags */ | /* Don't include zero-length frags */ | ||||
if (ri->iri_frags[i].irf_len == 0) { | if (ri->iri_frags[i].irf_len == 0) { | ||||
/* XXX we can save the cluster here, but not the mbuf */ | /* XXX we can save the cluster here, but not the mbuf */ | ||||
m_init(sd->ifsd_m, M_NOWAIT, MT_DATA, 0); | m_init(*sd->ifsd_m, M_NOWAIT, MT_DATA, 0); | ||||
m_free(sd->ifsd_m); | m_free(*sd->ifsd_m); | ||||
sd->ifsd_m = NULL; | *sd->ifsd_m = NULL; | ||||
continue; | continue; | ||||
} | } | ||||
m = *sd->ifsd_m; | |||||
m = sd->ifsd_m; | *sd->ifsd_m = NULL; | ||||
if (mh == NULL) { | if (mh == NULL) { | ||||
flags = M_PKTHDR|M_EXT; | flags = M_PKTHDR|M_EXT; | ||||
mh = mt = m; | mh = mt = m; | ||||
padlen = ri->iri_pad; | padlen = ri->iri_pad; | ||||
} else { | } else { | ||||
flags = M_EXT; | flags = M_EXT; | ||||
mt->m_next = m; | mt->m_next = m; | ||||
mt = m; | mt = m; | ||||
/* assuming padding is only on the first fragment */ | /* assuming padding is only on the first fragment */ | ||||
padlen = 0; | padlen = 0; | ||||
} | } | ||||
sd->ifsd_m = NULL; | cl = *sd->ifsd_cl; | ||||
cl = sd->ifsd_cl; | *sd->ifsd_cl = NULL; | ||||
sd->ifsd_cl = NULL; | |||||
/* Can these two be made one ? */ | /* Can these two be made one ? */ | ||||
m_init(m, M_NOWAIT, MT_DATA, flags); | m_init(m, M_NOWAIT, MT_DATA, flags); | ||||
m_cljset(m, cl, cltype); | m_cljset(m, cl, sd->ifsd_fl->ifl_cltype); | ||||
/* | /* | ||||
* These must follow m_init and m_cljset | * These must follow m_init and m_cljset | ||||
*/ | */ | ||||
m->m_data += padlen; | m->m_data += padlen; | ||||
ri->iri_len -= padlen; | ri->iri_len -= padlen; | ||||
m->m_len = ri->iri_frags[i].irf_len; | m->m_len = ri->iri_frags[i].irf_len; | ||||
} while (++i < ri->iri_nfrags); | } while (++i < ri->iri_nfrags); | ||||
return (mh); | return (mh); | ||||
} | } | ||||
/* | /* | ||||
* Process one software descriptor | * Process one software descriptor | ||||
*/ | */ | ||||
static struct mbuf * | static struct mbuf * | ||||
iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) | iflib_rxd_pkt_get(iflib_rxq_t rxq, if_rxd_info_t ri) | ||||
{ | { | ||||
struct if_rxsd sd; | |||||
struct mbuf *m; | struct mbuf *m; | ||||
iflib_rxsd_t sd; | |||||
/* should I merge this back in now that the two paths are basically duplicated? */ | /* should I merge this back in now that the two paths are basically duplicated? */ | ||||
if (ri->iri_nfrags == 1 && | if (ri->iri_nfrags == 1 && | ||||
ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { | ri->iri_frags[0].irf_len <= MIN(IFLIB_RX_COPY_THRESH, MHLEN)) { | ||||
sd = rxd_frag_to_sd(rxq, &ri->iri_frags[0], NULL, FALSE); | rxd_frag_to_sd(rxq, &ri->iri_frags[0], FALSE, &sd); | ||||
m = sd->ifsd_m; | m = *sd.ifsd_m; | ||||
sd->ifsd_m = NULL; | *sd.ifsd_m = NULL; | ||||
m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); | m_init(m, M_NOWAIT, MT_DATA, M_PKTHDR); | ||||
memcpy(m->m_data, sd->ifsd_cl, ri->iri_len); | #ifndef __NO_STRICT_ALIGNMENT | ||||
if (!IP_ALIGNED(m)) | |||||
m->m_data += 2; | |||||
#endif | |||||
memcpy(m->m_data, *sd.ifsd_cl, ri->iri_len); | |||||
m->m_len = ri->iri_frags[0].irf_len; | m->m_len = ri->iri_frags[0].irf_len; | ||||
} else { | } else { | ||||
m = assemble_segments(rxq, ri); | m = assemble_segments(rxq, ri, &sd); | ||||
} | } | ||||
m->m_pkthdr.len = ri->iri_len; | m->m_pkthdr.len = ri->iri_len; | ||||
m->m_pkthdr.rcvif = ri->iri_ifp; | m->m_pkthdr.rcvif = ri->iri_ifp; | ||||
m->m_flags |= ri->iri_flags; | m->m_flags |= ri->iri_flags; | ||||
m->m_pkthdr.ether_vtag = ri->iri_vtag; | m->m_pkthdr.ether_vtag = ri->iri_vtag; | ||||
m->m_pkthdr.flowid = ri->iri_flowid; | m->m_pkthdr.flowid = ri->iri_flowid; | ||||
M_HASHTYPE_SET(m, ri->iri_rsstype); | M_HASHTYPE_SET(m, ri->iri_rsstype); | ||||
m->m_pkthdr.csum_flags = ri->iri_csum_flags; | m->m_pkthdr.csum_flags = ri->iri_csum_flags; | ||||
m->m_pkthdr.csum_data = ri->iri_csum_data; | m->m_pkthdr.csum_data = ri->iri_csum_data; | ||||
return (m); | return (m); | ||||
} | } | ||||
#if defined(INET6) || defined(INET) | |||||
static void | |||||
iflib_get_ip_forwarding(struct lro_ctrl *lc, bool *v4, bool *v6) | |||||
{ | |||||
CURVNET_SET(lc->ifp->if_vnet); | |||||
#if defined(INET6) | |||||
*v6 = VNET(ip6_forwarding); | |||||
#endif | |||||
#if defined(INET) | |||||
*v4 = VNET(ipforwarding); | |||||
#endif | |||||
CURVNET_RESTORE(); | |||||
} | |||||
/* | |||||
* Returns true if it's possible this packet could be LROed. | |||||
* if it returns false, it is guaranteed that tcp_lro_rx() | |||||
* would not return zero. | |||||
*/ | |||||
static bool | static bool | ||||
iflib_rxeof(iflib_rxq_t rxq, int budget) | iflib_check_lro_possible(struct mbuf *m, bool v4_forwarding, bool v6_forwarding) | ||||
{ | { | ||||
struct ether_header *eh; | |||||
uint16_t eh_type; | |||||
eh = mtod(m, struct ether_header *); | |||||
eh_type = ntohs(eh->ether_type); | |||||
switch (eh_type) { | |||||
#if defined(INET6) | |||||
case ETHERTYPE_IPV6: | |||||
return !v6_forwarding; | |||||
#endif | |||||
#if defined (INET) | |||||
case ETHERTYPE_IP: | |||||
return !v4_forwarding; | |||||
#endif | |||||
} | |||||
return false; | |||||
} | |||||
#else | |||||
static void | |||||
iflib_get_ip_forwarding(struct lro_ctrl *lc __unused, bool *v4 __unused, bool *v6 __unused) | |||||
{ | |||||
} | |||||
#endif | |||||
static bool | |||||
iflib_rxeof(iflib_rxq_t rxq, qidx_t budget) | |||||
{ | |||||
if_ctx_t ctx = rxq->ifr_ctx; | if_ctx_t ctx = rxq->ifr_ctx; | ||||
if_shared_ctx_t sctx = ctx->ifc_sctx; | if_shared_ctx_t sctx = ctx->ifc_sctx; | ||||
if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; | if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; | ||||
int avail, i; | int avail, i; | ||||
uint16_t *cidxp; | qidx_t *cidxp; | ||||
struct if_rxd_info ri; | struct if_rxd_info ri; | ||||
int err, budget_left, rx_bytes, rx_pkts; | int err, budget_left, rx_bytes, rx_pkts; | ||||
iflib_fl_t fl; | iflib_fl_t fl; | ||||
struct ifnet *ifp; | struct ifnet *ifp; | ||||
int lro_enabled; | int lro_enabled; | ||||
bool lro_possible = false; | |||||
bool v4_forwarding, v6_forwarding; | |||||
/* | /* | ||||
* XXX early demux data packets so that if_input processing only handles | * XXX early demux data packets so that if_input processing only handles | ||||
* acks in interrupt context | * acks in interrupt context | ||||
*/ | */ | ||||
struct mbuf *m, *mh, *mt; | struct mbuf *m, *mh, *mt, *mf; | ||||
if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &budget)) { | ifp = ctx->ifc_ifp; | ||||
return (FALSE); | |||||
} | |||||
mh = mt = NULL; | mh = mt = NULL; | ||||
MPASS(budget > 0); | MPASS(budget > 0); | ||||
rx_pkts = rx_bytes = 0; | rx_pkts = rx_bytes = 0; | ||||
if (sctx->isc_flags & IFLIB_HAS_RXCQ) | if (sctx->isc_flags & IFLIB_HAS_RXCQ) | ||||
cidxp = &rxq->ifr_cq_cidx; | cidxp = &rxq->ifr_cq_cidx; | ||||
else | else | ||||
cidxp = &rxq->ifr_fl[0].ifl_cidx; | cidxp = &rxq->ifr_fl[0].ifl_cidx; | ||||
if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { | if ((avail = iflib_rxd_avail(ctx, rxq, *cidxp, budget)) == 0) { | ||||
for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) | for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) | ||||
__iflib_fl_refill_lt(ctx, fl, budget + 8); | __iflib_fl_refill_lt(ctx, fl, budget + 8); | ||||
DBG_COUNTER_INC(rx_unavail); | DBG_COUNTER_INC(rx_unavail); | ||||
return (false); | return (false); | ||||
} | } | ||||
for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { | for (budget_left = budget; (budget_left > 0) && (avail > 0); budget_left--, avail--) { | ||||
if (__predict_false(!CTX_ACTIVE(ctx))) { | if (__predict_false(!CTX_ACTIVE(ctx))) { | ||||
DBG_COUNTER_INC(rx_ctx_inactive); | DBG_COUNTER_INC(rx_ctx_inactive); | ||||
break; | break; | ||||
} | } | ||||
/* | /* | ||||
* Reset client set fields to their default values | * Reset client set fields to their default values | ||||
*/ | */ | ||||
bzero(&ri, sizeof(ri)); | rxd_info_zero(&ri); | ||||
ri.iri_qsidx = rxq->ifr_id; | ri.iri_qsidx = rxq->ifr_id; | ||||
ri.iri_cidx = *cidxp; | ri.iri_cidx = *cidxp; | ||||
ri.iri_ifp = ctx->ifc_ifp; | ri.iri_ifp = ifp; | ||||
ri.iri_frags = rxq->ifr_frags; | ri.iri_frags = rxq->ifr_frags; | ||||
err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); | err = ctx->isc_rxd_pkt_get(ctx->ifc_softc, &ri); | ||||
/* in lieu of handling correctly - make sure it isn't being unhandled */ | if (err) | ||||
MPASS(err == 0); | goto err; | ||||
if (sctx->isc_flags & IFLIB_HAS_RXCQ) { | if (sctx->isc_flags & IFLIB_HAS_RXCQ) { | ||||
*cidxp = ri.iri_cidx; | *cidxp = ri.iri_cidx; | ||||
/* Update our consumer index */ | /* Update our consumer index */ | ||||
/* XXX NB: shurd - check if this is still safe */ | |||||
while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { | while (rxq->ifr_cq_cidx >= scctx->isc_nrxd[0]) { | ||||
rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; | rxq->ifr_cq_cidx -= scctx->isc_nrxd[0]; | ||||
rxq->ifr_cq_gen = 0; | rxq->ifr_cq_gen = 0; | ||||
} | } | ||||
/* was this only a completion queue message? */ | /* was this only a completion queue message? */ | ||||
if (__predict_false(ri.iri_nfrags == 0)) | if (__predict_false(ri.iri_nfrags == 0)) | ||||
continue; | continue; | ||||
} | } | ||||
Show All 16 Lines | else { | ||||
mt->m_nextpkt = m; | mt->m_nextpkt = m; | ||||
mt = m; | mt = m; | ||||
} | } | ||||
} | } | ||||
/* make sure that we can refill faster than drain */ | /* make sure that we can refill faster than drain */ | ||||
for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) | for (i = 0, fl = &rxq->ifr_fl[0]; i < sctx->isc_nfl; i++, fl++) | ||||
__iflib_fl_refill_lt(ctx, fl, budget + 8); | __iflib_fl_refill_lt(ctx, fl, budget + 8); | ||||
ifp = ctx->ifc_ifp; | |||||
lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); | lro_enabled = (if_getcapenable(ifp) & IFCAP_LRO); | ||||
if (lro_enabled) | |||||
iflib_get_ip_forwarding(&rxq->ifr_lc, &v4_forwarding, &v6_forwarding); | |||||
mt = mf = NULL; | |||||
while (mh != NULL) { | while (mh != NULL) { | ||||
m = mh; | m = mh; | ||||
mh = mh->m_nextpkt; | mh = mh->m_nextpkt; | ||||
m->m_nextpkt = NULL; | m->m_nextpkt = NULL; | ||||
#ifndef __NO_STRICT_ALIGNMENT | |||||
if (!IP_ALIGNED(m) && (m = iflib_fixup_rx(m)) == NULL) | |||||
continue; | |||||
#endif | |||||
rx_bytes += m->m_pkthdr.len; | rx_bytes += m->m_pkthdr.len; | ||||
rx_pkts++; | rx_pkts++; | ||||
#if defined(INET6) || defined(INET) | #if defined(INET6) || defined(INET) | ||||
if (lro_enabled && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) | if (lro_enabled) { | ||||
if (!lro_possible) { | |||||
lro_possible = iflib_check_lro_possible(m, v4_forwarding, v6_forwarding); | |||||
if (lro_possible && mf != NULL) { | |||||
ifp->if_input(ifp, mf); | |||||
DBG_COUNTER_INC(rx_if_input); | |||||
mt = mf = NULL; | |||||
} | |||||
} | |||||
if ((m->m_pkthdr.csum_flags & (CSUM_L4_CALC|CSUM_L4_VALID)) == | |||||
(CSUM_L4_CALC|CSUM_L4_VALID)) { | |||||
if (lro_possible && tcp_lro_rx(&rxq->ifr_lc, m, 0) == 0) | |||||
continue; | continue; | ||||
} | |||||
} | |||||
#endif | #endif | ||||
DBG_COUNTER_INC(rx_if_input); | if (lro_possible) { | ||||
ifp->if_input(ifp, m); | ifp->if_input(ifp, m); | ||||
DBG_COUNTER_INC(rx_if_input); | |||||
continue; | |||||
} | } | ||||
if (mf == NULL) | |||||
mf = m; | |||||
if (mt != NULL) | |||||
mt->m_nextpkt = m; | |||||
mt = m; | |||||
} | |||||
if (mf != NULL) { | |||||
ifp->if_input(ifp, mf); | |||||
DBG_COUNTER_INC(rx_if_input); | |||||
} | |||||
if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); | if_inc_counter(ifp, IFCOUNTER_IBYTES, rx_bytes); | ||||
if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); | if_inc_counter(ifp, IFCOUNTER_IPACKETS, rx_pkts); | ||||
/* | /* | ||||
* Flush any outstanding LRO work | * Flush any outstanding LRO work | ||||
*/ | */ | ||||
#if defined(INET6) || defined(INET) | #if defined(INET6) || defined(INET) | ||||
tcp_lro_flush_all(&rxq->ifr_lc); | tcp_lro_flush_all(&rxq->ifr_lc); | ||||
#endif | #endif | ||||
if (avail) | if (avail) | ||||
return true; | return true; | ||||
return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); | return (iflib_rxd_avail(ctx, rxq, *cidxp, 1)); | ||||
err: | |||||
CTX_LOCK(ctx); | |||||
ctx->ifc_flags |= IFC_DO_RESET; | |||||
iflib_admin_intr_deferred(ctx); | |||||
CTX_UNLOCK(ctx); | |||||
return (false); | |||||
} | } | ||||
#define TXD_NOTIFY_COUNT(txq) (((txq)->ift_size / (txq)->ift_update_freq)-1) | |||||
static inline qidx_t | |||||
txq_max_db_deferred(iflib_txq_t txq, qidx_t in_use) | |||||
{ | |||||
qidx_t notify_count = TXD_NOTIFY_COUNT(txq); | |||||
qidx_t minthresh = txq->ift_size / 8; | |||||
if (in_use > 4*minthresh) | |||||
return (notify_count); | |||||
if (in_use > 2*minthresh) | |||||
return (notify_count >> 1); | |||||
if (in_use > minthresh) | |||||
return (notify_count >> 3); | |||||
return (0); | |||||
} | |||||
static inline qidx_t | |||||
txq_max_rs_deferred(iflib_txq_t txq) | |||||
{ | |||||
qidx_t notify_count = TXD_NOTIFY_COUNT(txq); | |||||
qidx_t minthresh = txq->ift_size / 8; | |||||
if (txq->ift_in_use > 4*minthresh) | |||||
return (notify_count); | |||||
if (txq->ift_in_use > 2*minthresh) | |||||
return (notify_count >> 1); | |||||
if (txq->ift_in_use > minthresh) | |||||
return (notify_count >> 2); | |||||
return (2); | |||||
} | |||||
#define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) | #define M_CSUM_FLAGS(m) ((m)->m_pkthdr.csum_flags) | ||||
#define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) | #define M_HAS_VLANTAG(m) (m->m_flags & M_VLANTAG) | ||||
#define TXQ_MAX_DB_DEFERRED(size) (size >> 5) | |||||
#define TXQ_MAX_DB_DEFERRED(txq, in_use) txq_max_db_deferred((txq), (in_use)) | |||||
#define TXQ_MAX_RS_DEFERRED(txq) txq_max_rs_deferred(txq) | |||||
#define TXQ_MAX_DB_CONSUMED(size) (size >> 4) | #define TXQ_MAX_DB_CONSUMED(size) (size >> 4) | ||||
static __inline void | /* forward compatibility for cxgb */ | ||||
iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring) | #define FIRST_QSET(ctx) 0 | ||||
{ | #define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) | ||||
uint32_t dbval; | #define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) | ||||
#define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) | |||||
#define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) | |||||
if (ring || txq->ift_db_pending >= | /* XXX we should be setting this to something other than zero */ | ||||
TXQ_MAX_DB_DEFERRED(txq->ift_size)) { | #define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) | ||||
#define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) | |||||
/* the lock will only ever be contended in the !min_latency case */ | static inline bool | ||||
if (!TXDB_TRYLOCK(txq)) | iflib_txd_db_check(if_ctx_t ctx, iflib_txq_t txq, int ring, qidx_t in_use) | ||||
return; | { | ||||
qidx_t dbval, max; | |||||
bool rang; | |||||
rang = false; | |||||
max = TXQ_MAX_DB_DEFERRED(txq, in_use); | |||||
if (ring || txq->ift_db_pending >= max) { | |||||
dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; | dbval = txq->ift_npending ? txq->ift_npending : txq->ift_pidx; | ||||
ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); | ctx->isc_txd_flush(ctx->ifc_softc, txq->ift_id, dbval); | ||||
txq->ift_db_pending = txq->ift_npending = 0; | txq->ift_db_pending = txq->ift_npending = 0; | ||||
TXDB_UNLOCK(txq); | rang = true; | ||||
} | } | ||||
return (rang); | |||||
} | } | ||||
static void | |||||
iflib_txd_deferred_db_check(void * arg) | |||||
{ | |||||
iflib_txq_t txq = arg; | |||||
/* simple non-zero boolean so use bitwise OR */ | |||||
if ((txq->ift_db_pending | txq->ift_npending) && | |||||
txq->ift_db_pending >= txq->ift_db_pending_queued) | |||||
iflib_txd_db_check(txq->ift_ctx, txq, TRUE); | |||||
txq->ift_db_pending_queued = 0; | |||||
if (ifmp_ring_is_stalled(txq->ift_br[0])) | |||||
iflib_txq_check_drain(txq, 4); | |||||
} | |||||
#ifdef PKT_DEBUG | #ifdef PKT_DEBUG | ||||
static void | static void | ||||
print_pkt(if_pkt_info_t pi) | print_pkt(if_pkt_info_t pi) | ||||
{ | { | ||||
printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", | printf("pi len: %d qsidx: %d nsegs: %d ndescs: %d flags: %x pidx: %d\n", | ||||
pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); | pi->ipi_len, pi->ipi_qsidx, pi->ipi_nsegs, pi->ipi_ndescs, pi->ipi_flags, pi->ipi_pidx); | ||||
printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", | printf("pi new_pidx: %d csum_flags: %lx tso_segsz: %d mflags: %x vtag: %d\n", | ||||
pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); | pi->ipi_new_pidx, pi->ipi_csum_flags, pi->ipi_tso_segsz, pi->ipi_mflags, pi->ipi_vtag); | ||||
printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", | printf("pi etype: %d ehdrlen: %d ip_hlen: %d ipproto: %d\n", | ||||
pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); | pi->ipi_etype, pi->ipi_ehdrlen, pi->ipi_ip_hlen, pi->ipi_ipproto); | ||||
} | } | ||||
#endif | #endif | ||||
#define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) | #define IS_TSO4(pi) ((pi)->ipi_csum_flags & CSUM_IP_TSO) | ||||
#define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) | #define IS_TSO6(pi) ((pi)->ipi_csum_flags & CSUM_IP6_TSO) | ||||
static int | static int | ||||
iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) | iflib_parse_header(iflib_txq_t txq, if_pkt_info_t pi, struct mbuf **mp) | ||||
{ | { | ||||
if_shared_ctx_t sctx = txq->ift_ctx->ifc_sctx; | |||||
struct ether_vlan_header *eh; | struct ether_vlan_header *eh; | ||||
struct mbuf *m, *n; | struct mbuf *m, *n; | ||||
n = m = *mp; | n = m = *mp; | ||||
if ((sctx->isc_flags & IFLIB_NEED_SCRATCH) && | |||||
M_WRITABLE(m) == 0) { | |||||
if ((m = m_dup(m, M_NOWAIT)) == NULL) { | |||||
return (ENOMEM); | |||||
} else { | |||||
m_freem(*mp); | |||||
n = *mp = m; | |||||
} | |||||
} | |||||
/* | /* | ||||
* Determine where frame payload starts. | * Determine where frame payload starts. | ||||
* Jump over vlan headers if already present, | * Jump over vlan headers if already present, | ||||
* helpful for QinQ too. | * helpful for QinQ too. | ||||
*/ | */ | ||||
if (__predict_false(m->m_len < sizeof(*eh))) { | if (__predict_false(m->m_len < sizeof(*eh))) { | ||||
txq->ift_pullups++; | txq->ift_pullups++; | ||||
if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) | if (__predict_false((m = m_pullup(m, sizeof(*eh))) == NULL)) | ||||
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines | if (__predict_false(m->m_len < minthlen)) { | ||||
ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); | ip = (struct ip *)(m->m_data + pi->ipi_ehdrlen); | ||||
if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) | if (m->m_len >= (ip->ip_hl << 2) + sizeof(*th)) | ||||
th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); | th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); | ||||
} | } | ||||
pi->ipi_ip_hlen = ip->ip_hl << 2; | pi->ipi_ip_hlen = ip->ip_hl << 2; | ||||
pi->ipi_ipproto = ip->ip_p; | pi->ipi_ipproto = ip->ip_p; | ||||
pi->ipi_flags |= IPI_TX_IPV4; | pi->ipi_flags |= IPI_TX_IPV4; | ||||
if (pi->ipi_csum_flags & CSUM_IP) | if ((sctx->isc_flags & IFLIB_NEED_ZERO_CSUM) && (pi->ipi_csum_flags & CSUM_IP)) | ||||
ip->ip_sum = 0; | ip->ip_sum = 0; | ||||
if (IS_TSO4(pi)) { | |||||
if (pi->ipi_ipproto == IPPROTO_TCP) { | if (pi->ipi_ipproto == IPPROTO_TCP) { | ||||
if (__predict_false(th == NULL)) { | if (__predict_false(th == NULL)) { | ||||
txq->ift_pullups++; | txq->ift_pullups++; | ||||
if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) | if (__predict_false((m = m_pullup(m, (ip->ip_hl << 2) + sizeof(*th))) == NULL)) | ||||
return (ENOMEM); | return (ENOMEM); | ||||
th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); | th = (struct tcphdr *)((caddr_t)ip + pi->ipi_ip_hlen); | ||||
} | } | ||||
pi->ipi_tcp_hflags = th->th_flags; | pi->ipi_tcp_hflags = th->th_flags; | ||||
pi->ipi_tcp_hlen = th->th_off << 2; | pi->ipi_tcp_hlen = th->th_off << 2; | ||||
pi->ipi_tcp_seq = th->th_seq; | pi->ipi_tcp_seq = th->th_seq; | ||||
} | } | ||||
if (IS_TSO4(pi)) { | |||||
if (__predict_false(ip->ip_p != IPPROTO_TCP)) | if (__predict_false(ip->ip_p != IPPROTO_TCP)) | ||||
return (ENXIO); | return (ENXIO); | ||||
th->th_sum = in_pseudo(ip->ip_src.s_addr, | th->th_sum = in_pseudo(ip->ip_src.s_addr, | ||||
ip->ip_dst.s_addr, htons(IPPROTO_TCP)); | ip->ip_dst.s_addr, htons(IPPROTO_TCP)); | ||||
pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; | pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; | ||||
if (sctx->isc_flags & IFLIB_TSO_INIT_IP) { | |||||
ip->ip_sum = 0; | |||||
ip->ip_len = htons(pi->ipi_ip_hlen + pi->ipi_tcp_hlen + pi->ipi_tso_segsz); | |||||
} | } | ||||
} | |||||
break; | break; | ||||
} | } | ||||
#endif | #endif | ||||
#ifdef INET6 | #ifdef INET6 | ||||
case ETHERTYPE_IPV6: | case ETHERTYPE_IPV6: | ||||
{ | { | ||||
struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); | struct ip6_hdr *ip6 = (struct ip6_hdr *)(m->m_data + pi->ipi_ehdrlen); | ||||
struct tcphdr *th; | struct tcphdr *th; | ||||
pi->ipi_ip_hlen = sizeof(struct ip6_hdr); | pi->ipi_ip_hlen = sizeof(struct ip6_hdr); | ||||
if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { | if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) { | ||||
if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) | if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr))) == NULL)) | ||||
return (ENOMEM); | return (ENOMEM); | ||||
} | } | ||||
th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); | th = (struct tcphdr *)((caddr_t)ip6 + pi->ipi_ip_hlen); | ||||
/* XXX-BZ this will go badly in case of ext hdrs. */ | /* XXX-BZ this will go badly in case of ext hdrs. */ | ||||
pi->ipi_ipproto = ip6->ip6_nxt; | pi->ipi_ipproto = ip6->ip6_nxt; | ||||
pi->ipi_flags |= IPI_TX_IPV6; | pi->ipi_flags |= IPI_TX_IPV6; | ||||
if (IS_TSO6(pi)) { | |||||
if (pi->ipi_ipproto == IPPROTO_TCP) { | if (pi->ipi_ipproto == IPPROTO_TCP) { | ||||
if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { | if (__predict_false(m->m_len < pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) { | ||||
if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) | if (__predict_false((m = m_pullup(m, pi->ipi_ehdrlen + sizeof(struct ip6_hdr) + sizeof(struct tcphdr))) == NULL)) | ||||
return (ENOMEM); | return (ENOMEM); | ||||
} | } | ||||
pi->ipi_tcp_hflags = th->th_flags; | pi->ipi_tcp_hflags = th->th_flags; | ||||
pi->ipi_tcp_hlen = th->th_off << 2; | pi->ipi_tcp_hlen = th->th_off << 2; | ||||
} | } | ||||
if (IS_TSO6(pi)) { | |||||
if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) | if (__predict_false(ip6->ip6_nxt != IPPROTO_TCP)) | ||||
return (ENXIO); | return (ENXIO); | ||||
/* | /* | ||||
* The corresponding flag is set by the stack in the IPv4 | * The corresponding flag is set by the stack in the IPv4 | ||||
* TSO case, but not in IPv6 (at least in FreeBSD 10.2). | * TSO case, but not in IPv6 (at least in FreeBSD 10.2). | ||||
* So, set it here because the rest of the flow requires it. | * So, set it here because the rest of the flow requires it. | ||||
*/ | */ | ||||
pi->ipi_csum_flags |= CSUM_TCP_IPV6; | pi->ipi_csum_flags |= CSUM_TCP_IPV6; | ||||
th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); | th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0); | ||||
pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; | pi->ipi_tso_segsz = m->m_pkthdr.tso_segsz; | ||||
} | } | ||||
break; | break; | ||||
} | } | ||||
#endif | #endif | ||||
default: | default: | ||||
pi->ipi_csum_flags &= ~CSUM_OFFLOAD; | pi->ipi_csum_flags &= ~CSUM_OFFLOAD; | ||||
pi->ipi_ip_hlen = 0; | pi->ipi_ip_hlen = 0; | ||||
break; | break; | ||||
} | } | ||||
*mp = m; | *mp = m; | ||||
return (0); | return (0); | ||||
} | } | ||||
static __noinline struct mbuf * | static __noinline struct mbuf * | ||||
collapse_pkthdr(struct mbuf *m0) | collapse_pkthdr(struct mbuf *m0) | ||||
{ | { | ||||
struct mbuf *m, *m_next, *tmp; | struct mbuf *m, *m_next, *tmp; | ||||
m = m0; | m = m0; | ||||
m_next = m->m_next; | m_next = m->m_next; | ||||
while (m_next != NULL && m_next->m_len == 0) { | while (m_next != NULL && m_next->m_len == 0) { | ||||
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines | |||||
static int | static int | ||||
iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, | iflib_busdma_load_mbuf_sg(iflib_txq_t txq, bus_dma_tag_t tag, bus_dmamap_t map, | ||||
struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, | struct mbuf **m0, bus_dma_segment_t *segs, int *nsegs, | ||||
int max_segs, int flags) | int max_segs, int flags) | ||||
{ | { | ||||
if_ctx_t ctx; | if_ctx_t ctx; | ||||
if_shared_ctx_t sctx; | if_shared_ctx_t sctx; | ||||
if_softc_ctx_t scctx; | if_softc_ctx_t scctx; | ||||
int i, next, pidx, mask, err, maxsegsz, ntxd, count; | int i, next, pidx, err, ntxd, count; | ||||
struct mbuf *m, *tmp, **ifsd_m, **mp; | struct mbuf *m, *tmp, **ifsd_m; | ||||
m = *m0; | m = *m0; | ||||
/* | /* | ||||
* Please don't ever do this | * Please don't ever do this | ||||
*/ | */ | ||||
if (__predict_false(m->m_len == 0)) | if (__predict_false(m->m_len == 0)) | ||||
*m0 = m = collapse_pkthdr(m); | *m0 = m = collapse_pkthdr(m); | ||||
ctx = txq->ift_ctx; | ctx = txq->ift_ctx; | ||||
sctx = ctx->ifc_sctx; | sctx = ctx->ifc_sctx; | ||||
scctx = &ctx->ifc_softc_ctx; | scctx = &ctx->ifc_softc_ctx; | ||||
ifsd_m = txq->ift_sds.ifsd_m; | ifsd_m = txq->ift_sds.ifsd_m; | ||||
ntxd = txq->ift_size; | ntxd = txq->ift_size; | ||||
pidx = txq->ift_pidx; | pidx = txq->ift_pidx; | ||||
if (map != NULL) { | if (map != NULL) { | ||||
uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; | uint8_t *ifsd_flags = txq->ift_sds.ifsd_flags; | ||||
err = bus_dmamap_load_mbuf_sg(tag, map, | err = bus_dmamap_load_mbuf_sg(tag, map, | ||||
*m0, segs, nsegs, BUS_DMA_NOWAIT); | *m0, segs, nsegs, BUS_DMA_NOWAIT); | ||||
if (err) | if (err) | ||||
return (err); | return (err); | ||||
ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; | ifsd_flags[pidx] |= TX_SW_DESC_MAPPED; | ||||
i = 0; | count = 0; | ||||
next = pidx; | |||||
mask = (txq->ift_size-1); | |||||
m = *m0; | m = *m0; | ||||
do { | do { | ||||
mp = &ifsd_m[next]; | if (__predict_false(m->m_len <= 0)) { | ||||
*mp = m; | tmp = m; | ||||
m = m->m_next; | m = m->m_next; | ||||
if (__predict_false((*mp)->m_len == 0)) { | tmp->m_next = NULL; | ||||
m_free(*mp); | m_free(tmp); | ||||
*mp = NULL; | continue; | ||||
} else | } | ||||
next = (pidx + i) & (ntxd-1); | m = m->m_next; | ||||
count++; | |||||
} while (m != NULL); | } while (m != NULL); | ||||
if (count > *nsegs) { | |||||
ifsd_m[pidx] = *m0; | |||||
ifsd_m[pidx]->m_flags |= M_TOOBIG; | |||||
return (0); | |||||
} | |||||
m = *m0; | |||||
count = 0; | |||||
do { | |||||
next = (pidx + count) & (ntxd-1); | |||||
MPASS(ifsd_m[next] == NULL); | |||||
ifsd_m[next] = m; | |||||
count++; | |||||
tmp = m; | |||||
m = m->m_next; | |||||
} while (m != NULL); | |||||
} else { | } else { | ||||
int buflen, sgsize, max_sgsize; | int buflen, sgsize, maxsegsz, max_sgsize; | ||||
vm_offset_t vaddr; | vm_offset_t vaddr; | ||||
vm_paddr_t curaddr; | vm_paddr_t curaddr; | ||||
count = i = 0; | count = i = 0; | ||||
maxsegsz = sctx->isc_tx_maxsize; | |||||
m = *m0; | m = *m0; | ||||
if (m->m_pkthdr.csum_flags & CSUM_TSO) | |||||
maxsegsz = scctx->isc_tx_tso_segsize_max; | |||||
else | |||||
maxsegsz = sctx->isc_tx_maxsegsize; | |||||
do { | do { | ||||
if (__predict_false(m->m_len <= 0)) { | if (__predict_false(m->m_len <= 0)) { | ||||
tmp = m; | tmp = m; | ||||
m = m->m_next; | m = m->m_next; | ||||
tmp->m_next = NULL; | tmp->m_next = NULL; | ||||
m_free(tmp); | m_free(tmp); | ||||
continue; | continue; | ||||
} | } | ||||
buflen = m->m_len; | buflen = m->m_len; | ||||
vaddr = (vm_offset_t)m->m_data; | vaddr = (vm_offset_t)m->m_data; | ||||
/* | /* | ||||
* see if we can't be smarter about physically | * see if we can't be smarter about physically | ||||
* contiguous mappings | * contiguous mappings | ||||
*/ | */ | ||||
next = (pidx + count) & (ntxd-1); | next = (pidx + count) & (ntxd-1); | ||||
MPASS(ifsd_m[next] == NULL); | MPASS(ifsd_m[next] == NULL); | ||||
#if MEMORY_LOGGING | #if MEMORY_LOGGING | ||||
txq->ift_enqueued++; | txq->ift_enqueued++; | ||||
#endif | #endif | ||||
ifsd_m[next] = m; | ifsd_m[next] = m; | ||||
while (buflen > 0) { | while (buflen > 0) { | ||||
if (i >= max_segs) | |||||
goto err; | |||||
max_sgsize = MIN(buflen, maxsegsz); | max_sgsize = MIN(buflen, maxsegsz); | ||||
curaddr = pmap_kextract(vaddr); | curaddr = pmap_kextract(vaddr); | ||||
sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); | sgsize = PAGE_SIZE - (curaddr & PAGE_MASK); | ||||
sgsize = MIN(sgsize, max_sgsize); | sgsize = MIN(sgsize, max_sgsize); | ||||
segs[i].ds_addr = curaddr; | segs[i].ds_addr = curaddr; | ||||
segs[i].ds_len = sgsize; | segs[i].ds_len = sgsize; | ||||
vaddr += sgsize; | vaddr += sgsize; | ||||
buflen -= sgsize; | buflen -= sgsize; | ||||
i++; | i++; | ||||
if (i >= max_segs) | |||||
goto err; | |||||
} | } | ||||
count++; | count++; | ||||
tmp = m; | tmp = m; | ||||
m = m->m_next; | m = m->m_next; | ||||
} while (m != NULL); | } while (m != NULL); | ||||
*nsegs = i; | *nsegs = i; | ||||
} | } | ||||
return (0); | return (0); | ||||
err: | err: | ||||
*m0 = iflib_remove_mbuf(txq); | *m0 = iflib_remove_mbuf(txq); | ||||
return (EFBIG); | return (EFBIG); | ||||
} | } | ||||
static inline caddr_t | |||||
calc_next_txd(iflib_txq_t txq, int cidx, uint8_t qid) | |||||
{ | |||||
qidx_t size; | |||||
int ntxd; | |||||
caddr_t start, end, cur, next; | |||||
ntxd = txq->ift_size; | |||||
size = txq->ift_txd_size[qid]; | |||||
start = txq->ift_ifdi[qid].idi_vaddr; | |||||
if (__predict_false(size == 0)) | |||||
return (start); | |||||
cur = start + size*cidx; | |||||
end = start + size*ntxd; | |||||
next = CACHE_PTR_NEXT(cur); | |||||
return (next < end ? next : start); | |||||
} | |||||
/* | |||||
* Pad an mbuf to ensure a minimum ethernet frame size. | |||||
* min_frame_size is the frame size (less CRC) to pad the mbuf to | |||||
*/ | |||||
static __noinline int | |||||
iflib_ether_pad(device_t dev, struct mbuf **m_head, uint16_t min_frame_size) | |||||
{ | |||||
/* | |||||
* 18 is enough bytes to pad an ARP packet to 46 bytes, and | |||||
* and ARP message is the smallest common payload I can think of | |||||
*/ | |||||
static char pad[18]; /* just zeros */ | |||||
int n; | |||||
struct mbuf *new_head; | |||||
if (!M_WRITABLE(*m_head)) { | |||||
new_head = m_dup(*m_head, M_NOWAIT); | |||||
if (new_head == NULL) { | |||||
m_freem(*m_head); | |||||
device_printf(dev, "cannot pad short frame, m_dup() failed"); | |||||
DBG_COUNTER_INC(encap_pad_mbuf_fail); | |||||
return ENOMEM; | |||||
} | |||||
m_freem(*m_head); | |||||
*m_head = new_head; | |||||
} | |||||
for (n = min_frame_size - (*m_head)->m_pkthdr.len; | |||||
n > 0; n -= sizeof(pad)) | |||||
if (!m_append(*m_head, min(n, sizeof(pad)), pad)) | |||||
break; | |||||
if (n > 0) { | |||||
m_freem(*m_head); | |||||
device_printf(dev, "cannot pad short frame\n"); | |||||
DBG_COUNTER_INC(encap_pad_mbuf_fail); | |||||
return (ENOBUFS); | |||||
} | |||||
return 0; | |||||
} | |||||
static int | static int | ||||
iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) | iflib_encap(iflib_txq_t txq, struct mbuf **m_headp) | ||||
{ | { | ||||
if_ctx_t ctx; | if_ctx_t ctx; | ||||
if_shared_ctx_t sctx; | if_shared_ctx_t sctx; | ||||
if_softc_ctx_t scctx; | if_softc_ctx_t scctx; | ||||
bus_dma_segment_t *segs; | bus_dma_segment_t *segs; | ||||
struct mbuf *m_head; | struct mbuf *m_head; | ||||
void *next_txd; | |||||
bus_dmamap_t map; | bus_dmamap_t map; | ||||
struct if_pkt_info pi; | struct if_pkt_info pi; | ||||
int remap = 0; | int remap = 0; | ||||
int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; | int err, nsegs, ndesc, max_segs, pidx, cidx, next, ntxd; | ||||
bus_dma_tag_t desc_tag; | bus_dma_tag_t desc_tag; | ||||
segs = txq->ift_segs; | segs = txq->ift_segs; | ||||
ctx = txq->ift_ctx; | ctx = txq->ift_ctx; | ||||
sctx = ctx->ifc_sctx; | sctx = ctx->ifc_sctx; | ||||
scctx = &ctx->ifc_softc_ctx; | scctx = &ctx->ifc_softc_ctx; | ||||
segs = txq->ift_segs; | segs = txq->ift_segs; | ||||
ntxd = txq->ift_size; | ntxd = txq->ift_size; | ||||
m_head = *m_headp; | m_head = *m_headp; | ||||
map = NULL; | map = NULL; | ||||
/* | /* | ||||
* If we're doing TSO the next descriptor to clean may be quite far ahead | * If we're doing TSO the next descriptor to clean may be quite far ahead | ||||
*/ | */ | ||||
cidx = txq->ift_cidx; | cidx = txq->ift_cidx; | ||||
pidx = txq->ift_pidx; | pidx = txq->ift_pidx; | ||||
if (ctx->ifc_flags & IFC_PREFETCH) { | |||||
next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); | next = (cidx + CACHE_PTR_INCREMENT) & (ntxd-1); | ||||
if (!(ctx->ifc_flags & IFLIB_HAS_TXCQ)) { | |||||
next_txd = calc_next_txd(txq, cidx, 0); | |||||
prefetch(next_txd); | |||||
} | |||||
/* prefetch the next cache line of mbuf pointers and flags */ | /* prefetch the next cache line of mbuf pointers and flags */ | ||||
prefetch(&txq->ift_sds.ifsd_m[next]); | prefetch(&txq->ift_sds.ifsd_m[next]); | ||||
if (txq->ift_sds.ifsd_map != NULL) { | if (txq->ift_sds.ifsd_map != NULL) { | ||||
prefetch(&txq->ift_sds.ifsd_map[next]); | prefetch(&txq->ift_sds.ifsd_map[next]); | ||||
map = txq->ift_sds.ifsd_map[pidx]; | |||||
next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); | next = (cidx + CACHE_LINE_SIZE) & (ntxd-1); | ||||
prefetch(&txq->ift_sds.ifsd_flags[next]); | prefetch(&txq->ift_sds.ifsd_flags[next]); | ||||
} | } | ||||
} else if (txq->ift_sds.ifsd_map != NULL) | |||||
map = txq->ift_sds.ifsd_map[pidx]; | |||||
if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { | if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { | ||||
desc_tag = txq->ift_tso_desc_tag; | desc_tag = txq->ift_tso_desc_tag; | ||||
max_segs = scctx->isc_tx_tso_segments_max; | max_segs = scctx->isc_tx_tso_segments_max; | ||||
} else { | } else { | ||||
desc_tag = txq->ift_desc_tag; | desc_tag = txq->ift_desc_tag; | ||||
max_segs = scctx->isc_tx_nsegments; | max_segs = scctx->isc_tx_nsegments; | ||||
} | } | ||||
if ((sctx->isc_flags & IFLIB_NEED_ETHER_PAD) && | |||||
__predict_false(m_head->m_pkthdr.len < scctx->isc_min_frame_size)) { | |||||
err = iflib_ether_pad(ctx->ifc_dev, m_headp, scctx->isc_min_frame_size); | |||||
if (err) | |||||
return err; | |||||
} | |||||
m_head = *m_headp; | m_head = *m_headp; | ||||
bzero(&pi, sizeof(pi)); | |||||
pi.ipi_len = m_head->m_pkthdr.len; | pkt_info_zero(&pi); | ||||
pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); | pi.ipi_mflags = (m_head->m_flags & (M_VLANTAG|M_BCAST|M_MCAST)); | ||||
pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; | |||||
pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; | |||||
pi.ipi_pidx = pidx; | pi.ipi_pidx = pidx; | ||||
pi.ipi_qsidx = txq->ift_id; | pi.ipi_qsidx = txq->ift_id; | ||||
pi.ipi_len = m_head->m_pkthdr.len; | |||||
pi.ipi_csum_flags = m_head->m_pkthdr.csum_flags; | |||||
pi.ipi_vtag = (m_head->m_flags & M_VLANTAG) ? m_head->m_pkthdr.ether_vtag : 0; | |||||
/* deliberate bitwise OR to make one condition */ | /* deliberate bitwise OR to make one condition */ | ||||
if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { | if (__predict_true((pi.ipi_csum_flags | pi.ipi_vtag))) { | ||||
if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) | if (__predict_false((err = iflib_parse_header(txq, &pi, m_headp)) != 0)) | ||||
return (err); | return (err); | ||||
m_head = *m_headp; | m_head = *m_headp; | ||||
} | } | ||||
Show All 39 Lines | if (__predict_false(nsegs + 2 > TXQ_AVAIL(txq))) { | ||||
txq->ift_no_desc_avail++; | txq->ift_no_desc_avail++; | ||||
if (map != NULL) | if (map != NULL) | ||||
bus_dmamap_unload(desc_tag, map); | bus_dmamap_unload(desc_tag, map); | ||||
DBG_COUNTER_INC(encap_txq_avail_fail); | DBG_COUNTER_INC(encap_txq_avail_fail); | ||||
if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) | if ((txq->ift_task.gt_task.ta_flags & TASK_ENQUEUED) == 0) | ||||
GROUPTASK_ENQUEUE(&txq->ift_task); | GROUPTASK_ENQUEUE(&txq->ift_task); | ||||
return (ENOBUFS); | return (ENOBUFS); | ||||
} | } | ||||
/* | |||||
* On Intel cards we can greatly reduce the number of TX interrupts | |||||
* we see by only setting report status on every Nth descriptor. | |||||
* However, this also means that the driver will need to keep track | |||||
* of the descriptors that RS was set on to check them for the DD bit. | |||||
*/ | |||||
txq->ift_rs_pending += nsegs + 1; | |||||
if (txq->ift_rs_pending > TXQ_MAX_RS_DEFERRED(txq) || | |||||
iflib_no_tx_batch || (TXQ_AVAIL(txq) - nsegs - 1) <= MAX_TX_DESC(ctx)) { | |||||
pi.ipi_flags |= IPI_TX_INTR; | |||||
txq->ift_rs_pending = 0; | |||||
} | |||||
pi.ipi_segs = segs; | pi.ipi_segs = segs; | ||||
pi.ipi_nsegs = nsegs; | pi.ipi_nsegs = nsegs; | ||||
MPASS(pidx >= 0 && pidx < txq->ift_size); | MPASS(pidx >= 0 && pidx < txq->ift_size); | ||||
#ifdef PKT_DEBUG | #ifdef PKT_DEBUG | ||||
print_pkt(&pi); | print_pkt(&pi); | ||||
#endif | #endif | ||||
if (map != NULL) | |||||
bus_dmamap_sync(desc_tag, map, BUS_DMASYNC_PREWRITE); | |||||
if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { | if ((err = ctx->isc_txd_encap(ctx->ifc_softc, &pi)) == 0) { | ||||
if (map != NULL) | |||||
bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, | bus_dmamap_sync(txq->ift_ifdi->idi_tag, txq->ift_ifdi->idi_map, | ||||
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); | BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); | ||||
DBG_COUNTER_INC(tx_encap); | DBG_COUNTER_INC(tx_encap); | ||||
MPASS(pi.ipi_new_pidx >= 0 && | MPASS(pi.ipi_new_pidx < txq->ift_size); | ||||
pi.ipi_new_pidx < txq->ift_size); | |||||
ndesc = pi.ipi_new_pidx - pi.ipi_pidx; | ndesc = pi.ipi_new_pidx - pi.ipi_pidx; | ||||
if (pi.ipi_new_pidx < pi.ipi_pidx) { | if (pi.ipi_new_pidx < pi.ipi_pidx) { | ||||
ndesc += txq->ift_size; | ndesc += txq->ift_size; | ||||
txq->ift_gen = 1; | txq->ift_gen = 1; | ||||
} | } | ||||
/* | |||||
* drivers can need as many as | |||||
* two sentinels | |||||
*/ | |||||
MPASS(ndesc <= pi.ipi_nsegs + 2); | |||||
MPASS(pi.ipi_new_pidx != pidx); | MPASS(pi.ipi_new_pidx != pidx); | ||||
MPASS(ndesc > 0); | MPASS(ndesc > 0); | ||||
txq->ift_in_use += ndesc; | txq->ift_in_use += ndesc; | ||||
/* | /* | ||||
* We update the last software descriptor again here because there may | * We update the last software descriptor again here because there may | ||||
* be a sentinel and/or there may be more mbufs than segments | * be a sentinel and/or there may be more mbufs than segments | ||||
*/ | */ | ||||
txq->ift_pidx = pi.ipi_new_pidx; | txq->ift_pidx = pi.ipi_new_pidx; | ||||
txq->ift_npending += pi.ipi_ndescs; | txq->ift_npending += pi.ipi_ndescs; | ||||
} else if (__predict_false(err == EFBIG && remap < 2)) { | } else if (__predict_false(err == EFBIG && remap < 2)) { | ||||
*m_headp = m_head = iflib_remove_mbuf(txq); | *m_headp = m_head = iflib_remove_mbuf(txq); | ||||
remap = 1; | remap = 1; | ||||
txq->ift_txd_encap_efbig++; | txq->ift_txd_encap_efbig++; | ||||
goto defrag; | goto defrag; | ||||
} else | } else | ||||
DBG_COUNTER_INC(encap_txd_encap_fail); | DBG_COUNTER_INC(encap_txd_encap_fail); | ||||
return (err); | return (err); | ||||
defrag_failed: | defrag_failed: | ||||
txq->ift_mbuf_defrag_failed++; | txq->ift_mbuf_defrag_failed++; | ||||
txq->ift_map_failed++; | txq->ift_map_failed++; | ||||
m_freem(*m_headp); | m_freem(*m_headp); | ||||
DBG_COUNTER_INC(tx_frees); | DBG_COUNTER_INC(tx_frees); | ||||
*m_headp = NULL; | *m_headp = NULL; | ||||
return (ENOMEM); | return (ENOMEM); | ||||
} | } | ||||
/* forward compatibility for cxgb */ | |||||
#define FIRST_QSET(ctx) 0 | |||||
#define NTXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_ntxqsets) | |||||
#define NRXQSETS(ctx) ((ctx)->ifc_softc_ctx.isc_nrxqsets) | |||||
#define QIDX(ctx, m) ((((m)->m_pkthdr.flowid & ctx->ifc_softc_ctx.isc_rss_table_mask) % NTXQSETS(ctx)) + FIRST_QSET(ctx)) | |||||
#define DESC_RECLAIMABLE(q) ((int)((q)->ift_processed - (q)->ift_cleaned - (q)->ift_ctx->ifc_softc_ctx.isc_tx_nsegments)) | |||||
#define RECLAIM_THRESH(ctx) ((ctx)->ifc_sctx->isc_tx_reclaim_thresh) | |||||
#define MAX_TX_DESC(ctx) ((ctx)->ifc_softc_ctx.isc_tx_tso_segments_max) | |||||
/* if there are more than TXQ_MIN_OCCUPANCY packets pending we consider deferring | |||||
* doorbell writes | |||||
* | |||||
* ORing with 2 assures that min occupancy is never less than 2 without any conditional logic | |||||
*/ | |||||
#define TXQ_MIN_OCCUPANCY(size) ((size >> 6)| 0x2) | |||||
static inline int | |||||
iflib_txq_min_occupancy(iflib_txq_t txq) | |||||
{ | |||||
if_ctx_t ctx; | |||||
ctx = txq->ift_ctx; | |||||
return (get_inuse(txq->ift_size, txq->ift_cidx, txq->ift_pidx, | |||||
txq->ift_gen) < TXQ_MIN_OCCUPANCY(txq->ift_size) + | |||||
MAX_TX_DESC(ctx)); | |||||
} | |||||
static void | static void | ||||
iflib_tx_desc_free(iflib_txq_t txq, int n) | iflib_tx_desc_free(iflib_txq_t txq, int n) | ||||
{ | { | ||||
int hasmap; | int hasmap; | ||||
uint32_t qsize, cidx, mask, gen; | uint32_t qsize, cidx, mask, gen; | ||||
struct mbuf *m, **ifsd_m; | struct mbuf *m, **ifsd_m; | ||||
uint8_t *ifsd_flags; | uint8_t *ifsd_flags; | ||||
bus_dmamap_t *ifsd_map; | bus_dmamap_t *ifsd_map; | ||||
bool do_prefetch; | |||||
cidx = txq->ift_cidx; | cidx = txq->ift_cidx; | ||||
gen = txq->ift_gen; | gen = txq->ift_gen; | ||||
qsize = txq->ift_size; | qsize = txq->ift_size; | ||||
mask = qsize-1; | mask = qsize-1; | ||||
hasmap = txq->ift_sds.ifsd_map != NULL; | hasmap = txq->ift_sds.ifsd_map != NULL; | ||||
ifsd_flags = txq->ift_sds.ifsd_flags; | ifsd_flags = txq->ift_sds.ifsd_flags; | ||||
ifsd_m = txq->ift_sds.ifsd_m; | ifsd_m = txq->ift_sds.ifsd_m; | ||||
ifsd_map = txq->ift_sds.ifsd_map; | ifsd_map = txq->ift_sds.ifsd_map; | ||||
do_prefetch = (txq->ift_ctx->ifc_flags & IFC_PREFETCH); | |||||
while (n--) { | while (n--) { | ||||
if (do_prefetch) { | |||||
prefetch(ifsd_m[(cidx + 3) & mask]); | prefetch(ifsd_m[(cidx + 3) & mask]); | ||||
prefetch(ifsd_m[(cidx + 4) & mask]); | prefetch(ifsd_m[(cidx + 4) & mask]); | ||||
} | |||||
if (ifsd_m[cidx] != NULL) { | if (ifsd_m[cidx] != NULL) { | ||||
prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); | prefetch(&ifsd_m[(cidx + CACHE_PTR_INCREMENT) & mask]); | ||||
prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); | prefetch(&ifsd_flags[(cidx + CACHE_PTR_INCREMENT) & mask]); | ||||
if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { | if (hasmap && (ifsd_flags[cidx] & TX_SW_DESC_MAPPED)) { | ||||
/* | /* | ||||
* does it matter if it's not the TSO tag? If so we'll | * does it matter if it's not the TSO tag? If so we'll | ||||
* have to add the type to flags | * have to add the type to flags | ||||
*/ | */ | ||||
bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); | bus_dmamap_unload(txq->ift_desc_tag, ifsd_map[cidx]); | ||||
ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; | ifsd_flags[cidx] &= ~TX_SW_DESC_MAPPED; | ||||
} | } | ||||
if ((m = ifsd_m[cidx]) != NULL) { | if ((m = ifsd_m[cidx]) != NULL) { | ||||
/* XXX we don't support any drivers that batch packets yet */ | /* XXX we don't support any drivers that batch packets yet */ | ||||
MPASS(m->m_nextpkt == NULL); | MPASS(m->m_nextpkt == NULL); | ||||
/* if the number of clusters exceeds the number of segments | |||||
* there won't be space on the ring to save a pointer to each | |||||
* cluster so we simply free the list here | |||||
*/ | |||||
if (m->m_flags & M_TOOBIG) { | |||||
m_freem(m); | |||||
} else { | |||||
m_free(m); | m_free(m); | ||||
} | |||||
ifsd_m[cidx] = NULL; | ifsd_m[cidx] = NULL; | ||||
#if MEMORY_LOGGING | #if MEMORY_LOGGING | ||||
txq->ift_dequeued++; | txq->ift_dequeued++; | ||||
#endif | #endif | ||||
DBG_COUNTER_INC(tx_frees); | DBG_COUNTER_INC(tx_frees); | ||||
} | } | ||||
} | } | ||||
if (__predict_false(++cidx == qsize)) { | if (__predict_false(++cidx == qsize)) { | ||||
Show All 30 Lines | #ifdef INVARIANTS | ||||
} | } | ||||
#endif | #endif | ||||
return (0); | return (0); | ||||
} | } | ||||
iflib_tx_desc_free(txq, reclaim); | iflib_tx_desc_free(txq, reclaim); | ||||
txq->ift_cleaned += reclaim; | txq->ift_cleaned += reclaim; | ||||
txq->ift_in_use -= reclaim; | txq->ift_in_use -= reclaim; | ||||
if (txq->ift_active == FALSE) | |||||
txq->ift_active = TRUE; | |||||
return (reclaim); | return (reclaim); | ||||
} | } | ||||
static struct mbuf ** | static struct mbuf ** | ||||
_ring_peek_one(struct ifmp_ring *r, int cidx, int offset) | _ring_peek_one(struct ifmp_ring *r, int cidx, int offset, int remaining) | ||||
{ | { | ||||
int next, size; | |||||
struct mbuf **items; | |||||
return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (r->size-1)])); | size = r->size; | ||||
next = (cidx + CACHE_PTR_INCREMENT) & (size-1); | |||||
items = __DEVOLATILE(struct mbuf **, &r->items[0]); | |||||
prefetch(items[(cidx + offset) & (size-1)]); | |||||
if (remaining > 1) { | |||||
prefetch2cachelines(&items[next]); | |||||
prefetch2cachelines(items[(cidx + offset + 1) & (size-1)]); | |||||
prefetch2cachelines(items[(cidx + offset + 2) & (size-1)]); | |||||
prefetch2cachelines(items[(cidx + offset + 3) & (size-1)]); | |||||
} | } | ||||
return (__DEVOLATILE(struct mbuf **, &r->items[(cidx + offset) & (size-1)])); | |||||
} | |||||
static void | static void | ||||
iflib_txq_check_drain(iflib_txq_t txq, int budget) | iflib_txq_check_drain(iflib_txq_t txq, int budget) | ||||
{ | { | ||||
ifmp_ring_check_drainage(txq->ift_br[0], budget); | ifmp_ring_check_drainage(txq->ift_br, budget); | ||||
} | } | ||||
static uint32_t | static uint32_t | ||||
iflib_txq_can_drain(struct ifmp_ring *r) | iflib_txq_can_drain(struct ifmp_ring *r) | ||||
{ | { | ||||
iflib_txq_t txq = r->cookie; | iflib_txq_t txq = r->cookie; | ||||
if_ctx_t ctx = txq->ift_ctx; | if_ctx_t ctx = txq->ift_ctx; | ||||
return ((TXQ_AVAIL(txq) >= MAX_TX_DESC(ctx)) || | return ((TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2) || | ||||
ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, txq->ift_cidx_processed, false)); | ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)); | ||||
} | } | ||||
static uint32_t | static uint32_t | ||||
iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) | iflib_txq_drain(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) | ||||
{ | { | ||||
iflib_txq_t txq = r->cookie; | iflib_txq_t txq = r->cookie; | ||||
if_ctx_t ctx = txq->ift_ctx; | if_ctx_t ctx = txq->ift_ctx; | ||||
if_t ifp = ctx->ifc_ifp; | struct ifnet *ifp = ctx->ifc_ifp; | ||||
struct mbuf **mp, *m; | struct mbuf **mp, *m; | ||||
int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail, err, in_use_prev, desc_used; | int i, count, consumed, pkt_sent, bytes_sent, mcast_sent, avail; | ||||
int reclaimed, err, in_use_prev, desc_used; | |||||
bool do_prefetch, ring, rang; | |||||
if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || | if (__predict_false(!(if_getdrvflags(ifp) & IFF_DRV_RUNNING) || | ||||
!LINK_ACTIVE(ctx))) { | !LINK_ACTIVE(ctx))) { | ||||
DBG_COUNTER_INC(txq_drain_notready); | DBG_COUNTER_INC(txq_drain_notready); | ||||
return (0); | return (0); | ||||
} | } | ||||
reclaimed = iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); | |||||
rang = iflib_txd_db_check(ctx, txq, reclaimed, txq->ift_in_use); | |||||
avail = IDXDIFF(pidx, cidx, r->size); | avail = IDXDIFF(pidx, cidx, r->size); | ||||
if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { | if (__predict_false(ctx->ifc_flags & IFC_QFLUSH)) { | ||||
DBG_COUNTER_INC(txq_drain_flushing); | DBG_COUNTER_INC(txq_drain_flushing); | ||||
for (i = 0; i < avail; i++) { | for (i = 0; i < avail; i++) { | ||||
m_free(r->items[(cidx + i) & (r->size-1)]); | m_free(r->items[(cidx + i) & (r->size-1)]); | ||||
r->items[(cidx + i) & (r->size-1)] = NULL; | r->items[(cidx + i) & (r->size-1)] = NULL; | ||||
} | } | ||||
return (avail); | return (avail); | ||||
} | } | ||||
iflib_completed_tx_reclaim(txq, RECLAIM_THRESH(ctx)); | |||||
if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { | if (__predict_false(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { | ||||
txq->ift_qstatus = IFLIB_QUEUE_IDLE; | txq->ift_qstatus = IFLIB_QUEUE_IDLE; | ||||
CALLOUT_LOCK(txq); | CALLOUT_LOCK(txq); | ||||
callout_stop(&txq->ift_timer); | callout_stop(&txq->ift_timer); | ||||
callout_stop(&txq->ift_db_check); | |||||
CALLOUT_UNLOCK(txq); | CALLOUT_UNLOCK(txq); | ||||
DBG_COUNTER_INC(txq_drain_oactive); | DBG_COUNTER_INC(txq_drain_oactive); | ||||
return (0); | return (0); | ||||
} | } | ||||
if (reclaimed) | |||||
txq->ift_qstatus = IFLIB_QUEUE_IDLE; | |||||
consumed = mcast_sent = bytes_sent = pkt_sent = 0; | consumed = mcast_sent = bytes_sent = pkt_sent = 0; | ||||
count = MIN(avail, TX_BATCH_SIZE); | count = MIN(avail, TX_BATCH_SIZE); | ||||
#ifdef INVARIANTS | |||||
if (iflib_verbose_debug) | |||||
printf("%s avail=%d ifc_flags=%x txq_avail=%d ", __FUNCTION__, | |||||
avail, ctx->ifc_flags, TXQ_AVAIL(txq)); | |||||
#endif | |||||
do_prefetch = (ctx->ifc_flags & IFC_PREFETCH); | |||||
avail = TXQ_AVAIL(txq); | |||||
for (desc_used = i = 0; i < count && avail > MAX_TX_DESC(ctx) + 2; i++) { | |||||
int pidx_prev, rem = do_prefetch ? count - i : 0; | |||||
for (desc_used = i = 0; i < count && TXQ_AVAIL(txq) > MAX_TX_DESC(ctx) + 2; i++) { | mp = _ring_peek_one(r, cidx, i, rem); | ||||
mp = _ring_peek_one(r, cidx, i); | MPASS(mp != NULL && *mp != NULL); | ||||
if (__predict_false(*mp == (struct mbuf *)txq)) { | |||||
consumed++; | |||||
reclaimed++; | |||||
continue; | |||||
} | |||||
in_use_prev = txq->ift_in_use; | in_use_prev = txq->ift_in_use; | ||||
pidx_prev = txq->ift_pidx; | |||||
err = iflib_encap(txq, mp); | err = iflib_encap(txq, mp); | ||||
/* | if (__predict_false(err)) { | ||||
* What other errors should we bail out for? | |||||
*/ | |||||
if (err == ENOBUFS) { | |||||
DBG_COUNTER_INC(txq_drain_encapfail); | DBG_COUNTER_INC(txq_drain_encapfail); | ||||
/* no room - bail out */ | |||||
if (err == ENOBUFS) | |||||
break; | break; | ||||
} | |||||
consumed++; | consumed++; | ||||
if (err) | DBG_COUNTER_INC(txq_drain_encapfail); | ||||
/* we can't send this packet - skip it */ | |||||
continue; | continue; | ||||
} | |||||
consumed++; | |||||
pkt_sent++; | pkt_sent++; | ||||
m = *mp; | m = *mp; | ||||
DBG_COUNTER_INC(tx_sent); | DBG_COUNTER_INC(tx_sent); | ||||
bytes_sent += m->m_pkthdr.len; | bytes_sent += m->m_pkthdr.len; | ||||
if (m->m_flags & M_MCAST) | mcast_sent += !!(m->m_flags & M_MCAST); | ||||
mcast_sent++; | avail = TXQ_AVAIL(txq); | ||||
txq->ift_db_pending += (txq->ift_in_use - in_use_prev); | txq->ift_db_pending += (txq->ift_in_use - in_use_prev); | ||||
desc_used += (txq->ift_in_use - in_use_prev); | desc_used += (txq->ift_in_use - in_use_prev); | ||||
iflib_txd_db_check(ctx, txq, FALSE); | |||||
ETHER_BPF_MTAP(ifp, m); | ETHER_BPF_MTAP(ifp, m); | ||||
if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) | if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) | ||||
break; | break; | ||||
rang = iflib_txd_db_check(ctx, txq, false, in_use_prev); | |||||
if (desc_used > TXQ_MAX_DB_CONSUMED(txq->ift_size)) | |||||
break; | |||||
} | } | ||||
if ((iflib_min_tx_latency || iflib_txq_min_occupancy(txq)) && txq->ift_db_pending) | /* deliberate use of bitwise or to avoid gratuitous short-circuit */ | ||||
iflib_txd_db_check(ctx, txq, TRUE); | ring = rang ? false : (iflib_min_tx_latency | err) || (TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)); | ||||
else if ((txq->ift_db_pending || TXQ_AVAIL(txq) < MAX_TX_DESC(ctx)) && | iflib_txd_db_check(ctx, txq, ring, txq->ift_in_use); | ||||
(callout_pending(&txq->ift_db_check) == 0)) { | |||||
txq->ift_db_pending_queued = txq->ift_db_pending; | |||||
callout_reset_on(&txq->ift_db_check, 1, iflib_txd_deferred_db_check, | |||||
txq, txq->ift_db_check.c_cpu); | |||||
} | |||||
if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); | if_inc_counter(ifp, IFCOUNTER_OBYTES, bytes_sent); | ||||
if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); | if_inc_counter(ifp, IFCOUNTER_OPACKETS, pkt_sent); | ||||
if (mcast_sent) | if (mcast_sent) | ||||
if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); | if_inc_counter(ifp, IFCOUNTER_OMCASTS, mcast_sent); | ||||
#ifdef INVARIANTS | |||||
if (iflib_verbose_debug) | |||||
printf("consumed=%d\n", consumed); | |||||
#endif | |||||
return (consumed); | return (consumed); | ||||
} | } | ||||
static uint32_t | |||||
iflib_txq_drain_always(struct ifmp_ring *r) | |||||
{ | |||||
return (1); | |||||
} | |||||
static uint32_t | |||||
iflib_txq_drain_free(struct ifmp_ring *r, uint32_t cidx, uint32_t pidx) | |||||
{ | |||||
int i, avail; | |||||
struct mbuf **mp; | |||||
iflib_txq_t txq; | |||||
txq = r->cookie; | |||||
txq->ift_qstatus = IFLIB_QUEUE_IDLE; | |||||
CALLOUT_LOCK(txq); | |||||
callout_stop(&txq->ift_timer); | |||||
CALLOUT_UNLOCK(txq); | |||||
avail = IDXDIFF(pidx, cidx, r->size); | |||||
for (i = 0; i < avail; i++) { | |||||
mp = _ring_peek_one(r, cidx, i, avail - i); | |||||
if (__predict_false(*mp == (struct mbuf *)txq)) | |||||
continue; | |||||
m_freem(*mp); | |||||
} | |||||
MPASS(ifmp_ring_is_stalled(r) == 0); | |||||
return (avail); | |||||
} | |||||
static void | static void | ||||
iflib_ifmp_purge(iflib_txq_t txq) | |||||
{ | |||||
struct ifmp_ring *r; | |||||
r = txq->ift_br; | |||||
r->drain = iflib_txq_drain_free; | |||||
r->can_drain = iflib_txq_drain_always; | |||||
ifmp_ring_check_drainage(r, r->size); | |||||
r->drain = iflib_txq_drain; | |||||
r->can_drain = iflib_txq_can_drain; | |||||
} | |||||
static void | |||||
_task_fn_tx(void *context) | _task_fn_tx(void *context) | ||||
{ | { | ||||
iflib_txq_t txq = context; | iflib_txq_t txq = context; | ||||
if_ctx_t ctx = txq->ift_ctx; | if_ctx_t ctx = txq->ift_ctx; | ||||
struct ifnet *ifp = ctx->ifc_ifp; | |||||
int rc; | |||||
#ifdef IFLIB_DIAGNOSTICS | |||||
txq->ift_cpu_exec_count[curcpu]++; | |||||
#endif | |||||
if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) | if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) | ||||
return; | return; | ||||
ifmp_ring_check_drainage(txq->ift_br[0], TX_BATCH_SIZE); | if (if_getcapenable(ifp) & IFCAP_NETMAP) { | ||||
if (ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, false)) | |||||
netmap_tx_irq(ifp, txq->ift_id); | |||||
IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); | |||||
return; | |||||
} | } | ||||
if (txq->ift_db_pending) | |||||
ifmp_ring_enqueue(txq->ift_br, (void **)&txq, 1, TX_BATCH_SIZE); | |||||
ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); | |||||
if (ctx->ifc_flags & IFC_LEGACY) | |||||
IFDI_INTR_ENABLE(ctx); | |||||
else { | |||||
rc = IFDI_TX_QUEUE_INTR_ENABLE(ctx, txq->ift_id); | |||||
KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); | |||||
} | |||||
} | |||||
static void | static void | ||||
_task_fn_rx(void *context) | _task_fn_rx(void *context) | ||||
{ | { | ||||
iflib_rxq_t rxq = context; | iflib_rxq_t rxq = context; | ||||
if_ctx_t ctx = rxq->ifr_ctx; | if_ctx_t ctx = rxq->ifr_ctx; | ||||
bool more; | bool more; | ||||
int rc; | int rc; | ||||
uint16_t budget; | |||||
#ifdef IFLIB_DIAGNOSTICS | |||||
rxq->ifr_cpu_exec_count[curcpu]++; | |||||
#endif | |||||
DBG_COUNTER_INC(task_fn_rxs); | DBG_COUNTER_INC(task_fn_rxs); | ||||
if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) | if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) | ||||
return; | return; | ||||
more = true; | |||||
if ((more = iflib_rxeof(rxq, 16 /* XXX */)) == false) { | #ifdef DEV_NETMAP | ||||
if (if_getcapenable(ctx->ifc_ifp) & IFCAP_NETMAP) { | |||||
u_int work = 0; | |||||
if (netmap_rx_irq(ctx->ifc_ifp, rxq->ifr_id, &work)) { | |||||
more = false; | |||||
} | |||||
} | |||||
#endif | |||||
budget = ctx->ifc_sysctl_rx_budget; | |||||
if (budget == 0) | |||||
budget = 16; /* XXX */ | |||||
if (more == false || (more = iflib_rxeof(rxq, budget)) == false) { | |||||
if (ctx->ifc_flags & IFC_LEGACY) | if (ctx->ifc_flags & IFC_LEGACY) | ||||
IFDI_INTR_ENABLE(ctx); | IFDI_INTR_ENABLE(ctx); | ||||
else { | else { | ||||
DBG_COUNTER_INC(rx_intr_enables); | DBG_COUNTER_INC(rx_intr_enables); | ||||
rc = IFDI_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); | rc = IFDI_RX_QUEUE_INTR_ENABLE(ctx, rxq->ifr_id); | ||||
KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); | KASSERT(rc != ENOTSUP, ("MSI-X support requires queue_intr_enable, but not implemented in driver")); | ||||
} | } | ||||
} | } | ||||
if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) | if (__predict_false(!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING))) | ||||
return; | return; | ||||
if (more) | if (more) | ||||
GROUPTASK_ENQUEUE(&rxq->ifr_task); | GROUPTASK_ENQUEUE(&rxq->ifr_task); | ||||
} | } | ||||
static void | static void | ||||
_task_fn_admin(void *context) | _task_fn_admin(void *context) | ||||
{ | { | ||||
if_ctx_t ctx = context; | if_ctx_t ctx = context; | ||||
if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; | if_softc_ctx_t sctx = &ctx->ifc_softc_ctx; | ||||
iflib_txq_t txq; | iflib_txq_t txq; | ||||
int i; | int i; | ||||
if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) | if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_RUNNING)) { | ||||
if (!(if_getdrvflags(ctx->ifc_ifp) & IFF_DRV_OACTIVE)) { | |||||
return; | return; | ||||
} | |||||
} | |||||
CTX_LOCK(ctx); | CTX_LOCK(ctx); | ||||
for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { | for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) { | ||||
CALLOUT_LOCK(txq); | CALLOUT_LOCK(txq); | ||||
callout_stop(&txq->ift_timer); | callout_stop(&txq->ift_timer); | ||||
CALLOUT_UNLOCK(txq); | CALLOUT_UNLOCK(txq); | ||||
} | } | ||||
IFDI_UPDATE_ADMIN_STATUS(ctx); | IFDI_UPDATE_ADMIN_STATUS(ctx); | ||||
for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) | for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) | ||||
callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); | callout_reset_on(&txq->ift_timer, hz/2, iflib_timer, txq, txq->ift_timer.c_cpu); | ||||
IFDI_LINK_INTR_ENABLE(ctx); | IFDI_LINK_INTR_ENABLE(ctx); | ||||
if (ctx->ifc_flags & IFC_DO_RESET) { | |||||
ctx->ifc_flags &= ~IFC_DO_RESET; | |||||
iflib_if_init_locked(ctx); | |||||
} | |||||
CTX_UNLOCK(ctx); | CTX_UNLOCK(ctx); | ||||
if (LINK_ACTIVE(ctx) == 0) | if (LINK_ACTIVE(ctx) == 0) | ||||
return; | return; | ||||
for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) | for (txq = ctx->ifc_txqs, i = 0; i < sctx->isc_ntxqsets; i++, txq++) | ||||
iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); | iflib_txq_check_drain(txq, IFLIB_RESTART_BUDGET); | ||||
} | } | ||||
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines | iflib_if_transmit(if_t ifp, struct mbuf *m) | ||||
if_ctx_t ctx = if_getsoftc(ifp); | if_ctx_t ctx = if_getsoftc(ifp); | ||||
iflib_txq_t txq; | iflib_txq_t txq; | ||||
int err, qidx; | int err, qidx; | ||||
if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { | if (__predict_false((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || !LINK_ACTIVE(ctx))) { | ||||
DBG_COUNTER_INC(tx_frees); | DBG_COUNTER_INC(tx_frees); | ||||
m_freem(m); | m_freem(m); | ||||
return (0); | return (ENOBUFS); | ||||
} | } | ||||
MPASS(m->m_nextpkt == NULL); | MPASS(m->m_nextpkt == NULL); | ||||
qidx = 0; | qidx = 0; | ||||
if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) | if ((NTXQSETS(ctx) > 1) && M_HASHTYPE_GET(m)) | ||||
qidx = QIDX(ctx, m); | qidx = QIDX(ctx, m); | ||||
/* | /* | ||||
* XXX calculate buf_ring based on flowid (divvy up bits?) | * XXX calculate buf_ring based on flowid (divvy up bits?) | ||||
Show All 30 Lines | if (count > nitems(marr)) | ||||
} | } | ||||
for (next = m, i = 0; next != NULL; i++) { | for (next = m, i = 0; next != NULL; i++) { | ||||
mp[i] = next; | mp[i] = next; | ||||
next = next->m_nextpkt; | next = next->m_nextpkt; | ||||
mp[i]->m_nextpkt = NULL; | mp[i]->m_nextpkt = NULL; | ||||
} | } | ||||
#endif | #endif | ||||
DBG_COUNTER_INC(tx_seen); | DBG_COUNTER_INC(tx_seen); | ||||
err = ifmp_ring_enqueue(txq->ift_br[0], (void **)&m, 1, TX_BATCH_SIZE); | err = ifmp_ring_enqueue(txq->ift_br, (void **)&m, 1, TX_BATCH_SIZE); | ||||
if (err) { | |||||
GROUPTASK_ENQUEUE(&txq->ift_task); | GROUPTASK_ENQUEUE(&txq->ift_task); | ||||
if (err) { | |||||
/* support forthcoming later */ | /* support forthcoming later */ | ||||
#ifdef DRIVER_BACKPRESSURE | #ifdef DRIVER_BACKPRESSURE | ||||
txq->ift_closed = TRUE; | txq->ift_closed = TRUE; | ||||
#endif | #endif | ||||
ifmp_ring_check_drainage(txq->ift_br[0], TX_BATCH_SIZE); | ifmp_ring_check_drainage(txq->ift_br, TX_BATCH_SIZE); | ||||
m_freem(m); | m_freem(m); | ||||
} else if (TXQ_AVAIL(txq) < (txq->ift_size >> 1)) { | |||||
GROUPTASK_ENQUEUE(&txq->ift_task); | |||||
} | } | ||||
return (err); | return (err); | ||||
} | } | ||||
static void | static void | ||||
iflib_if_qflush(if_t ifp) | iflib_if_qflush(if_t ifp) | ||||
{ | { | ||||
if_ctx_t ctx = if_getsoftc(ifp); | if_ctx_t ctx = if_getsoftc(ifp); | ||||
iflib_txq_t txq = ctx->ifc_txqs; | iflib_txq_t txq = ctx->ifc_txqs; | ||||
int i; | int i; | ||||
CTX_LOCK(ctx); | CTX_LOCK(ctx); | ||||
ctx->ifc_flags |= IFC_QFLUSH; | ctx->ifc_flags |= IFC_QFLUSH; | ||||
CTX_UNLOCK(ctx); | CTX_UNLOCK(ctx); | ||||
for (i = 0; i < NTXQSETS(ctx); i++, txq++) | for (i = 0; i < NTXQSETS(ctx); i++, txq++) | ||||
while (!(ifmp_ring_is_idle(txq->ift_br[0]) || ifmp_ring_is_stalled(txq->ift_br[0]))) | while (!(ifmp_ring_is_idle(txq->ift_br) || ifmp_ring_is_stalled(txq->ift_br))) | ||||
iflib_txq_check_drain(txq, 0); | iflib_txq_check_drain(txq, 0); | ||||
CTX_LOCK(ctx); | CTX_LOCK(ctx); | ||||
ctx->ifc_flags &= ~IFC_QFLUSH; | ctx->ifc_flags &= ~IFC_QFLUSH; | ||||
CTX_UNLOCK(ctx); | CTX_UNLOCK(ctx); | ||||
if_qflush(ifp); | if_qflush(ifp); | ||||
} | } | ||||
#define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ | #define IFCAP_FLAGS (IFCAP_TXCSUM_IPV6 | IFCAP_RXCSUM_IPV6 | IFCAP_HWCSUM | IFCAP_LRO | \ | ||||
IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | \ | IFCAP_TSO4 | IFCAP_TSO6 | IFCAP_VLAN_HWTAGGING | IFCAP_HWSTATS | \ | ||||
IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) | IFCAP_VLAN_MTU | IFCAP_VLAN_HWFILTER | IFCAP_VLAN_HWTSO) | ||||
#define IFCAP_REINIT IFCAP_FLAGS | |||||
static int | static int | ||||
iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) | iflib_if_ioctl(if_t ifp, u_long command, caddr_t data) | ||||
{ | { | ||||
if_ctx_t ctx = if_getsoftc(ifp); | if_ctx_t ctx = if_getsoftc(ifp); | ||||
struct ifreq *ifr = (struct ifreq *)data; | struct ifreq *ifr = (struct ifreq *)data; | ||||
#if defined(INET) || defined(INET6) | #if defined(INET) || defined(INET6) | ||||
struct ifaddr *ifa = (struct ifaddr *)data; | struct ifaddr *ifa = (struct ifaddr *)data; | ||||
#endif | #endif | ||||
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines | if (if_getflags(ifp) & IFF_UP) { | ||||
} else | } else | ||||
reinit = 1; | reinit = 1; | ||||
} else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { | } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { | ||||
iflib_stop(ctx); | iflib_stop(ctx); | ||||
} | } | ||||
ctx->ifc_if_flags = if_getflags(ifp); | ctx->ifc_if_flags = if_getflags(ifp); | ||||
CTX_UNLOCK(ctx); | CTX_UNLOCK(ctx); | ||||
break; | break; | ||||
break; | |||||
case SIOCADDMULTI: | case SIOCADDMULTI: | ||||
case SIOCDELMULTI: | case SIOCDELMULTI: | ||||
if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { | if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { | ||||
CTX_LOCK(ctx); | CTX_LOCK(ctx); | ||||
IFDI_INTR_DISABLE(ctx); | IFDI_INTR_DISABLE(ctx); | ||||
IFDI_MULTI_SET(ctx); | IFDI_MULTI_SET(ctx); | ||||
IFDI_INTR_ENABLE(ctx); | IFDI_INTR_ENABLE(ctx); | ||||
CTX_UNLOCK(ctx); | CTX_UNLOCK(ctx); | ||||
} | } | ||||
break; | break; | ||||
case SIOCSIFMEDIA: | case SIOCSIFMEDIA: | ||||
CTX_LOCK(ctx); | CTX_LOCK(ctx); | ||||
IFDI_MEDIA_SET(ctx); | IFDI_MEDIA_SET(ctx); | ||||
CTX_UNLOCK(ctx); | CTX_UNLOCK(ctx); | ||||
/* falls thru */ | /* falls thru */ | ||||
case SIOCGIFMEDIA: | case SIOCGIFMEDIA: | ||||
case SIOCGIFXMEDIA: | |||||
err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); | err = ifmedia_ioctl(ifp, ifr, &ctx->ifc_media, command); | ||||
break; | break; | ||||
case SIOCGI2C: | case SIOCGI2C: | ||||
{ | { | ||||
struct ifi2creq i2c; | struct ifi2creq i2c; | ||||
err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); | err = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); | ||||
if (err != 0) | if (err != 0) | ||||
Show All 18 Lines | case SIOCSIFCAP: | ||||
mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); | mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); | ||||
setmask = 0; | setmask = 0; | ||||
#ifdef TCP_OFFLOAD | #ifdef TCP_OFFLOAD | ||||
setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); | setmask |= mask & (IFCAP_TOE4|IFCAP_TOE6); | ||||
#endif | #endif | ||||
setmask |= (mask & IFCAP_FLAGS); | setmask |= (mask & IFCAP_FLAGS); | ||||
if (setmask & (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6)) | |||||
setmask |= (IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6); | |||||
if ((mask & IFCAP_WOL) && | if ((mask & IFCAP_WOL) && | ||||
(if_getcapabilities(ifp) & IFCAP_WOL) != 0) | (if_getcapabilities(ifp) & IFCAP_WOL) != 0) | ||||
setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); | setmask |= (mask & (IFCAP_WOL_MCAST|IFCAP_WOL_MAGIC)); | ||||
if_vlancap(ifp); | if_vlancap(ifp); | ||||
/* | /* | ||||
* want to ensure that traffic has stopped before we change any of the flags | * want to ensure that traffic has stopped before we change any of the flags | ||||
*/ | */ | ||||
if (setmask) { | if (setmask) { | ||||
CTX_LOCK(ctx); | CTX_LOCK(ctx); | ||||
bits = if_getdrvflags(ifp); | bits = if_getdrvflags(ifp); | ||||
if (setmask & IFCAP_REINIT) | if (bits & IFF_DRV_RUNNING) | ||||
iflib_stop(ctx); | iflib_stop(ctx); | ||||
if_togglecapenable(ifp, setmask); | if_togglecapenable(ifp, setmask); | ||||
if (setmask & IFCAP_REINIT) | if (bits & IFF_DRV_RUNNING) | ||||
iflib_init_locked(ctx); | iflib_init_locked(ctx); | ||||
if_setdrvflags(ifp, bits); | if_setdrvflags(ifp, bits); | ||||
CTX_UNLOCK(ctx); | CTX_UNLOCK(ctx); | ||||
} | } | ||||
break; | break; | ||||
} | } | ||||
case SIOCGPRIVATE_0: | case SIOCGPRIVATE_0: | ||||
case SIOCSDRVSPEC: | case SIOCSDRVSPEC: | ||||
Show All 35 Lines | iflib_vlan_register(void *arg, if_t ifp, uint16_t vtag) | ||||
if ((vtag == 0) || (vtag > 4095)) | if ((vtag == 0) || (vtag > 4095)) | ||||
return; | return; | ||||
CTX_LOCK(ctx); | CTX_LOCK(ctx); | ||||
IFDI_VLAN_REGISTER(ctx, vtag); | IFDI_VLAN_REGISTER(ctx, vtag); | ||||
/* Re-init to load the changes */ | /* Re-init to load the changes */ | ||||
if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) | if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) | ||||
iflib_init_locked(ctx); | iflib_if_init_locked(ctx); | ||||
CTX_UNLOCK(ctx); | CTX_UNLOCK(ctx); | ||||
} | } | ||||
static void | static void | ||||
iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) | iflib_vlan_unregister(void *arg, if_t ifp, uint16_t vtag) | ||||
{ | { | ||||
if_ctx_t ctx = if_getsoftc(ifp); | if_ctx_t ctx = if_getsoftc(ifp); | ||||
if ((void *)ctx != arg) | if ((void *)ctx != arg) | ||||
return; | return; | ||||
if ((vtag == 0) || (vtag > 4095)) | if ((vtag == 0) || (vtag > 4095)) | ||||
return; | return; | ||||
CTX_LOCK(ctx); | CTX_LOCK(ctx); | ||||
IFDI_VLAN_UNREGISTER(ctx, vtag); | IFDI_VLAN_UNREGISTER(ctx, vtag); | ||||
/* Re-init to load the changes */ | /* Re-init to load the changes */ | ||||
if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) | if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) | ||||
iflib_init_locked(ctx); | iflib_if_init_locked(ctx); | ||||
CTX_UNLOCK(ctx); | CTX_UNLOCK(ctx); | ||||
} | } | ||||
static void | static void | ||||
iflib_led_func(void *arg, int onoff) | iflib_led_func(void *arg, int onoff) | ||||
{ | { | ||||
if_ctx_t ctx = arg; | if_ctx_t ctx = arg; | ||||
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines | iflib_device_register(device_t dev, void *sc, if_shared_ctx_t sctx, if_ctx_t *ctxp) | ||||
if (sc == NULL) { | if (sc == NULL) { | ||||
sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); | sc = malloc(sctx->isc_driver->size, M_IFLIB, M_WAITOK|M_ZERO); | ||||
device_set_softc(dev, ctx); | device_set_softc(dev, ctx); | ||||
ctx->ifc_flags |= IFC_SC_ALLOCATED; | ctx->ifc_flags |= IFC_SC_ALLOCATED; | ||||
} | } | ||||
ctx->ifc_sctx = sctx; | ctx->ifc_sctx = sctx; | ||||
ctx->ifc_dev = dev; | ctx->ifc_dev = dev; | ||||
ctx->ifc_txrx = *sctx->isc_txrx; | |||||
ctx->ifc_softc = sc; | ctx->ifc_softc = sc; | ||||
if ((err = iflib_register(ctx)) != 0) { | if ((err = iflib_register(ctx)) != 0) { | ||||
device_printf(dev, "iflib_register failed %d\n", err); | device_printf(dev, "iflib_register failed %d\n", err); | ||||
return (err); | return (err); | ||||
} | } | ||||
iflib_add_device_sysctl_pre(ctx); | iflib_add_device_sysctl_pre(ctx); | ||||
scctx = &ctx->ifc_softc_ctx; | scctx = &ctx->ifc_softc_ctx; | ||||
ifp = ctx->ifc_ifp; | |||||
ctx->ifc_nhwtxqs = sctx->isc_ntxqs; | |||||
/* | /* | ||||
* XXX sanity check that ntxd & nrxd are a power of 2 | * XXX sanity check that ntxd & nrxd are a power of 2 | ||||
*/ | */ | ||||
if (ctx->ifc_sysctl_ntxqs != 0) | if (ctx->ifc_sysctl_ntxqs != 0) | ||||
scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; | scctx->isc_ntxqsets = ctx->ifc_sysctl_ntxqs; | ||||
if (ctx->ifc_sysctl_nrxqs != 0) | if (ctx->ifc_sysctl_nrxqs != 0) | ||||
scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; | scctx->isc_nrxqsets = ctx->ifc_sysctl_nrxqs; | ||||
Show All 36 Lines | if (scctx->isc_ntxd[i] > sctx->isc_ntxd_max[i]) { | ||||
scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; | scctx->isc_ntxd[i] = sctx->isc_ntxd_max[i]; | ||||
} | } | ||||
} | } | ||||
if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { | if ((err = IFDI_ATTACH_PRE(ctx)) != 0) { | ||||
device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); | device_printf(dev, "IFDI_ATTACH_PRE failed %d\n", err); | ||||
return (err); | return (err); | ||||
} | } | ||||
if (scctx->isc_ntxqsets_max) | _iflib_pre_assert(scctx); | ||||
scctx->isc_ntxqsets = min(scctx->isc_ntxqsets, scctx->isc_ntxqsets_max); | ctx->ifc_txrx = *scctx->isc_txrx; | ||||
if (scctx->isc_nrxqsets_max) | |||||
scctx->isc_nrxqsets = min(scctx->isc_nrxqsets, scctx->isc_nrxqsets_max); | |||||
#ifdef INVARIANTS | |||||
MPASS(scctx->isc_capenable); | |||||
if (scctx->isc_capenable & IFCAP_TXCSUM) | |||||
MPASS(scctx->isc_tx_csum_flags); | |||||
#endif | |||||
if_setcapabilities(ifp, scctx->isc_capenable | IFCAP_HWSTATS); | |||||
if_setcapenable(ifp, scctx->isc_capenable | IFCAP_HWSTATS); | |||||
if (scctx->isc_ntxqsets == 0 || (scctx->isc_ntxqsets_max && scctx->isc_ntxqsets_max < scctx->isc_ntxqsets)) | |||||
scctx->isc_ntxqsets = scctx->isc_ntxqsets_max; | |||||
if (scctx->isc_nrxqsets == 0 || (scctx->isc_nrxqsets_max && scctx->isc_nrxqsets_max < scctx->isc_nrxqsets)) | |||||
scctx->isc_nrxqsets = scctx->isc_nrxqsets_max; | |||||
#ifdef ACPI_DMAR | #ifdef ACPI_DMAR | ||||
if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) | if (dmar_get_dma_tag(device_get_parent(dev), dev) != NULL) | ||||
ctx->ifc_flags |= IFC_DMAR; | ctx->ifc_flags |= IFC_DMAR; | ||||
#elif !(defined(__i386__) || defined(__amd64__)) | |||||
/* set unconditionally for !x86 */ | |||||
ctx->ifc_flags |= IFC_DMAR; | |||||
#endif | #endif | ||||
msix_bar = scctx->isc_msix_bar; | msix_bar = scctx->isc_msix_bar; | ||||
main_txq = (sctx->isc_flags & IFLIB_HAS_TXCQ) ? 1 : 0; | |||||
main_rxq = (sctx->isc_flags & IFLIB_HAS_RXCQ) ? 1 : 0; | |||||
ifp = ctx->ifc_ifp; | |||||
if(sctx->isc_flags & IFLIB_HAS_TXCQ) | |||||
main_txq = 1; | |||||
else | |||||
main_txq = 0; | |||||
if(sctx->isc_flags & IFLIB_HAS_RXCQ) | |||||
main_rxq = 1; | |||||
else | |||||
main_rxq = 0; | |||||
/* XXX change for per-queue sizes */ | /* XXX change for per-queue sizes */ | ||||
device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", | device_printf(dev, "using %d tx descriptors and %d rx descriptors\n", | ||||
scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); | scctx->isc_ntxd[main_txq], scctx->isc_nrxd[main_rxq]); | ||||
for (i = 0; i < sctx->isc_nrxqs; i++) { | for (i = 0; i < sctx->isc_nrxqs; i++) { | ||||
if (!powerof2(scctx->isc_nrxd[i])) { | if (!powerof2(scctx->isc_nrxd[i])) { | ||||
/* round down instead? */ | /* round down instead? */ | ||||
device_printf(dev, "# rx descriptors must be a power of 2\n"); | device_printf(dev, "# rx descriptors must be a power of 2\n"); | ||||
err = EINVAL; | err = EINVAL; | ||||
Show All 26 Lines | #endif | ||||
/* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ | /* TSO parameters - dig these out of the data sheet - simply correspond to tag setup */ | ||||
ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; | ifp->if_hw_tsomaxsegcount = scctx->isc_tx_tso_segments_max; | ||||
ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; | ifp->if_hw_tsomax = scctx->isc_tx_tso_size_max; | ||||
ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; | ifp->if_hw_tsomaxsegsize = scctx->isc_tx_tso_segsize_max; | ||||
if (scctx->isc_rss_table_size == 0) | if (scctx->isc_rss_table_size == 0) | ||||
scctx->isc_rss_table_size = 64; | scctx->isc_rss_table_size = 64; | ||||
scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; | scctx->isc_rss_table_mask = scctx->isc_rss_table_size-1; | ||||
GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); | |||||
/* XXX format name */ | |||||
taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin"); | |||||
/* Set up cpu set. If it fails, use the set of all CPUs. */ | |||||
if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) != 0) { | |||||
device_printf(dev, "Unable to fetch CPU list\n"); | |||||
CPU_COPY(&all_cpus, &ctx->ifc_cpus); | |||||
} | |||||
MPASS(CPU_COUNT(&ctx->ifc_cpus) > 0); | |||||
/* | /* | ||||
** Now setup MSI or MSI/X, should | ** Now setup MSI or MSI/X, should | ||||
** return us the number of supported | ** return us the number of supported | ||||
** vectors. (Will be 1 for MSI) | ** vectors. (Will be 1 for MSI) | ||||
*/ | */ | ||||
if (sctx->isc_flags & IFLIB_SKIP_MSIX) { | if (sctx->isc_flags & IFLIB_SKIP_MSIX) { | ||||
msix = scctx->isc_vectors; | msix = scctx->isc_vectors; | ||||
} else if (scctx->isc_msix_bar != 0) | } else if (scctx->isc_msix_bar != 0) | ||||
/* | |||||
* The simple fact that isc_msix_bar is not 0 does not mean we | |||||
* we have a good value there that is known to work. | |||||
*/ | |||||
msix = iflib_msix_init(ctx); | msix = iflib_msix_init(ctx); | ||||
else { | else { | ||||
scctx->isc_vectors = 1; | scctx->isc_vectors = 1; | ||||
scctx->isc_ntxqsets = 1; | scctx->isc_ntxqsets = 1; | ||||
scctx->isc_nrxqsets = 1; | scctx->isc_nrxqsets = 1; | ||||
scctx->isc_intr = IFLIB_INTR_LEGACY; | scctx->isc_intr = IFLIB_INTR_LEGACY; | ||||
msix = 0; | msix = 0; | ||||
} | } | ||||
/* Get memory for the station queues */ | /* Get memory for the station queues */ | ||||
if ((err = iflib_queues_alloc(ctx))) { | if ((err = iflib_queues_alloc(ctx))) { | ||||
device_printf(dev, "Unable to allocate queue memory\n"); | device_printf(dev, "Unable to allocate queue memory\n"); | ||||
goto fail; | goto fail; | ||||
} | } | ||||
if ((err = iflib_qset_structures_setup(ctx))) { | if ((err = iflib_qset_structures_setup(ctx))) { | ||||
device_printf(dev, "qset structure setup failed %d\n", err); | device_printf(dev, "qset structure setup failed %d\n", err); | ||||
goto fail_queues; | goto fail_queues; | ||||
} | } | ||||
/* | |||||
* Group taskqueues aren't properly set up until SMP is started, | |||||
* so we disable interrupts until we can handle them post | |||||
* SI_SUB_SMP. | |||||
* | |||||
* XXX: disabling interrupts doesn't actually work, at least for | |||||
* the non-MSI case. When they occur before SI_SUB_SMP completes, | |||||
* we do null handling and depend on this not causing too large an | |||||
* interrupt storm. | |||||
*/ | |||||
IFDI_INTR_DISABLE(ctx); | |||||
if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { | if (msix > 1 && (err = IFDI_MSIX_INTR_ASSIGN(ctx, msix)) != 0) { | ||||
device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); | device_printf(dev, "IFDI_MSIX_INTR_ASSIGN failed %d\n", err); | ||||
goto fail_intr_free; | goto fail_intr_free; | ||||
} | } | ||||
if (msix <= 1) { | if (msix <= 1) { | ||||
rid = 0; | rid = 0; | ||||
if (scctx->isc_intr == IFLIB_INTR_MSI) { | if (scctx->isc_intr == IFLIB_INTR_MSI) { | ||||
MPASS(msix == 1); | MPASS(msix == 1); | ||||
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines | |||||
int | int | ||||
iflib_device_deregister(if_ctx_t ctx) | iflib_device_deregister(if_ctx_t ctx) | ||||
{ | { | ||||
if_t ifp = ctx->ifc_ifp; | if_t ifp = ctx->ifc_ifp; | ||||
iflib_txq_t txq; | iflib_txq_t txq; | ||||
iflib_rxq_t rxq; | iflib_rxq_t rxq; | ||||
device_t dev = ctx->ifc_dev; | device_t dev = ctx->ifc_dev; | ||||
int i; | int i, j; | ||||
struct taskqgroup *tqg; | struct taskqgroup *tqg; | ||||
iflib_fl_t fl; | |||||
/* Make sure VLANS are not using driver */ | /* Make sure VLANS are not using driver */ | ||||
if (if_vlantrunkinuse(ifp)) { | if (if_vlantrunkinuse(ifp)) { | ||||
device_printf(dev,"Vlan in use, detach first\n"); | device_printf(dev,"Vlan in use, detach first\n"); | ||||
return (EBUSY); | return (EBUSY); | ||||
} | } | ||||
CTX_LOCK(ctx); | CTX_LOCK(ctx); | ||||
Show All 9 Lines | iflib_device_deregister(if_ctx_t ctx) | ||||
iflib_netmap_detach(ifp); | iflib_netmap_detach(ifp); | ||||
ether_ifdetach(ifp); | ether_ifdetach(ifp); | ||||
/* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ | /* ether_ifdetach calls if_qflush - lock must be destroy afterwards*/ | ||||
CTX_LOCK_DESTROY(ctx); | CTX_LOCK_DESTROY(ctx); | ||||
if (ctx->ifc_led_dev != NULL) | if (ctx->ifc_led_dev != NULL) | ||||
led_destroy(ctx->ifc_led_dev); | led_destroy(ctx->ifc_led_dev); | ||||
/* XXX drain any dependent tasks */ | /* XXX drain any dependent tasks */ | ||||
tqg = qgroup_softirq; | tqg = qgroup_if_io_tqg; | ||||
for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { | for (txq = ctx->ifc_txqs, i = 0; i < NTXQSETS(ctx); i++, txq++) { | ||||
callout_drain(&txq->ift_timer); | callout_drain(&txq->ift_timer); | ||||
callout_drain(&txq->ift_db_check); | |||||
if (txq->ift_task.gt_uniq != NULL) | if (txq->ift_task.gt_uniq != NULL) | ||||
taskqgroup_detach(tqg, &txq->ift_task); | taskqgroup_detach(tqg, &txq->ift_task); | ||||
} | } | ||||
for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { | for (i = 0, rxq = ctx->ifc_rxqs; i < NRXQSETS(ctx); i++, rxq++) { | ||||
if (rxq->ifr_task.gt_uniq != NULL) | if (rxq->ifr_task.gt_uniq != NULL) | ||||
taskqgroup_detach(tqg, &rxq->ifr_task); | taskqgroup_detach(tqg, &rxq->ifr_task); | ||||
for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) | |||||
free(fl->ifl_rx_bitmap, M_IFLIB); | |||||
} | } | ||||
tqg = qgroup_if_config_tqg; | tqg = qgroup_if_config_tqg; | ||||
if (ctx->ifc_admin_task.gt_uniq != NULL) | if (ctx->ifc_admin_task.gt_uniq != NULL) | ||||
taskqgroup_detach(tqg, &ctx->ifc_admin_task); | taskqgroup_detach(tqg, &ctx->ifc_admin_task); | ||||
if (ctx->ifc_vflr_task.gt_uniq != NULL) | if (ctx->ifc_vflr_task.gt_uniq != NULL) | ||||
taskqgroup_detach(tqg, &ctx->ifc_vflr_task); | taskqgroup_detach(tqg, &ctx->ifc_vflr_task); | ||||
IFDI_DETACH(ctx); | IFDI_DETACH(ctx); | ||||
▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Lines | |||||
{ | { | ||||
MPASS(sctx->isc_tx_maxsize); | MPASS(sctx->isc_tx_maxsize); | ||||
MPASS(sctx->isc_tx_maxsegsize); | MPASS(sctx->isc_tx_maxsegsize); | ||||
MPASS(sctx->isc_rx_maxsize); | MPASS(sctx->isc_rx_maxsize); | ||||
MPASS(sctx->isc_rx_nsegments); | MPASS(sctx->isc_rx_nsegments); | ||||
MPASS(sctx->isc_rx_maxsegsize); | MPASS(sctx->isc_rx_maxsegsize); | ||||
MPASS(sctx->isc_txrx->ift_txd_encap); | |||||
MPASS(sctx->isc_txrx->ift_txd_flush); | |||||
MPASS(sctx->isc_txrx->ift_txd_credits_update); | |||||
MPASS(sctx->isc_txrx->ift_rxd_available); | |||||
MPASS(sctx->isc_txrx->ift_rxd_pkt_get); | |||||
MPASS(sctx->isc_txrx->ift_rxd_refill); | |||||
MPASS(sctx->isc_txrx->ift_rxd_flush); | |||||
MPASS(sctx->isc_nrxd_min[0]); | MPASS(sctx->isc_nrxd_min[0]); | ||||
MPASS(sctx->isc_nrxd_max[0]); | MPASS(sctx->isc_nrxd_max[0]); | ||||
MPASS(sctx->isc_nrxd_default[0]); | MPASS(sctx->isc_nrxd_default[0]); | ||||
MPASS(sctx->isc_ntxd_min[0]); | MPASS(sctx->isc_ntxd_min[0]); | ||||
MPASS(sctx->isc_ntxd_max[0]); | MPASS(sctx->isc_ntxd_max[0]); | ||||
MPASS(sctx->isc_ntxd_default[0]); | MPASS(sctx->isc_ntxd_default[0]); | ||||
} | } | ||||
static void | |||||
_iflib_pre_assert(if_softc_ctx_t scctx) | |||||
{ | |||||
MPASS(scctx->isc_txrx->ift_txd_encap); | |||||
MPASS(scctx->isc_txrx->ift_txd_flush); | |||||
MPASS(scctx->isc_txrx->ift_txd_credits_update); | |||||
MPASS(scctx->isc_txrx->ift_rxd_available); | |||||
MPASS(scctx->isc_txrx->ift_rxd_pkt_get); | |||||
MPASS(scctx->isc_txrx->ift_rxd_refill); | |||||
MPASS(scctx->isc_txrx->ift_rxd_flush); | |||||
} | |||||
static int | static int | ||||
iflib_register(if_ctx_t ctx) | iflib_register(if_ctx_t ctx) | ||||
{ | { | ||||
if_shared_ctx_t sctx = ctx->ifc_sctx; | if_shared_ctx_t sctx = ctx->ifc_sctx; | ||||
driver_t *driver = sctx->isc_driver; | driver_t *driver = sctx->isc_driver; | ||||
device_t dev = ctx->ifc_dev; | device_t dev = ctx->ifc_dev; | ||||
if_t ifp; | if_t ifp; | ||||
Show All 18 Lines | iflib_register(if_ctx_t ctx) | ||||
if_setsoftc(ifp, ctx); | if_setsoftc(ifp, ctx); | ||||
if_setdev(ifp, dev); | if_setdev(ifp, dev); | ||||
if_setinitfn(ifp, iflib_if_init); | if_setinitfn(ifp, iflib_if_init); | ||||
if_setioctlfn(ifp, iflib_if_ioctl); | if_setioctlfn(ifp, iflib_if_ioctl); | ||||
if_settransmitfn(ifp, iflib_if_transmit); | if_settransmitfn(ifp, iflib_if_transmit); | ||||
if_setqflushfn(ifp, iflib_if_qflush); | if_setqflushfn(ifp, iflib_if_qflush); | ||||
if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); | if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); | ||||
if_setcapabilities(ifp, 0); | |||||
if_setcapenable(ifp, 0); | |||||
ctx->ifc_vlan_attach_event = | ctx->ifc_vlan_attach_event = | ||||
EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, | EVENTHANDLER_REGISTER(vlan_config, iflib_vlan_register, ctx, | ||||
EVENTHANDLER_PRI_FIRST); | EVENTHANDLER_PRI_FIRST); | ||||
ctx->ifc_vlan_detach_event = | ctx->ifc_vlan_detach_event = | ||||
EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, | EVENTHANDLER_REGISTER(vlan_unconfig, iflib_vlan_unregister, ctx, | ||||
EVENTHANDLER_PRI_FIRST); | EVENTHANDLER_PRI_FIRST); | ||||
ifmedia_init(&ctx->ifc_media, IFM_IMASK, | ifmedia_init(&ctx->ifc_media, IFM_IMASK, | ||||
Show All 19 Lines | iflib_queues_alloc(if_ctx_t ctx) | ||||
uint32_t *rxqsizes = scctx->isc_rxqsizes; | uint32_t *rxqsizes = scctx->isc_rxqsizes; | ||||
uint32_t *txqsizes = scctx->isc_txqsizes; | uint32_t *txqsizes = scctx->isc_txqsizes; | ||||
uint8_t nrxqs = sctx->isc_nrxqs; | uint8_t nrxqs = sctx->isc_nrxqs; | ||||
uint8_t ntxqs = sctx->isc_ntxqs; | uint8_t ntxqs = sctx->isc_ntxqs; | ||||
int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; | int nfree_lists = sctx->isc_nfl ? sctx->isc_nfl : 1; | ||||
caddr_t *vaddrs; | caddr_t *vaddrs; | ||||
uint64_t *paddrs; | uint64_t *paddrs; | ||||
struct ifmp_ring **brscp; | struct ifmp_ring **brscp; | ||||
int nbuf_rings = 1; /* XXX determine dynamically */ | |||||
KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); | KASSERT(ntxqs > 0, ("number of queues per qset must be at least 1")); | ||||
KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); | KASSERT(nrxqs > 0, ("number of queues per qset must be at least 1")); | ||||
brscp = NULL; | brscp = NULL; | ||||
txq = NULL; | txq = NULL; | ||||
rxq = NULL; | rxq = NULL; | ||||
Show All 9 Lines | /* Allocate the TX ring struct memory */ | ||||
/* Now allocate the RX */ | /* Now allocate the RX */ | ||||
if (!(rxq = | if (!(rxq = | ||||
(iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * | (iflib_rxq_t) malloc(sizeof(struct iflib_rxq) * | ||||
nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { | nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { | ||||
device_printf(dev, "Unable to allocate RX ring memory\n"); | device_printf(dev, "Unable to allocate RX ring memory\n"); | ||||
err = ENOMEM; | err = ENOMEM; | ||||
goto rx_fail; | goto rx_fail; | ||||
} | } | ||||
if (!(brscp = malloc(sizeof(void *) * nbuf_rings * nrxqsets, M_IFLIB, M_NOWAIT | M_ZERO))) { | |||||
device_printf(dev, "Unable to buf_ring_sc * memory\n"); | |||||
err = ENOMEM; | |||||
goto rx_fail; | |||||
} | |||||
ctx->ifc_txqs = txq; | ctx->ifc_txqs = txq; | ||||
ctx->ifc_rxqs = rxq; | ctx->ifc_rxqs = rxq; | ||||
/* | /* | ||||
* XXX handle allocation failure | * XXX handle allocation failure | ||||
*/ | */ | ||||
for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { | for (txconf = i = 0, cpu = CPU_FIRST(); i < ntxqsets; i++, txconf++, txq++, cpu = CPU_NEXT(cpu)) { | ||||
/* Set up some basics */ | /* Set up some basics */ | ||||
if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { | if ((ifdip = malloc(sizeof(struct iflib_dma_info) * ntxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { | ||||
device_printf(dev, "failed to allocate iflib_dma_info\n"); | device_printf(dev, "failed to allocate iflib_dma_info\n"); | ||||
err = ENOMEM; | err = ENOMEM; | ||||
goto err_tx_desc; | goto err_tx_desc; | ||||
} | } | ||||
txq->ift_ifdi = ifdip; | txq->ift_ifdi = ifdip; | ||||
for (j = 0; j < ntxqs; j++, ifdip++) { | for (j = 0; j < ntxqs; j++, ifdip++) { | ||||
if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { | if (iflib_dma_alloc(ctx, txqsizes[j], ifdip, BUS_DMA_NOWAIT)) { | ||||
device_printf(dev, "Unable to allocate Descriptor memory\n"); | device_printf(dev, "Unable to allocate Descriptor memory\n"); | ||||
err = ENOMEM; | err = ENOMEM; | ||||
goto err_tx_desc; | goto err_tx_desc; | ||||
} | } | ||||
txq->ift_txd_size[j] = scctx->isc_txd_size[j]; | |||||
bzero((void *)ifdip->idi_vaddr, txqsizes[j]); | bzero((void *)ifdip->idi_vaddr, txqsizes[j]); | ||||
} | } | ||||
txq->ift_ctx = ctx; | txq->ift_ctx = ctx; | ||||
txq->ift_id = i; | txq->ift_id = i; | ||||
if (sctx->isc_flags & IFLIB_HAS_TXCQ) { | if (sctx->isc_flags & IFLIB_HAS_TXCQ) { | ||||
txq->ift_br_offset = 1; | txq->ift_br_offset = 1; | ||||
} else { | } else { | ||||
txq->ift_br_offset = 0; | txq->ift_br_offset = 0; | ||||
} | } | ||||
/* XXX fix this */ | /* XXX fix this */ | ||||
txq->ift_timer.c_cpu = cpu; | txq->ift_timer.c_cpu = cpu; | ||||
txq->ift_db_check.c_cpu = cpu; | |||||
txq->ift_nbr = nbuf_rings; | |||||
if (iflib_txsd_alloc(txq)) { | if (iflib_txsd_alloc(txq)) { | ||||
device_printf(dev, "Critical Failure setting up TX buffers\n"); | device_printf(dev, "Critical Failure setting up TX buffers\n"); | ||||
err = ENOMEM; | err = ENOMEM; | ||||
goto err_tx_desc; | goto err_tx_desc; | ||||
} | } | ||||
/* Initialize the TX lock */ | /* Initialize the TX lock */ | ||||
snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", | snprintf(txq->ift_mtx_name, MTX_NAME_LEN, "%s:tx(%d):callout", | ||||
device_get_nameunit(dev), txq->ift_id); | device_get_nameunit(dev), txq->ift_id); | ||||
mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); | mtx_init(&txq->ift_mtx, txq->ift_mtx_name, NULL, MTX_DEF); | ||||
callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); | callout_init_mtx(&txq->ift_timer, &txq->ift_mtx, 0); | ||||
callout_init_mtx(&txq->ift_db_check, &txq->ift_mtx, 0); | |||||
snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", | snprintf(txq->ift_db_mtx_name, MTX_NAME_LEN, "%s:tx(%d):db", | ||||
device_get_nameunit(dev), txq->ift_id); | device_get_nameunit(dev), txq->ift_id); | ||||
TXDB_LOCK_INIT(txq); | |||||
txq->ift_br = brscp + i*nbuf_rings; | err = ifmp_ring_alloc(&txq->ift_br, 2048, txq, iflib_txq_drain, | ||||
for (j = 0; j < nbuf_rings; j++) { | |||||
err = ifmp_ring_alloc(&txq->ift_br[j], 2048, txq, iflib_txq_drain, | |||||
iflib_txq_can_drain, M_IFLIB, M_WAITOK); | iflib_txq_can_drain, M_IFLIB, M_WAITOK); | ||||
if (err) { | if (err) { | ||||
/* XXX free any allocated rings */ | /* XXX free any allocated rings */ | ||||
device_printf(dev, "Unable to allocate buf_ring\n"); | device_printf(dev, "Unable to allocate buf_ring\n"); | ||||
goto err_tx_desc; | goto err_tx_desc; | ||||
} | } | ||||
} | } | ||||
} | |||||
for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { | for (rxconf = i = 0; i < nrxqsets; i++, rxconf++, rxq++) { | ||||
/* Set up some basics */ | /* Set up some basics */ | ||||
if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { | if ((ifdip = malloc(sizeof(struct iflib_dma_info) * nrxqs, M_IFLIB, M_WAITOK|M_ZERO)) == NULL) { | ||||
device_printf(dev, "failed to allocate iflib_dma_info\n"); | device_printf(dev, "failed to allocate iflib_dma_info\n"); | ||||
err = ENOMEM; | err = ENOMEM; | ||||
goto err_tx_desc; | goto err_tx_desc; | ||||
} | } | ||||
rxq->ifr_ifdi = ifdip; | rxq->ifr_ifdi = ifdip; | ||||
/* XXX this needs to be changed if #rx queues != #tx queues */ | |||||
rxq->ifr_ntxqirq = 1; | |||||
rxq->ifr_txqid[0] = i; | |||||
for (j = 0; j < nrxqs; j++, ifdip++) { | for (j = 0; j < nrxqs; j++, ifdip++) { | ||||
if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { | if (iflib_dma_alloc(ctx, rxqsizes[j], ifdip, BUS_DMA_NOWAIT)) { | ||||
device_printf(dev, "Unable to allocate Descriptor memory\n"); | device_printf(dev, "Unable to allocate Descriptor memory\n"); | ||||
err = ENOMEM; | err = ENOMEM; | ||||
goto err_tx_desc; | goto err_tx_desc; | ||||
} | } | ||||
bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); | bzero((void *)ifdip->idi_vaddr, rxqsizes[j]); | ||||
} | } | ||||
rxq->ifr_ctx = ctx; | rxq->ifr_ctx = ctx; | ||||
rxq->ifr_id = i; | rxq->ifr_id = i; | ||||
if (sctx->isc_flags & IFLIB_HAS_RXCQ) { | if (sctx->isc_flags & IFLIB_HAS_RXCQ) { | ||||
rxq->ifr_fl_offset = 1; | rxq->ifr_fl_offset = 1; | ||||
} else { | } else { | ||||
rxq->ifr_fl_offset = 0; | rxq->ifr_fl_offset = 0; | ||||
} | } | ||||
rxq->ifr_nfl = nfree_lists; | rxq->ifr_nfl = nfree_lists; | ||||
if (!(fl = | if (!(fl = | ||||
(iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { | (iflib_fl_t) malloc(sizeof(struct iflib_fl) * nfree_lists, M_IFLIB, M_NOWAIT | M_ZERO))) { | ||||
device_printf(dev, "Unable to allocate free list memory\n"); | device_printf(dev, "Unable to allocate free list memory\n"); | ||||
err = ENOMEM; | err = ENOMEM; | ||||
goto err_tx_desc; | goto err_tx_desc; | ||||
} | } | ||||
rxq->ifr_fl = fl; | rxq->ifr_fl = fl; | ||||
for (j = 0; j < nfree_lists; j++) { | for (j = 0; j < nfree_lists; j++) { | ||||
rxq->ifr_fl[j].ifl_rxq = rxq; | fl[j].ifl_rxq = rxq; | ||||
rxq->ifr_fl[j].ifl_id = j; | fl[j].ifl_id = j; | ||||
rxq->ifr_fl[j].ifl_ifdi = | fl[j].ifl_ifdi = &rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; | ||||
&rxq->ifr_ifdi[j + rxq->ifr_fl_offset]; | fl[j].ifl_rxd_size = scctx->isc_rxd_size[j]; | ||||
} | } | ||||
/* Allocate receive buffers for the ring*/ | /* Allocate receive buffers for the ring*/ | ||||
if (iflib_rxsd_alloc(rxq)) { | if (iflib_rxsd_alloc(rxq)) { | ||||
device_printf(dev, | device_printf(dev, | ||||
"Critical Failure setting up receive buffers\n"); | "Critical Failure setting up receive buffers\n"); | ||||
err = ENOMEM; | err = ENOMEM; | ||||
goto err_rx_desc; | goto err_rx_desc; | ||||
} | } | ||||
for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) | |||||
fl->ifl_rx_bitmap = bit_alloc(fl->ifl_size, M_IFLIB, M_WAITOK|M_ZERO); | |||||
} | } | ||||
/* TXQs */ | /* TXQs */ | ||||
vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); | vaddrs = malloc(sizeof(caddr_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); | ||||
paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); | paddrs = malloc(sizeof(uint64_t)*ntxqsets*ntxqs, M_IFLIB, M_WAITOK); | ||||
for (i = 0; i < ntxqsets; i++) { | for (i = 0; i < ntxqsets; i++) { | ||||
iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; | iflib_dma_info_t di = ctx->ifc_txqs[i].ift_ifdi; | ||||
▲ Show 20 Lines • Show All 161 Lines • ▼ Show 20 Lines | |||||
int | int | ||||
iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, | iflib_irq_alloc(if_ctx_t ctx, if_irq_t irq, int rid, | ||||
driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) | driver_filter_t filter, void *filter_arg, driver_intr_t handler, void *arg, char *name) | ||||
{ | { | ||||
return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); | return (_iflib_irq_alloc(ctx, irq, rid, filter, handler, arg, name)); | ||||
} | } | ||||
static void | #ifdef SMP | ||||
find_nth(if_ctx_t ctx, cpuset_t *cpus, int qid) | static int | ||||
find_nth(if_ctx_t ctx, int qid) | |||||
{ | { | ||||
int i, cpuid; | cpuset_t cpus; | ||||
int i, cpuid, eqid, count; | |||||
CPU_COPY(&ctx->ifc_cpus, cpus); | CPU_COPY(&ctx->ifc_cpus, &cpus); | ||||
count = CPU_COUNT(&cpus); | |||||
eqid = qid % count; | |||||
/* clear up to the qid'th bit */ | /* clear up to the qid'th bit */ | ||||
for (i = 0; i < qid; i++) { | for (i = 0; i < eqid; i++) { | ||||
cpuid = CPU_FFS(cpus); | cpuid = CPU_FFS(&cpus); | ||||
CPU_CLR(cpuid, cpus); | MPASS(cpuid != 0); | ||||
CPU_CLR(cpuid-1, &cpus); | |||||
} | } | ||||
cpuid = CPU_FFS(&cpus); | |||||
MPASS(cpuid != 0); | |||||
return (cpuid-1); | |||||
} | } | ||||
#ifdef SCHED_ULE | |||||
extern struct cpu_group *cpu_top; /* CPU topology */ | |||||
static int | |||||
find_child_with_core(int cpu, struct cpu_group *grp) | |||||
{ | |||||
int i; | |||||
if (grp->cg_children == 0) | |||||
return -1; | |||||
MPASS(grp->cg_child); | |||||
for (i = 0; i < grp->cg_children; i++) { | |||||
if (CPU_ISSET(cpu, &grp->cg_child[i].cg_mask)) | |||||
return i; | |||||
} | |||||
return -1; | |||||
} | |||||
/* | |||||
* Find the nth "close" core to the specified core | |||||
* "close" is defined as the deepest level that shares | |||||
* at least an L2 cache. With threads, this will be | |||||
* threads on the same core. If the sahred cache is L3 | |||||
* or higher, simply returns the same core. | |||||
*/ | |||||
static int | |||||
find_close_core(int cpu, int core_offset) | |||||
{ | |||||
struct cpu_group *grp; | |||||
int i; | |||||
int fcpu; | |||||
cpuset_t cs; | |||||
grp = cpu_top; | |||||
if (grp == NULL) | |||||
return cpu; | |||||
i = 0; | |||||
while ((i = find_child_with_core(cpu, grp)) != -1) { | |||||
/* If the child only has one cpu, don't descend */ | |||||
if (grp->cg_child[i].cg_count <= 1) | |||||
break; | |||||
grp = &grp->cg_child[i]; | |||||
} | |||||
/* If they don't share at least an L2 cache, use the same CPU */ | |||||
if (grp->cg_level > CG_SHARE_L2 || grp->cg_level == CG_SHARE_NONE) | |||||
return cpu; | |||||
/* Now pick one */ | |||||
CPU_COPY(&grp->cg_mask, &cs); | |||||
/* Add the selected CPU offset to core offset. */ | |||||
for (i = 0; (fcpu = CPU_FFS(&cs)) != 0; i++) { | |||||
if (fcpu - 1 == cpu) | |||||
break; | |||||
CPU_CLR(fcpu - 1, &cs); | |||||
} | |||||
MPASS(fcpu); | |||||
core_offset += i; | |||||
CPU_COPY(&grp->cg_mask, &cs); | |||||
for (i = core_offset % grp->cg_count; i > 0; i--) { | |||||
MPASS(CPU_FFS(&cs)); | |||||
CPU_CLR(CPU_FFS(&cs) - 1, &cs); | |||||
} | |||||
MPASS(CPU_FFS(&cs)); | |||||
return CPU_FFS(&cs) - 1; | |||||
} | |||||
#else | |||||
static int | |||||
find_close_core(int cpu, int core_offset __unused) | |||||
{ | |||||
return cpu; | |||||
} | |||||
#endif | |||||
static int | |||||
get_core_offset(if_ctx_t ctx, iflib_intr_type_t type, int qid) | |||||
{ | |||||
switch (type) { | |||||
case IFLIB_INTR_TX: | |||||
/* TX queues get cores which share at least an L2 cache with the corresponding RX queue */ | |||||
/* XXX handle multiple RX threads per core and more than two core per L2 group */ | |||||
return qid / CPU_COUNT(&ctx->ifc_cpus) + 1; | |||||
case IFLIB_INTR_RX: | |||||
case IFLIB_INTR_RXTX: | |||||
/* RX queues get the specified core */ | |||||
return qid / CPU_COUNT(&ctx->ifc_cpus); | |||||
default: | |||||
return -1; | |||||
} | |||||
} | |||||
#else | |||||
#define get_core_offset(ctx, type, qid) CPU_FIRST() | |||||
#define find_close_core(cpuid, tid) CPU_FIRST() | |||||
#define find_nth(ctx, gid) CPU_FIRST() | |||||
#endif | |||||
/* Just to avoid copy/paste */ | |||||
static inline int | |||||
iflib_irq_set_affinity(if_ctx_t ctx, int irq, iflib_intr_type_t type, int qid, | |||||
struct grouptask *gtask, struct taskqgroup *tqg, void *uniq, char *name) | |||||
{ | |||||
int cpuid; | |||||
int err, tid; | |||||
cpuid = find_nth(ctx, qid); | |||||
tid = get_core_offset(ctx, type, qid); | |||||
MPASS(tid >= 0); | |||||
cpuid = find_close_core(cpuid, tid); | |||||
err = taskqgroup_attach_cpu(tqg, gtask, uniq, cpuid, irq, name); | |||||
if (err) { | |||||
device_printf(ctx->ifc_dev, "taskqgroup_attach_cpu failed %d\n", err); | |||||
return (err); | |||||
} | |||||
#ifdef notyet | |||||
if (cpuid > ctx->ifc_cpuid_highest) | |||||
ctx->ifc_cpuid_highest = cpuid; | |||||
#endif | |||||
return 0; | |||||
} | |||||
int | int | ||||
iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, | iflib_irq_alloc_generic(if_ctx_t ctx, if_irq_t irq, int rid, | ||||
iflib_intr_type_t type, driver_filter_t *filter, | iflib_intr_type_t type, driver_filter_t *filter, | ||||
void *filter_arg, int qid, char *name) | void *filter_arg, int qid, char *name) | ||||
{ | { | ||||
struct grouptask *gtask; | struct grouptask *gtask; | ||||
struct taskqgroup *tqg; | struct taskqgroup *tqg; | ||||
iflib_filter_info_t info; | iflib_filter_info_t info; | ||||
cpuset_t cpus; | |||||
gtask_fn_t *fn; | gtask_fn_t *fn; | ||||
int tqrid, err; | int tqrid, err; | ||||
driver_filter_t *intr_fast; | |||||
void *q; | void *q; | ||||
info = &ctx->ifc_filter_info; | info = &ctx->ifc_filter_info; | ||||
tqrid = rid; | |||||
switch (type) { | switch (type) { | ||||
/* XXX merge tx/rx for netmap? */ | /* XXX merge tx/rx for netmap? */ | ||||
case IFLIB_INTR_TX: | case IFLIB_INTR_TX: | ||||
q = &ctx->ifc_txqs[qid]; | q = &ctx->ifc_txqs[qid]; | ||||
info = &ctx->ifc_txqs[qid].ift_filter_info; | info = &ctx->ifc_txqs[qid].ift_filter_info; | ||||
gtask = &ctx->ifc_txqs[qid].ift_task; | gtask = &ctx->ifc_txqs[qid].ift_task; | ||||
tqg = qgroup_softirq; | tqg = qgroup_if_io_tqg; | ||||
tqrid = irq->ii_rid; | |||||
fn = _task_fn_tx; | fn = _task_fn_tx; | ||||
intr_fast = iflib_fast_intr; | |||||
GROUPTASK_INIT(gtask, 0, fn, q); | |||||
break; | break; | ||||
case IFLIB_INTR_RX: | case IFLIB_INTR_RX: | ||||
q = &ctx->ifc_rxqs[qid]; | q = &ctx->ifc_rxqs[qid]; | ||||
info = &ctx->ifc_rxqs[qid].ifr_filter_info; | info = &ctx->ifc_rxqs[qid].ifr_filter_info; | ||||
gtask = &ctx->ifc_rxqs[qid].ifr_task; | gtask = &ctx->ifc_rxqs[qid].ifr_task; | ||||
tqg = qgroup_softirq; | tqg = qgroup_if_io_tqg; | ||||
tqrid = irq->ii_rid; | |||||
fn = _task_fn_rx; | fn = _task_fn_rx; | ||||
intr_fast = iflib_fast_intr; | |||||
GROUPTASK_INIT(gtask, 0, fn, q); | |||||
break; | break; | ||||
case IFLIB_INTR_RXTX: | |||||
q = &ctx->ifc_rxqs[qid]; | |||||
info = &ctx->ifc_rxqs[qid].ifr_filter_info; | |||||
gtask = &ctx->ifc_rxqs[qid].ifr_task; | |||||
tqg = qgroup_if_io_tqg; | |||||
fn = _task_fn_rx; | |||||
intr_fast = iflib_fast_intr_rxtx; | |||||
GROUPTASK_INIT(gtask, 0, fn, q); | |||||
break; | |||||
case IFLIB_INTR_ADMIN: | case IFLIB_INTR_ADMIN: | ||||
q = ctx; | q = ctx; | ||||
tqrid = -1; | |||||
info = &ctx->ifc_filter_info; | info = &ctx->ifc_filter_info; | ||||
gtask = &ctx->ifc_admin_task; | gtask = &ctx->ifc_admin_task; | ||||
tqg = qgroup_if_config_tqg; | tqg = qgroup_if_config_tqg; | ||||
tqrid = -1; | |||||
fn = _task_fn_admin; | fn = _task_fn_admin; | ||||
intr_fast = iflib_fast_intr_ctx; | |||||
break; | break; | ||||
default: | default: | ||||
panic("unknown net intr type"); | panic("unknown net intr type"); | ||||
} | } | ||||
GROUPTASK_INIT(gtask, 0, fn, q); | |||||
info->ifi_filter = filter; | info->ifi_filter = filter; | ||||
info->ifi_filter_arg = filter_arg; | info->ifi_filter_arg = filter_arg; | ||||
info->ifi_task = gtask; | info->ifi_task = gtask; | ||||
info->ifi_ctx = q; | |||||
/* XXX query cpu that rid belongs to */ | err = _iflib_irq_alloc(ctx, irq, rid, intr_fast, NULL, info, name); | ||||
if (err != 0) { | |||||
err = _iflib_irq_alloc(ctx, irq, rid, iflib_fast_intr, NULL, info, name); | device_printf(ctx->ifc_dev, "_iflib_irq_alloc failed %d\n", err); | ||||
if (err != 0) | |||||
return (err); | return (err); | ||||
} | |||||
if (type == IFLIB_INTR_ADMIN) | |||||
return (0); | |||||
if (tqrid != -1) { | if (tqrid != -1) { | ||||
find_nth(ctx, &cpus, qid); | err = iflib_irq_set_affinity(ctx, rman_get_start(irq->ii_res), type, qid, gtask, tqg, q, name); | ||||
taskqgroup_attach_cpu(tqg, gtask, q, CPU_FFS(&cpus), irq->ii_rid, name); | if (err) | ||||
} else | return (err); | ||||
taskqgroup_attach(tqg, gtask, q, tqrid, name); | } else { | ||||
taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); | |||||
} | |||||
return (0); | return (0); | ||||
} | } | ||||
void | void | ||||
iflib_softirq_alloc_generic(if_ctx_t ctx, int rid, iflib_intr_type_t type, void *arg, int qid, char *name) | iflib_softirq_alloc_generic(if_ctx_t ctx, if_irq_t irq, iflib_intr_type_t type, void *arg, int qid, char *name) | ||||
{ | { | ||||
struct grouptask *gtask; | struct grouptask *gtask; | ||||
struct taskqgroup *tqg; | struct taskqgroup *tqg; | ||||
gtask_fn_t *fn; | gtask_fn_t *fn; | ||||
void *q; | void *q; | ||||
int irq_num = -1; | |||||
int err; | |||||
switch (type) { | switch (type) { | ||||
case IFLIB_INTR_TX: | case IFLIB_INTR_TX: | ||||
q = &ctx->ifc_txqs[qid]; | q = &ctx->ifc_txqs[qid]; | ||||
gtask = &ctx->ifc_txqs[qid].ift_task; | gtask = &ctx->ifc_txqs[qid].ift_task; | ||||
tqg = qgroup_softirq; | tqg = qgroup_if_io_tqg; | ||||
fn = _task_fn_tx; | fn = _task_fn_tx; | ||||
if (irq != NULL) | |||||
irq_num = rman_get_start(irq->ii_res); | |||||
break; | break; | ||||
case IFLIB_INTR_RX: | case IFLIB_INTR_RX: | ||||
q = &ctx->ifc_rxqs[qid]; | q = &ctx->ifc_rxqs[qid]; | ||||
gtask = &ctx->ifc_rxqs[qid].ifr_task; | gtask = &ctx->ifc_rxqs[qid].ifr_task; | ||||
tqg = qgroup_softirq; | tqg = qgroup_if_io_tqg; | ||||
fn = _task_fn_rx; | fn = _task_fn_rx; | ||||
if (irq != NULL) | |||||
irq_num = rman_get_start(irq->ii_res); | |||||
break; | break; | ||||
case IFLIB_INTR_ADMIN: | |||||
q = ctx; | |||||
gtask = &ctx->ifc_admin_task; | |||||
tqg = qgroup_if_config_tqg; | |||||
rid = -1; | |||||
fn = _task_fn_admin; | |||||
break; | |||||
case IFLIB_INTR_IOV: | case IFLIB_INTR_IOV: | ||||
q = ctx; | q = ctx; | ||||
gtask = &ctx->ifc_vflr_task; | gtask = &ctx->ifc_vflr_task; | ||||
tqg = qgroup_if_config_tqg; | tqg = qgroup_if_config_tqg; | ||||
rid = -1; | |||||
fn = _task_fn_iov; | fn = _task_fn_iov; | ||||
break; | break; | ||||
default: | default: | ||||
panic("unknown net intr type"); | panic("unknown net intr type"); | ||||
} | } | ||||
GROUPTASK_INIT(gtask, 0, fn, q); | GROUPTASK_INIT(gtask, 0, fn, q); | ||||
taskqgroup_attach(tqg, gtask, q, rid, name); | if (irq_num != -1) { | ||||
err = iflib_irq_set_affinity(ctx, irq_num, type, qid, gtask, tqg, q, name); | |||||
if (err) | |||||
taskqgroup_attach(tqg, gtask, q, irq_num, name); | |||||
} | } | ||||
else { | |||||
taskqgroup_attach(tqg, gtask, q, irq_num, name); | |||||
} | |||||
} | |||||
void | void | ||||
iflib_irq_free(if_ctx_t ctx, if_irq_t irq) | iflib_irq_free(if_ctx_t ctx, if_irq_t irq) | ||||
{ | { | ||||
if (irq->ii_tag) | if (irq->ii_tag) | ||||
bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); | bus_teardown_intr(ctx->ifc_dev, irq->ii_res, irq->ii_tag); | ||||
if (irq->ii_res) | if (irq->ii_res) | ||||
Show All 12 Lines | iflib_legacy_setup(if_ctx_t ctx, driver_filter_t filter, void *filter_arg, int *rid, char *name) | ||||
gtask_fn_t *fn; | gtask_fn_t *fn; | ||||
int tqrid; | int tqrid; | ||||
void *q; | void *q; | ||||
int err; | int err; | ||||
q = &ctx->ifc_rxqs[0]; | q = &ctx->ifc_rxqs[0]; | ||||
info = &rxq[0].ifr_filter_info; | info = &rxq[0].ifr_filter_info; | ||||
gtask = &rxq[0].ifr_task; | gtask = &rxq[0].ifr_task; | ||||
tqg = qgroup_softirq; | tqg = qgroup_if_io_tqg; | ||||
tqrid = irq->ii_rid = *rid; | tqrid = irq->ii_rid = *rid; | ||||
fn = _task_fn_rx; | fn = _task_fn_rx; | ||||
ctx->ifc_flags |= IFC_LEGACY; | ctx->ifc_flags |= IFC_LEGACY; | ||||
info->ifi_filter = filter; | info->ifi_filter = filter; | ||||
info->ifi_filter_arg = filter_arg; | info->ifi_filter_arg = filter_arg; | ||||
info->ifi_task = gtask; | info->ifi_task = gtask; | ||||
/* We allocate a single interrupt resource */ | /* We allocate a single interrupt resource */ | ||||
if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr, NULL, info, name)) != 0) | if ((err = _iflib_irq_alloc(ctx, irq, tqrid, iflib_fast_intr_ctx, NULL, info, name)) != 0) | ||||
return (err); | return (err); | ||||
GROUPTASK_INIT(gtask, 0, fn, q); | GROUPTASK_INIT(gtask, 0, fn, q); | ||||
taskqgroup_attach(tqg, gtask, q, tqrid, name); | taskqgroup_attach(tqg, gtask, q, rman_get_start(irq->ii_res), name); | ||||
GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); | GROUPTASK_INIT(&txq->ift_task, 0, _task_fn_tx, txq); | ||||
taskqgroup_attach(qgroup_softirq, &txq->ift_task, txq, tqrid, "tx"); | taskqgroup_attach(qgroup_if_io_tqg, &txq->ift_task, txq, rman_get_start(irq->ii_res), "tx"); | ||||
GROUPTASK_INIT(&ctx->ifc_admin_task, 0, _task_fn_admin, ctx); | |||||
taskqgroup_attach(qgroup_if_config_tqg, &ctx->ifc_admin_task, ctx, -1, "admin/link"); | |||||
return (0); | return (0); | ||||
} | } | ||||
void | void | ||||
iflib_led_create(if_ctx_t ctx) | iflib_led_create(if_ctx_t ctx) | ||||
{ | { | ||||
ctx->ifc_led_dev = led_create(iflib_led_func, ctx, | ctx->ifc_led_dev = led_create(iflib_led_func, ctx, | ||||
device_get_nameunit(ctx->ifc_dev)); | device_get_nameunit(ctx->ifc_dev)); | ||||
} | } | ||||
void | void | ||||
iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) | iflib_tx_intr_deferred(if_ctx_t ctx, int txqid) | ||||
{ | { | ||||
GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); | GROUPTASK_ENQUEUE(&ctx->ifc_txqs[txqid].ift_task); | ||||
} | } | ||||
void | void | ||||
iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) | iflib_rx_intr_deferred(if_ctx_t ctx, int rxqid) | ||||
{ | { | ||||
GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); | GROUPTASK_ENQUEUE(&ctx->ifc_rxqs[rxqid].ifr_task); | ||||
} | } | ||||
void | void | ||||
iflib_admin_intr_deferred(if_ctx_t ctx) | iflib_admin_intr_deferred(if_ctx_t ctx) | ||||
{ | { | ||||
#ifdef INVARIANTS | |||||
struct grouptask *gtask; | |||||
gtask = &ctx->ifc_admin_task; | |||||
MPASS(gtask != NULL && gtask->gt_taskqueue != NULL); | |||||
#endif | |||||
GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); | GROUPTASK_ENQUEUE(&ctx->ifc_admin_task); | ||||
} | } | ||||
void | void | ||||
iflib_iov_intr_deferred(if_ctx_t ctx) | iflib_iov_intr_deferred(if_ctx_t ctx) | ||||
{ | { | ||||
GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); | GROUPTASK_ENQUEUE(&ctx->ifc_vflr_task); | ||||
} | } | ||||
void | void | ||||
iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) | iflib_io_tqg_attach(struct grouptask *gt, void *uniq, int cpu, char *name) | ||||
{ | { | ||||
taskqgroup_attach_cpu(qgroup_softirq, gt, uniq, cpu, -1, name); | taskqgroup_attach_cpu(qgroup_if_io_tqg, gt, uniq, cpu, -1, name); | ||||
} | } | ||||
void | void | ||||
iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, | iflib_config_gtask_init(if_ctx_t ctx, struct grouptask *gtask, gtask_fn_t *fn, | ||||
char *name) | char *name) | ||||
{ | { | ||||
GROUPTASK_INIT(gtask, 0, fn, ctx); | GROUPTASK_INIT(gtask, 0, fn, ctx); | ||||
taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); | taskqgroup_attach(qgroup_if_config_tqg, gtask, gtask, -1, name); | ||||
} | } | ||||
void | void | ||||
iflib_config_gtask_deinit(struct grouptask *gtask) | iflib_config_gtask_deinit(struct grouptask *gtask) | ||||
{ | { | ||||
taskqgroup_detach(qgroup_if_config_tqg, gtask); | taskqgroup_detach(qgroup_if_config_tqg, gtask); | ||||
} | } | ||||
void | void | ||||
iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) | iflib_link_state_change(if_ctx_t ctx, int link_state, uint64_t baudrate) | ||||
{ | { | ||||
if_t ifp = ctx->ifc_ifp; | if_t ifp = ctx->ifc_ifp; | ||||
iflib_txq_t txq = ctx->ifc_txqs; | iflib_txq_t txq = ctx->ifc_txqs; | ||||
if_setbaudrate(ifp, baudrate); | if_setbaudrate(ifp, baudrate); | ||||
if (baudrate >= IF_Gbps(10)) | |||||
ctx->ifc_flags |= IFC_PREFETCH; | |||||
/* If link down, disable watchdog */ | /* If link down, disable watchdog */ | ||||
if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { | if ((ctx->ifc_link_state == LINK_STATE_UP) && (link_state == LINK_STATE_DOWN)) { | ||||
for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) | for (int i = 0; i < ctx->ifc_softc_ctx.isc_ntxqsets; i++, txq++) | ||||
txq->ift_qstatus = IFLIB_QUEUE_IDLE; | txq->ift_qstatus = IFLIB_QUEUE_IDLE; | ||||
} | } | ||||
ctx->ifc_link_state = link_state; | ctx->ifc_link_state = link_state; | ||||
if_link_state_change(ifp, link_state); | if_link_state_change(ifp, link_state); | ||||
} | } | ||||
static int | static int | ||||
iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) | iflib_tx_credits_update(if_ctx_t ctx, iflib_txq_t txq) | ||||
{ | { | ||||
int credits; | int credits; | ||||
#ifdef INVARIANTS | |||||
int credits_pre = txq->ift_cidx_processed; | |||||
#endif | |||||
if (ctx->isc_txd_credits_update == NULL) | if (ctx->isc_txd_credits_update == NULL) | ||||
return (0); | return (0); | ||||
if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, txq->ift_cidx_processed, true)) == 0) | if ((credits = ctx->isc_txd_credits_update(ctx->ifc_softc, txq->ift_id, true)) == 0) | ||||
return (0); | return (0); | ||||
txq->ift_processed += credits; | txq->ift_processed += credits; | ||||
txq->ift_cidx_processed += credits; | txq->ift_cidx_processed += credits; | ||||
MPASS(credits_pre + credits == txq->ift_cidx_processed); | |||||
if (txq->ift_cidx_processed >= txq->ift_size) | if (txq->ift_cidx_processed >= txq->ift_size) | ||||
txq->ift_cidx_processed -= txq->ift_size; | txq->ift_cidx_processed -= txq->ift_size; | ||||
return (credits); | return (credits); | ||||
} | } | ||||
static int | static int | ||||
iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, int cidx, int budget) | iflib_rxd_avail(if_ctx_t ctx, iflib_rxq_t rxq, qidx_t cidx, qidx_t budget) | ||||
{ | { | ||||
return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, | return (ctx->isc_rxd_available(ctx->ifc_softc, rxq->ifr_id, cidx, | ||||
budget)); | budget)); | ||||
} | } | ||||
void | void | ||||
iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, | iflib_add_int_delay_sysctl(if_ctx_t ctx, const char *name, | ||||
Show All 21 Lines | |||||
{ | { | ||||
device_t dev = ctx->ifc_dev; | device_t dev = ctx->ifc_dev; | ||||
if_shared_ctx_t sctx = ctx->ifc_sctx; | if_shared_ctx_t sctx = ctx->ifc_sctx; | ||||
if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; | if_softc_ctx_t scctx = &ctx->ifc_softc_ctx; | ||||
int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; | int vectors, queues, rx_queues, tx_queues, queuemsgs, msgs; | ||||
int iflib_num_tx_queues, iflib_num_rx_queues; | int iflib_num_tx_queues, iflib_num_rx_queues; | ||||
int err, admincnt, bar; | int err, admincnt, bar; | ||||
iflib_num_tx_queues = scctx->isc_ntxqsets; | iflib_num_tx_queues = ctx->ifc_sysctl_ntxqs; | ||||
iflib_num_rx_queues = scctx->isc_nrxqsets; | iflib_num_rx_queues = ctx->ifc_sysctl_nrxqs; | ||||
device_printf(dev, "msix_init qsets capped at %d\n", imax(scctx->isc_ntxqsets, scctx->isc_nrxqsets)); | |||||
bar = ctx->ifc_softc_ctx.isc_msix_bar; | bar = ctx->ifc_softc_ctx.isc_msix_bar; | ||||
admincnt = sctx->isc_admin_intrcnt; | admincnt = sctx->isc_admin_intrcnt; | ||||
/* Override by global tuneable */ | |||||
{ | |||||
int i; | |||||
size_t len = sizeof(i); | |||||
err = kernel_sysctlbyname(curthread, "hw.pci.enable_msix", &i, &len, NULL, 0, NULL, 0); | |||||
if (err == 0) { | |||||
if (i == 0) | |||||
goto msi; | |||||
} | |||||
else { | |||||
device_printf(dev, "unable to read hw.pci.enable_msix."); | |||||
} | |||||
} | |||||
/* Override by tuneable */ | /* Override by tuneable */ | ||||
if (enable_msix == 0) | if (scctx->isc_disable_msix) | ||||
goto msi; | goto msi; | ||||
/* | /* | ||||
** When used in a virtualized environment | ** When used in a virtualized environment | ||||
** PCI BUSMASTER capability may not be set | ** PCI BUSMASTER capability may not be set | ||||
** so explicity set it here and rewrite | ** so explicity set it here and rewrite | ||||
** the ENABLE in the MSIX control register | ** the ENABLE in the MSIX control register | ||||
** at this point to cause the host to | ** at this point to cause the host to | ||||
** successfully initialize us. | ** successfully initialize us. | ||||
*/ | */ | ||||
{ | { | ||||
uint16_t pci_cmd_word; | |||||
int msix_ctrl, rid; | int msix_ctrl, rid; | ||||
pci_enable_busmaster(dev); | |||||
rid = 0; | rid = 0; | ||||
pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); | if (pci_find_cap(dev, PCIY_MSIX, &rid) == 0 && rid != 0) { | ||||
pci_cmd_word |= PCIM_CMD_BUSMASTEREN; | |||||
pci_write_config(dev, PCIR_COMMAND, pci_cmd_word, 2); | |||||
pci_find_cap(dev, PCIY_MSIX, &rid); | |||||
rid += PCIR_MSIX_CTRL; | rid += PCIR_MSIX_CTRL; | ||||
msix_ctrl = pci_read_config(dev, rid, 2); | msix_ctrl = pci_read_config(dev, rid, 2); | ||||
msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; | msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE; | ||||
pci_write_config(dev, rid, msix_ctrl, 2); | pci_write_config(dev, rid, msix_ctrl, 2); | ||||
} else { | |||||
device_printf(dev, "PCIY_MSIX capability not found; " | |||||
"or rid %d == 0.\n", rid); | |||||
goto msi; | |||||
} | } | ||||
} | |||||
/* | /* | ||||
* bar == -1 => "trust me I know what I'm doing" | * bar == -1 => "trust me I know what I'm doing" | ||||
* Some drivers are for hardware that is so shoddily | * Some drivers are for hardware that is so shoddily | ||||
* documented that no one knows which bars are which | * documented that no one knows which bars are which | ||||
* so the developer has to map all bars. This hack | * so the developer has to map all bars. This hack | ||||
* allows shoddy garbage to use msix in this framework. | * allows shoddy garbage to use msix in this framework. | ||||
*/ | */ | ||||
Show All 15 Lines | if ((msgs = pci_msix_count(dev)) == 0) { /* system has msix disabled */ | ||||
goto msi; | goto msi; | ||||
} | } | ||||
#if IFLIB_DEBUG | #if IFLIB_DEBUG | ||||
/* use only 1 qset in debug mode */ | /* use only 1 qset in debug mode */ | ||||
queuemsgs = min(msgs - admincnt, 1); | queuemsgs = min(msgs - admincnt, 1); | ||||
#else | #else | ||||
queuemsgs = msgs - admincnt; | queuemsgs = msgs - admincnt; | ||||
#endif | #endif | ||||
if (bus_get_cpus(dev, INTR_CPUS, sizeof(ctx->ifc_cpus), &ctx->ifc_cpus) == 0) { | |||||
#ifdef RSS | #ifdef RSS | ||||
queues = imin(queuemsgs, rss_getnumbuckets()); | queues = imin(queuemsgs, rss_getnumbuckets()); | ||||
#else | #else | ||||
queues = queuemsgs; | queues = queuemsgs; | ||||
#endif | #endif | ||||
queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); | queues = imin(CPU_COUNT(&ctx->ifc_cpus), queues); | ||||
device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", | device_printf(dev, "pxm cpus: %d queue msgs: %d admincnt: %d\n", | ||||
CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); | CPU_COUNT(&ctx->ifc_cpus), queuemsgs, admincnt); | ||||
} else { | |||||
device_printf(dev, "Unable to fetch CPU list\n"); | |||||
/* Figure out a reasonable auto config value */ | |||||
queues = min(queuemsgs, mp_ncpus); | |||||
} | |||||
#ifdef RSS | #ifdef RSS | ||||
/* If we're doing RSS, clamp at the number of RSS buckets */ | /* If we're doing RSS, clamp at the number of RSS buckets */ | ||||
if (queues > rss_getnumbuckets()) | if (queues > rss_getnumbuckets()) | ||||
queues = rss_getnumbuckets(); | queues = rss_getnumbuckets(); | ||||
#endif | #endif | ||||
if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) | if (iflib_num_rx_queues > 0 && iflib_num_rx_queues < queuemsgs - admincnt) | ||||
rx_queues = iflib_num_rx_queues; | rx_queues = iflib_num_rx_queues; | ||||
else | else | ||||
rx_queues = queues; | rx_queues = queues; | ||||
if (rx_queues > scctx->isc_nrxqsets) | |||||
rx_queues = scctx->isc_nrxqsets; | |||||
/* | /* | ||||
* We want this to be all logical CPUs by default | * We want this to be all logical CPUs by default | ||||
*/ | */ | ||||
if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) | if (iflib_num_tx_queues > 0 && iflib_num_tx_queues < queues) | ||||
tx_queues = iflib_num_tx_queues; | tx_queues = iflib_num_tx_queues; | ||||
else | else | ||||
tx_queues = mp_ncpus; | tx_queues = mp_ncpus; | ||||
if (tx_queues > scctx->isc_ntxqsets) | |||||
tx_queues = scctx->isc_ntxqsets; | |||||
if (ctx->ifc_sysctl_qs_eq_override == 0) { | if (ctx->ifc_sysctl_qs_eq_override == 0) { | ||||
#ifdef INVARIANTS | #ifdef INVARIANTS | ||||
if (tx_queues != rx_queues) | if (tx_queues != rx_queues) | ||||
device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", | device_printf(dev, "queue equality override not set, capping rx_queues at %d and tx_queues at %d\n", | ||||
min(rx_queues, tx_queues), min(rx_queues, tx_queues)); | min(rx_queues, tx_queues), min(rx_queues, tx_queues)); | ||||
#endif | #endif | ||||
tx_queues = min(rx_queues, tx_queues); | tx_queues = min(rx_queues, tx_queues); | ||||
rx_queues = min(rx_queues, tx_queues); | rx_queues = min(rx_queues, tx_queues); | ||||
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines | |||||
}; | }; | ||||
static int | static int | ||||
mp_ndesc_handler(SYSCTL_HANDLER_ARGS) | mp_ndesc_handler(SYSCTL_HANDLER_ARGS) | ||||
{ | { | ||||
if_ctx_t ctx = (void *)arg1; | if_ctx_t ctx = (void *)arg1; | ||||
enum iflib_ndesc_handler type = arg2; | enum iflib_ndesc_handler type = arg2; | ||||
char buf[256] = {0}; | char buf[256] = {0}; | ||||
uint16_t *ndesc; | qidx_t *ndesc; | ||||
char *p, *next; | char *p, *next; | ||||
int nqs, rc, i; | int nqs, rc, i; | ||||
MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); | MPASS(type == IFLIB_NTXD_HANDLER || type == IFLIB_NRXD_HANDLER); | ||||
nqs = 8; | nqs = 8; | ||||
switch(type) { | switch(type) { | ||||
case IFLIB_NTXD_HANDLER: | case IFLIB_NTXD_HANDLER: | ||||
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines | SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_ntxqs", | ||||
CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, | CTLFLAG_RWTUN, &ctx->ifc_sysctl_ntxqs, 0, | ||||
"# of txqs to use, 0 => use default #"); | "# of txqs to use, 0 => use default #"); | ||||
SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", | SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_nrxqs", | ||||
CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, | CTLFLAG_RWTUN, &ctx->ifc_sysctl_nrxqs, 0, | ||||
"# of rxqs to use, 0 => use default #"); | "# of rxqs to use, 0 => use default #"); | ||||
SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", | SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "override_qs_enable", | ||||
CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, | CTLFLAG_RWTUN, &ctx->ifc_sysctl_qs_eq_override, 0, | ||||
"permit #txq != #rxq"); | "permit #txq != #rxq"); | ||||
SYSCTL_ADD_INT(ctx_list, oid_list, OID_AUTO, "disable_msix", | |||||
CTLFLAG_RWTUN, &ctx->ifc_softc_ctx.isc_disable_msix, 0, | |||||
"disable MSIX (default 0)"); | |||||
SYSCTL_ADD_U16(ctx_list, oid_list, OID_AUTO, "rx_budget", | |||||
CTLFLAG_RWTUN, &ctx->ifc_sysctl_rx_budget, 0, | |||||
"set the rx budget"); | |||||
/* XXX change for per-queue sizes */ | /* XXX change for per-queue sizes */ | ||||
SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", | SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_ntxds", | ||||
CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, | CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NTXD_HANDLER, | ||||
mp_ndesc_handler, "A", | mp_ndesc_handler, "A", | ||||
"list of # of tx descriptors to use, 0 = use default #"); | "list of # of tx descriptors to use, 0 = use default #"); | ||||
SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", | SYSCTL_ADD_PROC(ctx_list, oid_list, OID_AUTO, "override_nrxds", | ||||
CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, | CTLTYPE_STRING|CTLFLAG_RWTUN, ctx, IFLIB_NRXD_HANDLER, | ||||
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines | SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "txq_in_use", | ||||
&txq->ift_in_use, 1, "descriptors in use"); | &txq->ift_in_use, 1, "descriptors in use"); | ||||
SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", | SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_processed", | ||||
CTLFLAG_RD, | CTLFLAG_RD, | ||||
&txq->ift_processed, "descriptors procesed for clean"); | &txq->ift_processed, "descriptors procesed for clean"); | ||||
SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", | SYSCTL_ADD_QUAD(ctx_list, queue_list, OID_AUTO, "txq_cleaned", | ||||
CTLFLAG_RD, | CTLFLAG_RD, | ||||
&txq->ift_cleaned, "total cleaned"); | &txq->ift_cleaned, "total cleaned"); | ||||
SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", | SYSCTL_ADD_PROC(ctx_list, queue_list, OID_AUTO, "ring_state", | ||||
CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br[0]->state), | CTLTYPE_STRING | CTLFLAG_RD, __DEVOLATILE(uint64_t *, &txq->ift_br->state), | ||||
0, mp_ring_state_handler, "A", "soft ring state"); | 0, mp_ring_state_handler, "A", "soft ring state"); | ||||
SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", | SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_enqueues", | ||||
CTLFLAG_RD, &txq->ift_br[0]->enqueues, | CTLFLAG_RD, &txq->ift_br->enqueues, | ||||
"# of enqueues to the mp_ring for this queue"); | "# of enqueues to the mp_ring for this queue"); | ||||
SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", | SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_drops", | ||||
CTLFLAG_RD, &txq->ift_br[0]->drops, | CTLFLAG_RD, &txq->ift_br->drops, | ||||
"# of drops in the mp_ring for this queue"); | "# of drops in the mp_ring for this queue"); | ||||
SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", | SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_starts", | ||||
CTLFLAG_RD, &txq->ift_br[0]->starts, | CTLFLAG_RD, &txq->ift_br->starts, | ||||
"# of normal consumer starts in the mp_ring for this queue"); | "# of normal consumer starts in the mp_ring for this queue"); | ||||
SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", | SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_stalls", | ||||
CTLFLAG_RD, &txq->ift_br[0]->stalls, | CTLFLAG_RD, &txq->ift_br->stalls, | ||||
"# of consumer stalls in the mp_ring for this queue"); | "# of consumer stalls in the mp_ring for this queue"); | ||||
SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", | SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_restarts", | ||||
CTLFLAG_RD, &txq->ift_br[0]->restarts, | CTLFLAG_RD, &txq->ift_br->restarts, | ||||
"# of consumer restarts in the mp_ring for this queue"); | "# of consumer restarts in the mp_ring for this queue"); | ||||
SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", | SYSCTL_ADD_COUNTER_U64(ctx_list, queue_list, OID_AUTO, "r_abdications", | ||||
CTLFLAG_RD, &txq->ift_br[0]->abdications, | CTLFLAG_RD, &txq->ift_br->abdications, | ||||
"# of consumer abdications in the mp_ring for this queue"); | "# of consumer abdications in the mp_ring for this queue"); | ||||
} | } | ||||
if (scctx->isc_nrxqsets > 100) | if (scctx->isc_nrxqsets > 100) | ||||
qfmt = "rxq%03d"; | qfmt = "rxq%03d"; | ||||
else if (scctx->isc_nrxqsets > 10) | else if (scctx->isc_nrxqsets > 10) | ||||
qfmt = "rxq%02d"; | qfmt = "rxq%02d"; | ||||
else | else | ||||
qfmt = "rxq%d"; | qfmt = "rxq%d"; | ||||
for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { | for (i = 0, rxq = ctx->ifc_rxqs; i < scctx->isc_nrxqsets; i++, rxq++) { | ||||
snprintf(namebuf, NAME_BUFLEN, qfmt, i); | snprintf(namebuf, NAME_BUFLEN, qfmt, i); | ||||
queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, | queue_node = SYSCTL_ADD_NODE(ctx_list, child, OID_AUTO, namebuf, | ||||
CTLFLAG_RD, NULL, "Queue Name"); | CTLFLAG_RD, NULL, "Queue Name"); | ||||
queue_list = SYSCTL_CHILDREN(queue_node); | queue_list = SYSCTL_CHILDREN(queue_node); | ||||
if (sctx->isc_flags & IFLIB_HAS_RXCQ) { | if (sctx->isc_flags & IFLIB_HAS_RXCQ) { | ||||
SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", | SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_pidx", | ||||
CTLFLAG_RD, | CTLFLAG_RD, | ||||
&rxq->ifr_cq_pidx, 1, "Producer Index"); | &rxq->ifr_cq_pidx, 1, "Producer Index"); | ||||
SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", | SYSCTL_ADD_U16(ctx_list, queue_list, OID_AUTO, "rxq_cq_cidx", | ||||
CTLFLAG_RD, | CTLFLAG_RD, | ||||
&rxq->ifr_cq_cidx, 1, "Consumer Index"); | &rxq->ifr_cq_cidx, 1, "Consumer Index"); | ||||
} | } | ||||
for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { | for (j = 0, fl = rxq->ifr_fl; j < rxq->ifr_nfl; j++, fl++) { | ||||
snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); | snprintf(namebuf, NAME_BUFLEN, "rxq_fl%d", j); | ||||
fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, | fl_node = SYSCTL_ADD_NODE(ctx_list, queue_list, OID_AUTO, namebuf, | ||||
CTLFLAG_RD, NULL, "freelist Name"); | CTLFLAG_RD, NULL, "freelist Name"); | ||||
fl_list = SYSCTL_CHILDREN(fl_node); | fl_list = SYSCTL_CHILDREN(fl_node); | ||||
SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", | SYSCTL_ADD_U16(ctx_list, fl_list, OID_AUTO, "pidx", | ||||
CTLFLAG_RD, | CTLFLAG_RD, | ||||
&fl->ifl_pidx, 1, "Producer Index"); | &fl->ifl_pidx, 1, "Producer Index"); | ||||
Show All 17 Lines | #if MEMORY_LOGGING | ||||
CTLFLAG_RD, | CTLFLAG_RD, | ||||
&fl->ifl_cl_dequeued, "clusters freed"); | &fl->ifl_cl_dequeued, "clusters freed"); | ||||
#endif | #endif | ||||
} | } | ||||
} | } | ||||
} | } | ||||
#ifndef __NO_STRICT_ALIGNMENT | |||||
static struct mbuf * | |||||
iflib_fixup_rx(struct mbuf *m) | |||||
{ | |||||
struct mbuf *n; | |||||
if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { | |||||
bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); | |||||
m->m_data += ETHER_HDR_LEN; | |||||
n = m; | |||||
} else { | |||||
MGETHDR(n, M_NOWAIT, MT_DATA); | |||||
if (n == NULL) { | |||||
m_freem(m); | |||||
return (NULL); | |||||
} | |||||
bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); | |||||
m->m_data += ETHER_HDR_LEN; | |||||
m->m_len -= ETHER_HDR_LEN; | |||||
n->m_len = ETHER_HDR_LEN; | |||||
M_MOVE_PKTHDR(n, m); | |||||
n->m_next = m; | |||||
} | |||||
return (n); | |||||
} | |||||
#endif |