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sys/dev/ixl/ixl.h
/****************************************************************************** | /****************************************************************************** | ||||
Copyright (c) 2013-2015, Intel Corporation | Copyright (c) 2013-2017, Intel Corporation | ||||
All rights reserved. | All rights reserved. | ||||
Redistribution and use in source and binary forms, with or without | Redistribution and use in source and binary forms, with or without | ||||
modification, are permitted provided that the following conditions are met: | modification, are permitted provided that the following conditions are met: | ||||
1. Redistributions of source code must retain the above copyright notice, | 1. Redistributions of source code must retain the above copyright notice, | ||||
this list of conditions and the following disclaimer. | this list of conditions and the following disclaimer. | ||||
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* Ring Descriptors Valid Range: 32-4096 Default Value: 1024 This value is the | * Ring Descriptors Valid Range: 32-4096 Default Value: 1024 This value is the | ||||
* number of tx/rx descriptors allocated by the driver. Increasing this | * number of tx/rx descriptors allocated by the driver. Increasing this | ||||
* value allows the driver to queue more operations. | * value allows the driver to queue more operations. | ||||
* | * | ||||
* Tx descriptors are always 16 bytes, but Rx descriptors can be 32 bytes. | * Tx descriptors are always 16 bytes, but Rx descriptors can be 32 bytes. | ||||
* The driver currently always uses 32 byte Rx descriptors. | * The driver currently always uses 32 byte Rx descriptors. | ||||
*/ | */ | ||||
#define IXL_DEFAULT_RING 1024 | #define IXL_DEFAULT_RING 1024 | ||||
#define IXL_MAX_RING 8160 | #define IXL_MAX_RING 4096 | ||||
#define IXL_MIN_RING 32 | #define IXL_MIN_RING 64 | ||||
#define IXL_RING_INCREMENT 32 | #define IXL_RING_INCREMENT 32 | ||||
#define IXL_AQ_LEN 256 | #define IXL_AQ_LEN 256 | ||||
#define IXL_AQ_LEN_MAX 1024 | #define IXL_AQ_LEN_MAX 1024 | ||||
/* | /* | ||||
** Default number of entries in Tx queue buf_ring. | ** Default number of entries in Tx queue buf_ring. | ||||
*/ | */ | ||||
#define DEFAULT_TXBRSZ 4096 | #define DEFAULT_TXBRSZ 4096 | ||||
/* Alignment for rings */ | /* Alignment for rings */ | ||||
#define DBA_ALIGN 128 | #define DBA_ALIGN 128 | ||||
/* | /* | ||||
* This is the max watchdog interval, ie. the time that can | * This is the max watchdog interval, ie. the time that can | ||||
* pass between any two TX clean operations, such only happening | * pass between any two TX clean operations, such only happening | ||||
* when the TX hardware is functioning. | * when the TX hardware is functioning. | ||||
* | |||||
* XXX: Watchdog currently counts down in units of (hz) | |||||
* Set this to just (hz) if you want queues to hang under a little bit of stress | |||||
*/ | */ | ||||
#define IXL_WATCHDOG (10 * hz) | #define IXL_WATCHDOG (10 * hz) | ||||
/* | /* | ||||
* This parameters control when the driver calls the routine to reclaim | * This parameters control when the driver calls the routine to reclaim | ||||
* transmit descriptors. | * transmit descriptors. | ||||
*/ | */ | ||||
#define IXL_TX_CLEANUP_THRESHOLD (que->num_desc / 8) | #define IXL_TX_CLEANUP_THRESHOLD (que->num_tx_desc / 8) | ||||
#define IXL_TX_OP_THRESHOLD (que->num_desc / 32) | #define IXL_TX_OP_THRESHOLD (que->num_tx_desc / 32) | ||||
#define MAX_MULTICAST_ADDR 128 | #define MAX_MULTICAST_ADDR 128 | ||||
#define IXL_MSIX_BAR 3 | #define IXL_MSIX_BAR 3 | ||||
#define IXL_ADM_LIMIT 2 | #define IXL_ADM_LIMIT 2 | ||||
#define IXL_TSO_SIZE 65535 | #define IXL_TSO_SIZE 65535 | ||||
#define IXL_AQ_BUF_SZ ((u32) 4096) | #define IXL_AQ_BUF_SZ ((u32) 4096) | ||||
#define IXL_RX_HDR 128 | #define IXL_RX_HDR 128 | ||||
#define IXL_RX_LIMIT 512 | #define IXL_RX_LIMIT 512 | ||||
#define IXL_RX_ITR 0 | #define IXL_RX_ITR 0 | ||||
#define IXL_TX_ITR 1 | #define IXL_TX_ITR 1 | ||||
#define IXL_ITR_NONE 3 | #define IXL_ITR_NONE 3 | ||||
#define IXL_QUEUE_EOL 0x7FF | #define IXL_QUEUE_EOL 0x7FF | ||||
#define IXL_MAX_FRAME 9728 | #define IXL_MAX_FRAME 9728 | ||||
#define IXL_MAX_TX_SEGS 8 | #define IXL_MAX_TX_SEGS 8 | ||||
#define IXL_MAX_TSO_SEGS 128 | #define IXL_MAX_TSO_SEGS 128 | ||||
#define IXL_SPARSE_CHAIN 6 | #define IXL_SPARSE_CHAIN 7 | ||||
#define IXL_QUEUE_HUNG 0x80000000 | #define IXL_QUEUE_HUNG 0x80000000 | ||||
#define IXL_MIN_TSO_MSS 64 | #define IXL_MIN_TSO_MSS 64 | ||||
#define IXL_MAX_DMA_SEG_SIZE ((16 * 1024) - 1) | |||||
#define IXL_RSS_KEY_SIZE_REG 13 | #define IXL_RSS_KEY_SIZE_REG 13 | ||||
#define IXL_RSS_KEY_SIZE (IXL_RSS_KEY_SIZE_REG * 4) | #define IXL_RSS_KEY_SIZE (IXL_RSS_KEY_SIZE_REG * 4) | ||||
#define IXL_RSS_VSI_LUT_SIZE 64 /* X722 -> VSI, X710 -> VF */ | #define IXL_RSS_VSI_LUT_SIZE 64 /* X722 -> VSI, X710 -> VF */ | ||||
#define IXL_RSS_VSI_LUT_ENTRY_MASK 0x3F | #define IXL_RSS_VSI_LUT_ENTRY_MASK 0x3F | ||||
#define IXL_RSS_VF_LUT_ENTRY_MASK 0xF | #define IXL_RSS_VF_LUT_ENTRY_MASK 0xF | ||||
#define IXL_VF_MAX_BUFFER 0x3F80 | #define IXL_VF_MAX_BUFFER 0x3F80 | ||||
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*/ | */ | ||||
struct ixl_queue { | struct ixl_queue { | ||||
struct ixl_vsi *vsi; | struct ixl_vsi *vsi; | ||||
u32 me; | u32 me; | ||||
u32 msix; /* This queue's MSIX vector */ | u32 msix; /* This queue's MSIX vector */ | ||||
u32 eims; /* This queue's EIMS bit */ | u32 eims; /* This queue's EIMS bit */ | ||||
struct resource *res; | struct resource *res; | ||||
void *tag; | void *tag; | ||||
int num_desc; /* both tx and rx */ | int num_tx_desc; /* both tx and rx */ | ||||
int num_rx_desc; /* both tx and rx */ | |||||
#ifdef DEV_NETMAP | |||||
int num_desc; /* for compatibility with current netmap code in kernel */ | |||||
#endif | |||||
struct tx_ring txr; | struct tx_ring txr; | ||||
struct rx_ring rxr; | struct rx_ring rxr; | ||||
struct task task; | struct task task; | ||||
struct task tx_task; | struct task tx_task; | ||||
struct taskqueue *tq; | struct taskqueue *tq; | ||||
/* Queue stats */ | /* Queue stats */ | ||||
u64 irqs; | u64 irqs; | ||||
Show All 14 Lines | struct ixl_vsi { | ||||
void *back; | void *back; | ||||
struct ifnet *ifp; | struct ifnet *ifp; | ||||
device_t dev; | device_t dev; | ||||
struct i40e_hw *hw; | struct i40e_hw *hw; | ||||
struct ifmedia media; | struct ifmedia media; | ||||
enum i40e_vsi_type type; | enum i40e_vsi_type type; | ||||
int id; | int id; | ||||
u16 num_queues; | u16 num_queues; | ||||
int num_tx_desc; | |||||
int num_rx_desc; | |||||
u32 rx_itr_setting; | u32 rx_itr_setting; | ||||
u32 tx_itr_setting; | u32 tx_itr_setting; | ||||
u16 max_frame_size; | u16 max_frame_size; | ||||
bool enable_head_writeback; | |||||
struct ixl_queue *queues; /* head of queues */ | struct ixl_queue *queues; /* head of queues */ | ||||
u16 vsi_num; | u16 vsi_num; | ||||
bool link_active; | bool link_active; | ||||
u16 seid; | u16 seid; | ||||
u16 uplink_seid; | u16 uplink_seid; | ||||
u16 downlink_seid; | u16 downlink_seid; | ||||
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static inline u16 | static inline u16 | ||||
ixl_rx_unrefreshed(struct ixl_queue *que) | ixl_rx_unrefreshed(struct ixl_queue *que) | ||||
{ | { | ||||
struct rx_ring *rxr = &que->rxr; | struct rx_ring *rxr = &que->rxr; | ||||
if (rxr->next_check > rxr->next_refresh) | if (rxr->next_check > rxr->next_refresh) | ||||
return (rxr->next_check - rxr->next_refresh - 1); | return (rxr->next_check - rxr->next_refresh - 1); | ||||
else | else | ||||
return ((que->num_desc + rxr->next_check) - | return ((que->num_rx_desc + rxr->next_check) - | ||||
rxr->next_refresh - 1); | rxr->next_refresh - 1); | ||||
} | } | ||||
/* | /* | ||||
** Find the next available unused filter | ** Find the next available unused filter | ||||
*/ | */ | ||||
static inline struct ixl_mac_filter * | static inline struct ixl_mac_filter * | ||||
ixl_get_filter(struct ixl_vsi *vsi) | ixl_get_filter(struct ixl_vsi *vsi) | ||||
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bool ixl_rxeof(struct ixl_queue *, int); | bool ixl_rxeof(struct ixl_queue *, int); | ||||
bool ixl_txeof(struct ixl_queue *); | bool ixl_txeof(struct ixl_queue *); | ||||
void ixl_free_que_tx(struct ixl_queue *); | void ixl_free_que_tx(struct ixl_queue *); | ||||
void ixl_free_que_rx(struct ixl_queue *); | void ixl_free_que_rx(struct ixl_queue *); | ||||
int ixl_mq_start(struct ifnet *, struct mbuf *); | int ixl_mq_start(struct ifnet *, struct mbuf *); | ||||
int ixl_mq_start_locked(struct ifnet *, struct tx_ring *); | int ixl_mq_start_locked(struct ifnet *, struct tx_ring *); | ||||
void ixl_deferred_mq_start(void *, int); | void ixl_deferred_mq_start(void *, int); | ||||
void ixl_vsi_setup_rings_size(struct ixl_vsi *, int, int); | |||||
void ixl_free_vsi(struct ixl_vsi *); | void ixl_free_vsi(struct ixl_vsi *); | ||||
void ixl_qflush(struct ifnet *); | void ixl_qflush(struct ifnet *); | ||||
/* Common function prototypes between PF/VF driver */ | /* Common function prototypes between PF/VF driver */ | ||||
#if __FreeBSD_version >= 1100000 | #if __FreeBSD_version >= 1100000 | ||||
uint64_t ixl_get_counter(if_t ifp, ift_counter cnt); | uint64_t ixl_get_counter(if_t ifp, ift_counter cnt); | ||||
#endif | #endif | ||||
void ixl_get_default_rss_key(u32 *); | void ixl_get_default_rss_key(u32 *); | ||||
const char * i40e_vc_stat_str(struct i40e_hw *hw, | |||||
enum virtchnl_status_code stat_err); | |||||
void ixl_set_busmaster(device_t); | |||||
void ixl_set_msix_enable(device_t); | |||||
#endif /* _IXL_H_ */ | #endif /* _IXL_H_ */ |