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sys/dev/pci/pci_host_generic.c
| Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines | |||||
| #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ | #define PCIE_ADDR_OFFSET(bus, slot, func, reg) \ | ||||
| ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ | ((((bus) & PCIE_BUS_MASK) << PCIE_BUS_SHIFT) | \ | ||||
| (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ | (((slot) & PCIE_SLOT_MASK) << PCIE_SLOT_SHIFT) | \ | ||||
| (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ | (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ | ||||
| ((reg) & PCIE_REG_MASK)) | ((reg) & PCIE_REG_MASK)) | ||||
| /* Forward prototypes */ | /* Forward prototypes */ | ||||
| static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot, | |||||
| u_int func, u_int reg, int bytes); | |||||
| static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot, | static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot, | ||||
| u_int func, u_int reg, uint32_t val, int bytes); | u_int func, u_int reg, uint32_t val, int bytes); | ||||
| static int generic_pcie_maxslots(device_t dev); | static int generic_pcie_maxslots(device_t dev); | ||||
| static int generic_pcie_read_ivar(device_t dev, device_t child, int index, | static int generic_pcie_read_ivar(device_t dev, device_t child, int index, | ||||
| uintptr_t *result); | uintptr_t *result); | ||||
| static int generic_pcie_write_ivar(device_t dev, device_t child, int index, | static int generic_pcie_write_ivar(device_t dev, device_t child, int index, | ||||
| uintptr_t value); | uintptr_t value); | ||||
| Show All 18 Lines | error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ | ||||
| BUS_SPACE_MAXSIZE, /* maxsegsize */ | BUS_SPACE_MAXSIZE, /* maxsegsize */ | ||||
| sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */ | sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */ | ||||
| NULL, NULL, /* lockfunc, lockarg */ | NULL, NULL, /* lockfunc, lockarg */ | ||||
| &sc->dmat); | &sc->dmat); | ||||
| if (error != 0) | if (error != 0) | ||||
| return (error); | return (error); | ||||
| rid = 0; | rid = 0; | ||||
| sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); | sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE | RF_SHAREABLE); | ||||
| if (sc->res == NULL) { | if (sc->res == NULL) { | ||||
| device_printf(dev, "could not map memory.\n"); | device_printf(dev, "could not map memory.\n"); | ||||
| return (ENXIO); | return (ENXIO); | ||||
| } | } | ||||
| sc->bst = rman_get_bustag(sc->res); | sc->bst = rman_get_bustag(sc->res); | ||||
| sc->bsh = rman_get_bushandle(sc->res); | sc->bsh = rman_get_bushandle(sc->res); | ||||
| Show All 13 Lines | pci_host_generic_core_attach(device_t dev) | ||||
| if (error) { | if (error) { | ||||
| device_printf(dev, "rman_init() failed. error = %d\n", error); | device_printf(dev, "rman_init() failed. error = %d\n", error); | ||||
| return (error); | return (error); | ||||
| } | } | ||||
| return (0); | return (0); | ||||
| } | } | ||||
| static uint32_t | uint32_t | ||||
| generic_pcie_read_config(device_t dev, u_int bus, u_int slot, | generic_pcie_read_config(device_t dev, u_int bus, u_int slot, | ||||
| u_int func, u_int reg, int bytes) | u_int func, u_int reg, int bytes) | ||||
| { | { | ||||
| struct generic_pcie_core_softc *sc; | struct generic_pcie_core_softc *sc; | ||||
| bus_space_handle_t h; | bus_space_handle_t h; | ||||
| bus_space_tag_t t; | bus_space_tag_t t; | ||||
| uint64_t offset; | uint64_t offset; | ||||
| uint32_t data; | uint32_t data; | ||||
| ▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines | |||||
| { | { | ||||
| struct generic_pcie_core_softc *sc; | struct generic_pcie_core_softc *sc; | ||||
| int secondary_bus; | int secondary_bus; | ||||
| sc = device_get_softc(dev); | sc = device_get_softc(dev); | ||||
| if (index == PCIB_IVAR_BUS) { | if (index == PCIB_IVAR_BUS) { | ||||
| /* this pcib adds only pci bus 0 as child */ | /* this pcib adds only pci bus 0 as child */ | ||||
| secondary_bus = 0; | secondary_bus = 0; | ||||
andrew: Why 0x80? | |||||
Not Done Inline ActionsEvery 0x80 we have _BBN number of root complex. I can create analogue function in pci_host_generic_acpi, and obtain value directly from acpi pdk_semihalf.com: Every 0x80 we have _BBN number of root complex. I can create analogue function in… | |||||
| *result = secondary_bus; | *result = secondary_bus; | ||||
| return (0); | return (0); | ||||
| } | } | ||||
| if (index == PCIB_IVAR_DOMAIN) { | if (index == PCIB_IVAR_DOMAIN) { | ||||
| *result = sc->ecam; | *result = sc->ecam; | ||||
| return (0); | return (0); | ||||
| ▲ Show 20 Lines • Show All 156 Lines • Show Last 20 Lines | |||||
Why 0x80?