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sys/arm64/include/cpu.h
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#define CPU_IMPL_FREESCALE 0x4D | #define CPU_IMPL_FREESCALE 0x4D | ||||
#define CPU_IMPL_NVIDIA 0x4E | #define CPU_IMPL_NVIDIA 0x4E | ||||
#define CPU_IMPL_APM 0x50 | #define CPU_IMPL_APM 0x50 | ||||
#define CPU_IMPL_QUALCOMM 0x51 | #define CPU_IMPL_QUALCOMM 0x51 | ||||
#define CPU_IMPL_MARVELL 0x56 | #define CPU_IMPL_MARVELL 0x56 | ||||
#define CPU_IMPL_INTEL 0x69 | #define CPU_IMPL_INTEL 0x69 | ||||
#define CPU_PART_THUNDER 0x0A1 | #define CPU_PART_THUNDER 0x0A1 | ||||
#define CPU_PART_THUNDERX2 0x0AF | |||||
#define CPU_PART_FOUNDATION 0xD00 | #define CPU_PART_FOUNDATION 0xD00 | ||||
#define CPU_PART_CORTEX_A35 0xD04 | #define CPU_PART_CORTEX_A35 0xD04 | ||||
#define CPU_PART_CORTEX_A53 0xD03 | #define CPU_PART_CORTEX_A53 0xD03 | ||||
#define CPU_PART_CORTEX_A55 0xD05 | #define CPU_PART_CORTEX_A55 0xD05 | ||||
#define CPU_PART_CORTEX_A57 0xD07 | #define CPU_PART_CORTEX_A57 0xD07 | ||||
#define CPU_PART_CORTEX_A72 0xD08 | #define CPU_PART_CORTEX_A72 0xD08 | ||||
#define CPU_PART_CORTEX_A73 0xD09 | #define CPU_PART_CORTEX_A73 0xD09 | ||||
#define CPU_PART_CORTEX_A75 0xD0A | #define CPU_PART_CORTEX_A75 0xD0A | ||||
#define CPU_REV_THUNDER_1_0 0x00 | #define CPU_REV_THUNDER_1_0 0x00 | ||||
#define CPU_REV_THUNDER_1_1 0x01 | #define CPU_REV_THUNDER_1_1 0x01 | ||||
#define CPU_REV_THUNDERX2_0 0x00 | |||||
andrew: Can you split this out into a new review, and include the needed updates to identcpu.c? I have… | |||||
#define CPU_IMPL(midr) (((midr) >> 24) & 0xff) | #define CPU_IMPL(midr) (((midr) >> 24) & 0xff) | ||||
#define CPU_PART(midr) (((midr) >> 4) & 0xfff) | #define CPU_PART(midr) (((midr) >> 4) & 0xfff) | ||||
#define CPU_VAR(midr) (((midr) >> 20) & 0xf) | #define CPU_VAR(midr) (((midr) >> 20) & 0xf) | ||||
#define CPU_REV(midr) (((midr) >> 0) & 0xf) | #define CPU_REV(midr) (((midr) >> 0) & 0xf) | ||||
#define CPU_IMPL_TO_MIDR(val) (((val) & 0xff) << 24) | #define CPU_IMPL_TO_MIDR(val) (((val) & 0xff) << 24) | ||||
#define CPU_PART_TO_MIDR(val) (((val) & 0xfff) << 4) | #define CPU_PART_TO_MIDR(val) (((val) & 0xfff) << 4) | ||||
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Can you split this out into a new review, and include the needed updates to identcpu.c? I have moved some of these macros around so you'll also need to rebase.