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sys/dev/ixl/i40e_nvm.c
/****************************************************************************** | /****************************************************************************** | ||||
Copyright (c) 2013-2015, Intel Corporation | Copyright (c) 2013-2017, Intel Corporation | ||||
All rights reserved. | All rights reserved. | ||||
Redistribution and use in source and binary forms, with or without | Redistribution and use in source and binary forms, with or without | ||||
modification, are permitted provided that the following conditions are met: | modification, are permitted provided that the following conditions are met: | ||||
1. Redistributions of source code must retain the above copyright notice, | 1. Redistributions of source code must retain the above copyright notice, | ||||
this list of conditions and the following disclaimer. | this list of conditions and the following disclaimer. | ||||
Show All 17 Lines | /****************************************************************************** | ||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ||||
POSSIBILITY OF SUCH DAMAGE. | POSSIBILITY OF SUCH DAMAGE. | ||||
******************************************************************************/ | ******************************************************************************/ | ||||
/*$FreeBSD$*/ | /*$FreeBSD$*/ | ||||
#include "i40e_prototype.h" | #include "i40e_prototype.h" | ||||
enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset, | |||||
u16 *data); | |||||
enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset, | |||||
u16 *data); | |||||
enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset, | |||||
u16 *words, u16 *data); | |||||
enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset, | |||||
u16 *words, u16 *data); | |||||
enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer, | |||||
u32 offset, u16 words, void *data, | |||||
bool last_command); | |||||
/** | /** | ||||
* i40e_init_nvm_ops - Initialize NVM function pointers | * i40e_init_nvm_ops - Initialize NVM function pointers | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* | * | ||||
* Setup the function pointers and the NVM info structure. Should be called | * Setup the function pointers and the NVM info structure. Should be called | ||||
* once per NVM initialization, e.g. inside the i40e_init_shared_code(). | * once per NVM initialization, e.g. inside the i40e_init_shared_code(). | ||||
* Please notice that the NVM term is used here (& in all methods covered | * Please notice that the NVM term is used here (& in all methods covered | ||||
* in this file) as an equivalent of the FLASH part mapped into the SR. | * in this file) as an equivalent of the FLASH part mapped into the SR. | ||||
▲ Show 20 Lines • Show All 146 Lines • ▼ Show 20 Lines | for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) { | ||||
i40e_usec_delay(5); | i40e_usec_delay(5); | ||||
} | } | ||||
if (ret_code == I40E_ERR_TIMEOUT) | if (ret_code == I40E_ERR_TIMEOUT) | ||||
i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set"); | i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set"); | ||||
return ret_code; | return ret_code; | ||||
} | } | ||||
/** | /** | ||||
* i40e_read_nvm_word - Reads nvm word and acquire lock if necessary | |||||
* @hw: pointer to the HW structure | |||||
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) | |||||
* @data: word read from the Shadow RAM | |||||
* | |||||
* Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. | |||||
**/ | |||||
enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset, | |||||
u16 *data) | |||||
{ | |||||
enum i40e_status_code ret_code = I40E_SUCCESS; | |||||
ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); | |||||
if (!ret_code) { | |||||
if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) { | |||||
ret_code = i40e_read_nvm_word_aq(hw, offset, data); | |||||
} else { | |||||
ret_code = i40e_read_nvm_word_srctl(hw, offset, data); | |||||
} | |||||
i40e_release_nvm(hw); | |||||
} | |||||
return ret_code; | |||||
} | |||||
/** | |||||
* __i40e_read_nvm_word - Reads nvm word, assumes caller does the locking | |||||
* @hw: pointer to the HW structure | |||||
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) | |||||
* @data: word read from the Shadow RAM | |||||
* | |||||
* Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. | |||||
**/ | |||||
enum i40e_status_code __i40e_read_nvm_word(struct i40e_hw *hw, | |||||
u16 offset, | |||||
u16 *data) | |||||
{ | |||||
enum i40e_status_code ret_code = I40E_SUCCESS; | |||||
if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) | |||||
ret_code = i40e_read_nvm_word_aq(hw, offset, data); | |||||
else | |||||
ret_code = i40e_read_nvm_word_srctl(hw, offset, data); | |||||
return ret_code; | |||||
} | |||||
/** | |||||
* i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register | * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) | * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) | ||||
* @data: word read from the Shadow RAM | * @data: word read from the Shadow RAM | ||||
* | * | ||||
* Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. | * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset, | enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset, | ||||
Show All 34 Lines | i40e_debug(hw, I40E_DEBUG_NVM, | ||||
"NVM read error: Couldn't access Shadow RAM address: 0x%x\n", | "NVM read error: Couldn't access Shadow RAM address: 0x%x\n", | ||||
offset); | offset); | ||||
read_nvm_exit: | read_nvm_exit: | ||||
return ret_code; | return ret_code; | ||||
} | } | ||||
/** | /** | ||||
* i40e_read_nvm_aq - Read Shadow RAM. | |||||
* @hw: pointer to the HW structure. | |||||
* @module_pointer: module pointer location in words from the NVM beginning | |||||
* @offset: offset in words from module start | |||||
* @words: number of words to write | |||||
* @data: buffer with words to write to the Shadow RAM | |||||
* @last_command: tells the AdminQ that this is the last command | |||||
* | |||||
* Writes a 16 bit words buffer to the Shadow RAM using the admin command. | |||||
**/ | |||||
static enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, | |||||
u8 module_pointer, u32 offset, | |||||
u16 words, void *data, | |||||
bool last_command) | |||||
{ | |||||
enum i40e_status_code ret_code = I40E_ERR_NVM; | |||||
struct i40e_asq_cmd_details cmd_details; | |||||
DEBUGFUNC("i40e_read_nvm_aq"); | |||||
memset(&cmd_details, 0, sizeof(cmd_details)); | |||||
cmd_details.wb_desc = &hw->nvm_wb_desc; | |||||
/* Here we are checking the SR limit only for the flat memory model. | |||||
* We cannot do it for the module-based model, as we did not acquire | |||||
* the NVM resource yet (we cannot get the module pointer value). | |||||
* Firmware will check the module-based model. | |||||
*/ | |||||
if ((offset + words) > hw->nvm.sr_size) | |||||
i40e_debug(hw, I40E_DEBUG_NVM, | |||||
"NVM write error: offset %d beyond Shadow RAM limit %d\n", | |||||
(offset + words), hw->nvm.sr_size); | |||||
else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS) | |||||
/* We can write only up to 4KB (one sector), in one AQ write */ | |||||
i40e_debug(hw, I40E_DEBUG_NVM, | |||||
"NVM write fail error: tried to write %d words, limit is %d.\n", | |||||
words, I40E_SR_SECTOR_SIZE_IN_WORDS); | |||||
else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) | |||||
!= (offset / I40E_SR_SECTOR_SIZE_IN_WORDS)) | |||||
/* A single write cannot spread over two sectors */ | |||||
i40e_debug(hw, I40E_DEBUG_NVM, | |||||
"NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n", | |||||
offset, words); | |||||
else | |||||
ret_code = i40e_aq_read_nvm(hw, module_pointer, | |||||
2 * offset, /*bytes*/ | |||||
2 * words, /*bytes*/ | |||||
data, last_command, &cmd_details); | |||||
return ret_code; | |||||
} | |||||
/** | |||||
* i40e_read_nvm_word_aq - Reads Shadow RAM via AQ | * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) | * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) | ||||
* @data: word read from the Shadow RAM | * @data: word read from the Shadow RAM | ||||
* | * | ||||
* Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register. | * Reads one 16 bit word from the Shadow RAM using the AdminQ | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset, | static enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset, | ||||
u16 *data) | u16 *data) | ||||
{ | { | ||||
enum i40e_status_code ret_code = I40E_ERR_TIMEOUT; | enum i40e_status_code ret_code = I40E_ERR_TIMEOUT; | ||||
DEBUGFUNC("i40e_read_nvm_word_aq"); | DEBUGFUNC("i40e_read_nvm_word_aq"); | ||||
ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, TRUE); | ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, TRUE); | ||||
*data = LE16_TO_CPU(*(__le16 *)data); | *data = LE16_TO_CPU(*(__le16 *)data); | ||||
return ret_code; | return ret_code; | ||||
} | } | ||||
/** | /** | ||||
* __i40e_read_nvm_buffer - Reads nvm buffer, caller must acquire lock | * __i40e_read_nvm_word - Reads NVM word, assumes caller does the locking | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). | * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) | ||||
* @words: (in) number of words to read; (out) number of words actually read | * @data: word read from the Shadow RAM | ||||
* @data: words read from the Shadow RAM | |||||
* | * | ||||
* Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() | * Reads one 16 bit word from the Shadow RAM. | ||||
* method. The buffer read is preceded by the NVM ownership take | * | ||||
* and followed by the release. | * Do not use this function except in cases where the nvm lock is already | ||||
* taken via i40e_acquire_nvm(). | |||||
**/ | **/ | ||||
enum i40e_status_code __i40e_read_nvm_buffer(struct i40e_hw *hw, | enum i40e_status_code __i40e_read_nvm_word(struct i40e_hw *hw, | ||||
u16 offset, | u16 offset, | ||||
u16 *words, u16 *data) | u16 *data) | ||||
{ | { | ||||
enum i40e_status_code ret_code = I40E_SUCCESS; | |||||
if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) | if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) | ||||
ret_code = i40e_read_nvm_buffer_aq(hw, offset, words, data); | return i40e_read_nvm_word_aq(hw, offset, data); | ||||
else | |||||
ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data); | return i40e_read_nvm_word_srctl(hw, offset, data); | ||||
return ret_code; | |||||
} | } | ||||
/** | /** | ||||
* i40e_read_nvm_buffer - Reads Shadow RAM buffer and acuire lock if necessary | * i40e_read_nvm_word - Reads NVM word, acquires lock if necessary | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). | * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) | ||||
* @words: (in) number of words to read; (out) number of words actually read | * @data: word read from the Shadow RAM | ||||
* @data: words read from the Shadow RAM | |||||
* | * | ||||
* Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() | * Reads one 16 bit word from the Shadow RAM. | ||||
* method. The buffer read is preceded by the NVM ownership take | |||||
* and followed by the release. | |||||
**/ | **/ | ||||
enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset, | enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset, | ||||
u16 *words, u16 *data) | u16 *data) | ||||
{ | { | ||||
enum i40e_status_code ret_code = I40E_SUCCESS; | enum i40e_status_code ret_code = I40E_SUCCESS; | ||||
if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) { | if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK) | ||||
ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); | ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); | ||||
if (!ret_code) { | |||||
ret_code = i40e_read_nvm_buffer_aq(hw, offset, words, | if (ret_code) | ||||
data); | return ret_code; | ||||
ret_code = __i40e_read_nvm_word(hw, offset, data); | |||||
if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK) | |||||
i40e_release_nvm(hw); | i40e_release_nvm(hw); | ||||
} | |||||
} else { | |||||
ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data); | |||||
} | |||||
return ret_code; | return ret_code; | ||||
} | } | ||||
/** | /** | ||||
* i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register | * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). | * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). | ||||
* @words: (in) number of words to read; (out) number of words actually read | * @words: (in) number of words to read; (out) number of words actually read | ||||
* @data: words read from the Shadow RAM | * @data: words read from the Shadow RAM | ||||
* | * | ||||
* Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() | * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() | ||||
* method. The buffer read is preceded by the NVM ownership take | * method. The buffer read is preceded by the NVM ownership take | ||||
* and followed by the release. | * and followed by the release. | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset, | static enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset, | ||||
u16 *words, u16 *data) | u16 *words, u16 *data) | ||||
{ | { | ||||
enum i40e_status_code ret_code = I40E_SUCCESS; | enum i40e_status_code ret_code = I40E_SUCCESS; | ||||
u16 index, word; | u16 index, word; | ||||
DEBUGFUNC("i40e_read_nvm_buffer_srctl"); | DEBUGFUNC("i40e_read_nvm_buffer_srctl"); | ||||
/* Loop through the selected region */ | /* Loop through the selected region */ | ||||
for (word = 0; word < *words; word++) { | for (word = 0; word < *words; word++) { | ||||
Show All 15 Lines | |||||
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). | * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). | ||||
* @words: (in) number of words to read; (out) number of words actually read | * @words: (in) number of words to read; (out) number of words actually read | ||||
* @data: words read from the Shadow RAM | * @data: words read from the Shadow RAM | ||||
* | * | ||||
* Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq() | * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq() | ||||
* method. The buffer read is preceded by the NVM ownership take | * method. The buffer read is preceded by the NVM ownership take | ||||
* and followed by the release. | * and followed by the release. | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset, | static enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset, | ||||
u16 *words, u16 *data) | u16 *words, u16 *data) | ||||
{ | { | ||||
enum i40e_status_code ret_code; | enum i40e_status_code ret_code; | ||||
u16 read_size = *words; | u16 read_size = *words; | ||||
bool last_cmd = FALSE; | bool last_cmd = FALSE; | ||||
u16 words_read = 0; | u16 words_read = 0; | ||||
u16 i = 0; | u16 i = 0; | ||||
DEBUGFUNC("i40e_read_nvm_buffer_aq"); | DEBUGFUNC("i40e_read_nvm_buffer_aq"); | ||||
Show All 31 Lines | for (i = 0; i < *words; i++) | ||||
data[i] = LE16_TO_CPU(((__le16 *)data)[i]); | data[i] = LE16_TO_CPU(((__le16 *)data)[i]); | ||||
read_nvm_buffer_aq_exit: | read_nvm_buffer_aq_exit: | ||||
*words = words_read; | *words = words_read; | ||||
return ret_code; | return ret_code; | ||||
} | } | ||||
/** | /** | ||||
* i40e_read_nvm_aq - Read Shadow RAM. | * __i40e_read_nvm_buffer - Reads NVM buffer, caller must acquire lock | ||||
* @hw: pointer to the HW structure. | * @hw: pointer to the HW structure | ||||
* @module_pointer: module pointer location in words from the NVM beginning | * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). | ||||
* @offset: offset in words from module start | * @words: (in) number of words to read; (out) number of words actually read | ||||
* @words: number of words to write | * @data: words read from the Shadow RAM | ||||
* @data: buffer with words to write to the Shadow RAM | |||||
* @last_command: tells the AdminQ that this is the last command | |||||
* | * | ||||
* Writes a 16 bit words buffer to the Shadow RAM using the admin command. | * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() | ||||
* method. | |||||
**/ | **/ | ||||
enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer, | enum i40e_status_code __i40e_read_nvm_buffer(struct i40e_hw *hw, | ||||
u32 offset, u16 words, void *data, | u16 offset, | ||||
bool last_command) | u16 *words, u16 *data) | ||||
{ | { | ||||
enum i40e_status_code ret_code = I40E_ERR_NVM; | if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) | ||||
struct i40e_asq_cmd_details cmd_details; | return i40e_read_nvm_buffer_aq(hw, offset, words, data); | ||||
DEBUGFUNC("i40e_read_nvm_aq"); | return i40e_read_nvm_buffer_srctl(hw, offset, words, data); | ||||
} | |||||
memset(&cmd_details, 0, sizeof(cmd_details)); | /** | ||||
cmd_details.wb_desc = &hw->nvm_wb_desc; | * i40e_read_nvm_buffer - Reads Shadow RAM buffer and acquire lock if necessary | ||||
* @hw: pointer to the HW structure | |||||
* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF). | |||||
* @words: (in) number of words to read; (out) number of words actually read | |||||
* @data: words read from the Shadow RAM | |||||
* | |||||
* Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd() | |||||
* method. The buffer read is preceded by the NVM ownership take | |||||
* and followed by the release. | |||||
**/ | |||||
enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset, | |||||
u16 *words, u16 *data) | |||||
{ | |||||
enum i40e_status_code ret_code = I40E_SUCCESS; | |||||
/* Here we are checking the SR limit only for the flat memory model. | if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) { | ||||
* We cannot do it for the module-based model, as we did not acquire | ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); | ||||
* the NVM resource yet (we cannot get the module pointer value). | if (!ret_code) { | ||||
* Firmware will check the module-based model. | ret_code = i40e_read_nvm_buffer_aq(hw, offset, words, | ||||
*/ | data); | ||||
if ((offset + words) > hw->nvm.sr_size) | i40e_release_nvm(hw); | ||||
i40e_debug(hw, I40E_DEBUG_NVM, | } | ||||
"NVM write error: offset %d beyond Shadow RAM limit %d\n", | } else { | ||||
(offset + words), hw->nvm.sr_size); | ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data); | ||||
else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS) | } | ||||
/* We can write only up to 4KB (one sector), in one AQ write */ | |||||
i40e_debug(hw, I40E_DEBUG_NVM, | |||||
"NVM write fail error: tried to write %d words, limit is %d.\n", | |||||
words, I40E_SR_SECTOR_SIZE_IN_WORDS); | |||||
else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) | |||||
!= (offset / I40E_SR_SECTOR_SIZE_IN_WORDS)) | |||||
/* A single write cannot spread over two sectors */ | |||||
i40e_debug(hw, I40E_DEBUG_NVM, | |||||
"NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n", | |||||
offset, words); | |||||
else | |||||
ret_code = i40e_aq_read_nvm(hw, module_pointer, | |||||
2 * offset, /*bytes*/ | |||||
2 * words, /*bytes*/ | |||||
data, last_command, &cmd_details); | |||||
return ret_code; | return ret_code; | ||||
} | } | ||||
/** | /** | ||||
* i40e_write_nvm_aq - Writes Shadow RAM. | * i40e_write_nvm_aq - Writes Shadow RAM. | ||||
* @hw: pointer to the HW structure. | * @hw: pointer to the HW structure. | ||||
* @module_pointer: module pointer location in words from the NVM beginning | * @module_pointer: module pointer location in words from the NVM beginning | ||||
* @offset: offset in words from module start | * @offset: offset in words from module start | ||||
* @words: number of words to write | * @words: number of words to write | ||||
* @data: buffer with words to write to the Shadow RAM | * @data: buffer with words to write to the Shadow RAM | ||||
* @last_command: tells the AdminQ that this is the last command | * @last_command: tells the AdminQ that this is the last command | ||||
Show All 25 Lines | enum i40e_status_code i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer, | ||||
else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) | else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) | ||||
!= (offset / I40E_SR_SECTOR_SIZE_IN_WORDS)) | != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS)) | ||||
/* A single write cannot spread over two sectors */ | /* A single write cannot spread over two sectors */ | ||||
DEBUGOUT("NVM write error: cannot spread over two sectors in a single write.\n"); | DEBUGOUT("NVM write error: cannot spread over two sectors in a single write.\n"); | ||||
else | else | ||||
ret_code = i40e_aq_update_nvm(hw, module_pointer, | ret_code = i40e_aq_update_nvm(hw, module_pointer, | ||||
2 * offset, /*bytes*/ | 2 * offset, /*bytes*/ | ||||
2 * words, /*bytes*/ | 2 * words, /*bytes*/ | ||||
data, last_command, &cmd_details); | data, last_command, 0, | ||||
&cmd_details); | |||||
return ret_code; | return ret_code; | ||||
} | } | ||||
/** | /** | ||||
* __i40e_write_nvm_word - Writes Shadow RAM word | * __i40e_write_nvm_word - Writes Shadow RAM word | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @offset: offset of the Shadow RAM word to write | * @offset: offset of the Shadow RAM word to write | ||||
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_calc_nvm_checksum(struct i40e_hw *hw, u16 *checksum) | ||||
ret_code = i40e_allocate_virt_mem(hw, &vmem, | ret_code = i40e_allocate_virt_mem(hw, &vmem, | ||||
I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16)); | I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16)); | ||||
if (ret_code) | if (ret_code) | ||||
goto i40e_calc_nvm_checksum_exit; | goto i40e_calc_nvm_checksum_exit; | ||||
data = (u16 *)vmem.va; | data = (u16 *)vmem.va; | ||||
/* read pointer to VPD area */ | /* read pointer to VPD area */ | ||||
ret_code = __i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, | ret_code = __i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module); | ||||
&vpd_module); | |||||
if (ret_code != I40E_SUCCESS) { | if (ret_code != I40E_SUCCESS) { | ||||
ret_code = I40E_ERR_NVM_CHECKSUM; | ret_code = I40E_ERR_NVM_CHECKSUM; | ||||
goto i40e_calc_nvm_checksum_exit; | goto i40e_calc_nvm_checksum_exit; | ||||
} | } | ||||
/* read pointer to PCIe Alt Auto-load module */ | /* read pointer to PCIe Alt Auto-load module */ | ||||
ret_code = __i40e_read_nvm_word(hw, | ret_code = __i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR, | ||||
I40E_SR_PCIE_ALT_AUTO_LOAD_PTR, | |||||
&pcie_alt_module); | &pcie_alt_module); | ||||
if (ret_code != I40E_SUCCESS) { | if (ret_code != I40E_SUCCESS) { | ||||
ret_code = I40E_ERR_NVM_CHECKSUM; | ret_code = I40E_ERR_NVM_CHECKSUM; | ||||
goto i40e_calc_nvm_checksum_exit; | goto i40e_calc_nvm_checksum_exit; | ||||
} | } | ||||
/* Calculate SW checksum that covers the whole 64kB shadow RAM | /* Calculate SW checksum that covers the whole 64kB shadow RAM | ||||
* except the VPD and PCIe ALT Auto-load modules | * except the VPD and PCIe ALT Auto-load modules | ||||
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_validate_nvm_checksum(struct i40e_hw *hw, | ||||
u16 *checksum) | u16 *checksum) | ||||
{ | { | ||||
enum i40e_status_code ret_code = I40E_SUCCESS; | enum i40e_status_code ret_code = I40E_SUCCESS; | ||||
u16 checksum_sr = 0; | u16 checksum_sr = 0; | ||||
u16 checksum_local = 0; | u16 checksum_local = 0; | ||||
DEBUGFUNC("i40e_validate_nvm_checksum"); | DEBUGFUNC("i40e_validate_nvm_checksum"); | ||||
if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) | /* We must acquire the NVM lock in order to correctly synchronize the | ||||
* NVM accesses across multiple PFs. Without doing so it is possible | |||||
* for one of the PFs to read invalid data potentially indicating that | |||||
* the checksum is invalid. | |||||
*/ | |||||
ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); | ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ); | ||||
if (!ret_code) { | if (ret_code) | ||||
return ret_code; | |||||
ret_code = i40e_calc_nvm_checksum(hw, &checksum_local); | ret_code = i40e_calc_nvm_checksum(hw, &checksum_local); | ||||
if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) | __i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr); | ||||
i40e_release_nvm(hw); | i40e_release_nvm(hw); | ||||
if (ret_code != I40E_SUCCESS) | if (ret_code) | ||||
goto i40e_validate_nvm_checksum_exit; | return ret_code; | ||||
} else { | |||||
goto i40e_validate_nvm_checksum_exit; | |||||
} | |||||
i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr); | |||||
/* Verify read checksum from EEPROM is the same as | /* Verify read checksum from EEPROM is the same as | ||||
* calculated checksum | * calculated checksum | ||||
*/ | */ | ||||
if (checksum_local != checksum_sr) | if (checksum_local != checksum_sr) | ||||
ret_code = I40E_ERR_NVM_CHECKSUM; | ret_code = I40E_ERR_NVM_CHECKSUM; | ||||
/* If the user cares, return the calculated checksum */ | /* If the user cares, return the calculated checksum */ | ||||
if (checksum) | if (checksum) | ||||
*checksum = checksum_local; | *checksum = checksum_local; | ||||
i40e_validate_nvm_checksum_exit: | |||||
return ret_code; | return ret_code; | ||||
} | } | ||||
static enum i40e_status_code i40e_nvmupd_state_init(struct i40e_hw *hw, | static enum i40e_status_code i40e_nvmupd_state_init(struct i40e_hw *hw, | ||||
struct i40e_nvm_access *cmd, | struct i40e_nvm_access *cmd, | ||||
u8 *bytes, int *perrno); | u8 *bytes, int *perrno); | ||||
static enum i40e_status_code i40e_nvmupd_state_reading(struct i40e_hw *hw, | static enum i40e_status_code i40e_nvmupd_state_reading(struct i40e_hw *hw, | ||||
struct i40e_nvm_access *cmd, | struct i40e_nvm_access *cmd, | ||||
Show All 14 Lines | static enum i40e_status_code i40e_nvmupd_nvm_read(struct i40e_hw *hw, | ||||
struct i40e_nvm_access *cmd, | struct i40e_nvm_access *cmd, | ||||
u8 *bytes, int *perrno); | u8 *bytes, int *perrno); | ||||
static enum i40e_status_code i40e_nvmupd_exec_aq(struct i40e_hw *hw, | static enum i40e_status_code i40e_nvmupd_exec_aq(struct i40e_hw *hw, | ||||
struct i40e_nvm_access *cmd, | struct i40e_nvm_access *cmd, | ||||
u8 *bytes, int *perrno); | u8 *bytes, int *perrno); | ||||
static enum i40e_status_code i40e_nvmupd_get_aq_result(struct i40e_hw *hw, | static enum i40e_status_code i40e_nvmupd_get_aq_result(struct i40e_hw *hw, | ||||
struct i40e_nvm_access *cmd, | struct i40e_nvm_access *cmd, | ||||
u8 *bytes, int *perrno); | u8 *bytes, int *perrno); | ||||
static enum i40e_status_code i40e_nvmupd_get_aq_event(struct i40e_hw *hw, | |||||
struct i40e_nvm_access *cmd, | |||||
u8 *bytes, int *perrno); | |||||
static INLINE u8 i40e_nvmupd_get_module(u32 val) | static INLINE u8 i40e_nvmupd_get_module(u32 val) | ||||
{ | { | ||||
return (u8)(val & I40E_NVM_MOD_PNT_MASK); | return (u8)(val & I40E_NVM_MOD_PNT_MASK); | ||||
} | } | ||||
static INLINE u8 i40e_nvmupd_get_transaction(u32 val) | static INLINE u8 i40e_nvmupd_get_transaction(u32 val) | ||||
{ | { | ||||
return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT); | return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT); | ||||
} | } | ||||
static INLINE u8 i40e_nvmupd_get_preservation_flags(u32 val) | |||||
{ | |||||
return (u8)((val & I40E_NVM_PRESERVATION_FLAGS_MASK) >> | |||||
I40E_NVM_PRESERVATION_FLAGS_SHIFT); | |||||
} | |||||
static const char *i40e_nvm_update_state_str[] = { | static const char *i40e_nvm_update_state_str[] = { | ||||
"I40E_NVMUPD_INVALID", | "I40E_NVMUPD_INVALID", | ||||
"I40E_NVMUPD_READ_CON", | "I40E_NVMUPD_READ_CON", | ||||
"I40E_NVMUPD_READ_SNT", | "I40E_NVMUPD_READ_SNT", | ||||
"I40E_NVMUPD_READ_LCB", | "I40E_NVMUPD_READ_LCB", | ||||
"I40E_NVMUPD_READ_SA", | "I40E_NVMUPD_READ_SA", | ||||
"I40E_NVMUPD_WRITE_ERA", | "I40E_NVMUPD_WRITE_ERA", | ||||
"I40E_NVMUPD_WRITE_CON", | "I40E_NVMUPD_WRITE_CON", | ||||
"I40E_NVMUPD_WRITE_SNT", | "I40E_NVMUPD_WRITE_SNT", | ||||
"I40E_NVMUPD_WRITE_LCB", | "I40E_NVMUPD_WRITE_LCB", | ||||
"I40E_NVMUPD_WRITE_SA", | "I40E_NVMUPD_WRITE_SA", | ||||
"I40E_NVMUPD_CSUM_CON", | "I40E_NVMUPD_CSUM_CON", | ||||
"I40E_NVMUPD_CSUM_SA", | "I40E_NVMUPD_CSUM_SA", | ||||
"I40E_NVMUPD_CSUM_LCB", | "I40E_NVMUPD_CSUM_LCB", | ||||
"I40E_NVMUPD_STATUS", | "I40E_NVMUPD_STATUS", | ||||
"I40E_NVMUPD_EXEC_AQ", | "I40E_NVMUPD_EXEC_AQ", | ||||
"I40E_NVMUPD_GET_AQ_RESULT", | "I40E_NVMUPD_GET_AQ_RESULT", | ||||
"I40E_NVMUPD_GET_AQ_EVENT", | |||||
}; | }; | ||||
/** | /** | ||||
* i40e_nvmupd_command - Process an NVM update command | * i40e_nvmupd_command - Process an NVM update command | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* @cmd: pointer to nvm update command | * @cmd: pointer to nvm update command | ||||
* @bytes: pointer to the data buffer | * @bytes: pointer to the data buffer | ||||
* @perrno: pointer to return error code | * @perrno: pointer to return error code | ||||
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_nvmupd_command(struct i40e_hw *hw, | ||||
/* Clear status even it is not read and log */ | /* Clear status even it is not read and log */ | ||||
if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) { | if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) { | ||||
i40e_debug(hw, I40E_DEBUG_NVM, | i40e_debug(hw, I40E_DEBUG_NVM, | ||||
"Clearing I40E_NVMUPD_STATE_ERROR state without reading\n"); | "Clearing I40E_NVMUPD_STATE_ERROR state without reading\n"); | ||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; | hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; | ||||
} | } | ||||
/* Acquire lock to prevent race condition where adminq_task | |||||
* can execute after i40e_nvmupd_nvm_read/write but before state | |||||
* variables (nvm_wait_opcode, nvm_release_on_done) are updated. | |||||
* | |||||
* During NVMUpdate, it is observed that lock could be held for | |||||
* ~5ms for most commands. However lock is held for ~60ms for | |||||
* NVMUPD_CSUM_LCB command. | |||||
*/ | |||||
i40e_acquire_spinlock(&hw->aq.arq_spinlock); | |||||
switch (hw->nvmupd_state) { | switch (hw->nvmupd_state) { | ||||
case I40E_NVMUPD_STATE_INIT: | case I40E_NVMUPD_STATE_INIT: | ||||
status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno); | status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno); | ||||
break; | break; | ||||
case I40E_NVMUPD_STATE_READING: | case I40E_NVMUPD_STATE_READING: | ||||
status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno); | status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno); | ||||
break; | break; | ||||
case I40E_NVMUPD_STATE_WRITING: | case I40E_NVMUPD_STATE_WRITING: | ||||
status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno); | status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno); | ||||
break; | break; | ||||
case I40E_NVMUPD_STATE_INIT_WAIT: | case I40E_NVMUPD_STATE_INIT_WAIT: | ||||
case I40E_NVMUPD_STATE_WRITE_WAIT: | case I40E_NVMUPD_STATE_WRITE_WAIT: | ||||
/* if we need to stop waiting for an event, clear | /* if we need to stop waiting for an event, clear | ||||
* the wait info and return before doing anything else | * the wait info and return before doing anything else | ||||
*/ | */ | ||||
if (cmd->offset == 0xffff) { | if (cmd->offset == 0xffff) { | ||||
i40e_nvmupd_check_wait_event(hw, hw->nvm_wait_opcode); | i40e_nvmupd_clear_wait_state(hw); | ||||
return I40E_SUCCESS; | status = I40E_SUCCESS; | ||||
break; | |||||
} | } | ||||
status = I40E_ERR_NOT_READY; | status = I40E_ERR_NOT_READY; | ||||
*perrno = -EBUSY; | *perrno = -EBUSY; | ||||
break; | break; | ||||
default: | default: | ||||
/* invalid state, should never happen */ | /* invalid state, should never happen */ | ||||
i40e_debug(hw, I40E_DEBUG_NVM, | i40e_debug(hw, I40E_DEBUG_NVM, | ||||
"NVMUPD: no such state %d\n", hw->nvmupd_state); | "NVMUPD: no such state %d\n", hw->nvmupd_state); | ||||
status = I40E_NOT_SUPPORTED; | status = I40E_NOT_SUPPORTED; | ||||
*perrno = -ESRCH; | *perrno = -ESRCH; | ||||
break; | break; | ||||
} | } | ||||
i40e_release_spinlock(&hw->aq.arq_spinlock); | |||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_nvmupd_state_init - Handle NVM update state Init | * i40e_nvmupd_state_init - Handle NVM update state Init | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* @cmd: pointer to nvm update command buffer | * @cmd: pointer to nvm update command buffer | ||||
* @bytes: pointer to the data buffer | * @bytes: pointer to the data buffer | ||||
▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines | static enum i40e_status_code i40e_nvmupd_state_init(struct i40e_hw *hw, | ||||
case I40E_NVMUPD_EXEC_AQ: | case I40E_NVMUPD_EXEC_AQ: | ||||
status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno); | status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno); | ||||
break; | break; | ||||
case I40E_NVMUPD_GET_AQ_RESULT: | case I40E_NVMUPD_GET_AQ_RESULT: | ||||
status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno); | status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno); | ||||
break; | break; | ||||
case I40E_NVMUPD_GET_AQ_EVENT: | |||||
status = i40e_nvmupd_get_aq_event(hw, cmd, bytes, perrno); | |||||
break; | |||||
default: | default: | ||||
i40e_debug(hw, I40E_DEBUG_NVM, | i40e_debug(hw, I40E_DEBUG_NVM, | ||||
"NVMUPD: bad cmd %s in init state\n", | "NVMUPD: bad cmd %s in init state\n", | ||||
i40e_nvm_update_state_str[upd_cmd]); | i40e_nvm_update_state_str[upd_cmd]); | ||||
status = I40E_ERR_NVM; | status = I40E_ERR_NVM; | ||||
*perrno = -ESRCH; | *perrno = -ESRCH; | ||||
break; | break; | ||||
} | } | ||||
▲ Show 20 Lines • Show All 162 Lines • ▼ Show 20 Lines | if (gtime >= hw->nvm.hw_semaphore_timeout) { | ||||
} | } | ||||
} | } | ||||
} | } | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_nvmupd_check_wait_event - handle NVM update operation events | * i40e_nvmupd_clear_wait_state - clear wait state on hw | ||||
* @hw: pointer to the hardware structure | * @hw: pointer to the hardware structure | ||||
* @opcode: the event that just happened | |||||
**/ | **/ | ||||
void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode) | void i40e_nvmupd_clear_wait_state(struct i40e_hw *hw) | ||||
{ | { | ||||
if (opcode == hw->nvm_wait_opcode) { | |||||
i40e_debug(hw, I40E_DEBUG_NVM, | i40e_debug(hw, I40E_DEBUG_NVM, | ||||
"NVMUPD: clearing wait on opcode 0x%04x\n", opcode); | "NVMUPD: clearing wait on opcode 0x%04x\n", | ||||
hw->nvm_wait_opcode); | |||||
if (hw->nvm_release_on_done) { | if (hw->nvm_release_on_done) { | ||||
i40e_release_nvm(hw); | i40e_release_nvm(hw); | ||||
hw->nvm_release_on_done = FALSE; | hw->nvm_release_on_done = FALSE; | ||||
} | } | ||||
hw->nvm_wait_opcode = 0; | hw->nvm_wait_opcode = 0; | ||||
if (hw->aq.arq_last_status) { | if (hw->aq.arq_last_status) { | ||||
hw->nvmupd_state = I40E_NVMUPD_STATE_ERROR; | hw->nvmupd_state = I40E_NVMUPD_STATE_ERROR; | ||||
return; | return; | ||||
} | } | ||||
switch (hw->nvmupd_state) { | switch (hw->nvmupd_state) { | ||||
case I40E_NVMUPD_STATE_INIT_WAIT: | case I40E_NVMUPD_STATE_INIT_WAIT: | ||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; | hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; | ||||
break; | break; | ||||
case I40E_NVMUPD_STATE_WRITE_WAIT: | case I40E_NVMUPD_STATE_WRITE_WAIT: | ||||
hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING; | hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING; | ||||
break; | break; | ||||
default: | default: | ||||
break; | break; | ||||
} | } | ||||
} | } | ||||
/** | |||||
* i40e_nvmupd_check_wait_event - handle NVM update operation events | |||||
* @hw: pointer to the hardware structure | |||||
* @opcode: the event that just happened | |||||
* @desc: AdminQ descriptor | |||||
**/ | |||||
void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode, | |||||
struct i40e_aq_desc *desc) | |||||
{ | |||||
u32 aq_desc_len = sizeof(struct i40e_aq_desc); | |||||
if (opcode == hw->nvm_wait_opcode) { | |||||
i40e_memcpy(&hw->nvm_aq_event_desc, desc, | |||||
aq_desc_len, I40E_NONDMA_TO_NONDMA); | |||||
i40e_nvmupd_clear_wait_state(hw); | |||||
} | } | ||||
} | |||||
/** | /** | ||||
* i40e_nvmupd_validate_command - Validate given command | * i40e_nvmupd_validate_command - Validate given command | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* @cmd: pointer to nvm update command buffer | * @cmd: pointer to nvm update command buffer | ||||
* @perrno: pointer to return error code | * @perrno: pointer to return error code | ||||
* | * | ||||
* Return one of the valid command types or I40E_NVMUPD_INVALID | * Return one of the valid command types or I40E_NVMUPD_INVALID | ||||
Show All 39 Lines | case I40E_NVM_SA: | ||||
upd_cmd = I40E_NVMUPD_READ_SA; | upd_cmd = I40E_NVMUPD_READ_SA; | ||||
break; | break; | ||||
case I40E_NVM_EXEC: | case I40E_NVM_EXEC: | ||||
if (module == 0xf) | if (module == 0xf) | ||||
upd_cmd = I40E_NVMUPD_STATUS; | upd_cmd = I40E_NVMUPD_STATUS; | ||||
else if (module == 0) | else if (module == 0) | ||||
upd_cmd = I40E_NVMUPD_GET_AQ_RESULT; | upd_cmd = I40E_NVMUPD_GET_AQ_RESULT; | ||||
break; | break; | ||||
case I40E_NVM_AQE: | |||||
upd_cmd = I40E_NVMUPD_GET_AQ_EVENT; | |||||
break; | |||||
} | } | ||||
break; | break; | ||||
case I40E_NVM_WRITE: | case I40E_NVM_WRITE: | ||||
switch (transaction) { | switch (transaction) { | ||||
case I40E_NVM_CON: | case I40E_NVM_CON: | ||||
upd_cmd = I40E_NVMUPD_WRITE_CON; | upd_cmd = I40E_NVMUPD_WRITE_CON; | ||||
break; | break; | ||||
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines | static enum i40e_status_code i40e_nvmupd_exec_aq(struct i40e_hw *hw, | ||||
enum i40e_status_code status; | enum i40e_status_code status; | ||||
struct i40e_aq_desc *aq_desc; | struct i40e_aq_desc *aq_desc; | ||||
u32 buff_size = 0; | u32 buff_size = 0; | ||||
u8 *buff = NULL; | u8 *buff = NULL; | ||||
u32 aq_desc_len; | u32 aq_desc_len; | ||||
u32 aq_data_len; | u32 aq_data_len; | ||||
i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__); | i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__); | ||||
if (cmd->offset == 0xffff) | |||||
return I40E_SUCCESS; | |||||
memset(&cmd_details, 0, sizeof(cmd_details)); | memset(&cmd_details, 0, sizeof(cmd_details)); | ||||
cmd_details.wb_desc = &hw->nvm_wb_desc; | cmd_details.wb_desc = &hw->nvm_wb_desc; | ||||
aq_desc_len = sizeof(struct i40e_aq_desc); | aq_desc_len = sizeof(struct i40e_aq_desc); | ||||
memset(&hw->nvm_wb_desc, 0, aq_desc_len); | memset(&hw->nvm_wb_desc, 0, aq_desc_len); | ||||
/* get the aq descriptor */ | /* get the aq descriptor */ | ||||
if (cmd->data_size < aq_desc_len) { | if (cmd->data_size < aq_desc_len) { | ||||
Show All 20 Lines | if (buff_size) { | ||||
if (hw->nvm_buff.va) { | if (hw->nvm_buff.va) { | ||||
buff = hw->nvm_buff.va; | buff = hw->nvm_buff.va; | ||||
i40e_memcpy(buff, &bytes[aq_desc_len], aq_data_len, | i40e_memcpy(buff, &bytes[aq_desc_len], aq_data_len, | ||||
I40E_NONDMA_TO_NONDMA); | I40E_NONDMA_TO_NONDMA); | ||||
} | } | ||||
} | } | ||||
if (cmd->offset) | |||||
memset(&hw->nvm_aq_event_desc, 0, aq_desc_len); | |||||
/* and away we go! */ | /* and away we go! */ | ||||
status = i40e_asq_send_command(hw, aq_desc, buff, | status = i40e_asq_send_command(hw, aq_desc, buff, | ||||
buff_size, &cmd_details); | buff_size, &cmd_details); | ||||
if (status) { | if (status) { | ||||
i40e_debug(hw, I40E_DEBUG_NVM, | i40e_debug(hw, I40E_DEBUG_NVM, | ||||
"i40e_nvmupd_exec_aq err %s aq_err %s\n", | "i40e_nvmupd_exec_aq err %s aq_err %s\n", | ||||
i40e_stat_str(hw, status), | i40e_stat_str(hw, status), | ||||
i40e_aq_str(hw, hw->aq.asq_last_status)); | i40e_aq_str(hw, hw->aq.asq_last_status)); | ||||
*perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); | *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); | ||||
return status; | |||||
} | } | ||||
/* should we wait for a followup event? */ | /* should we wait for a followup event? */ | ||||
if (cmd->offset) { | if (cmd->offset) { | ||||
hw->nvm_wait_opcode = cmd->offset; | hw->nvm_wait_opcode = cmd->offset; | ||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; | hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; | ||||
} | } | ||||
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines | i40e_debug(hw, I40E_DEBUG_NVM, "%s: databuf bytes %d to %d\n", | ||||
__func__, start_byte, start_byte + remainder); | __func__, start_byte, start_byte + remainder); | ||||
i40e_memcpy(bytes, buff, remainder, I40E_NONDMA_TO_NONDMA); | i40e_memcpy(bytes, buff, remainder, I40E_NONDMA_TO_NONDMA); | ||||
} | } | ||||
return I40E_SUCCESS; | return I40E_SUCCESS; | ||||
} | } | ||||
/** | /** | ||||
* i40e_nvmupd_get_aq_event - Get the Admin Queue event from previous exec_aq | |||||
* @hw: pointer to hardware structure | |||||
* @cmd: pointer to nvm update command buffer | |||||
* @bytes: pointer to the data buffer | |||||
* @perrno: pointer to return error code | |||||
* | |||||
* cmd structure contains identifiers and data buffer | |||||
**/ | |||||
static enum i40e_status_code i40e_nvmupd_get_aq_event(struct i40e_hw *hw, | |||||
struct i40e_nvm_access *cmd, | |||||
u8 *bytes, int *perrno) | |||||
{ | |||||
u32 aq_total_len; | |||||
u32 aq_desc_len; | |||||
i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__); | |||||
aq_desc_len = sizeof(struct i40e_aq_desc); | |||||
aq_total_len = aq_desc_len + LE16_TO_CPU(hw->nvm_aq_event_desc.datalen); | |||||
/* check copylength range */ | |||||
if (cmd->data_size > aq_total_len) { | |||||
i40e_debug(hw, I40E_DEBUG_NVM, | |||||
"%s: copy length %d too big, trimming to %d\n", | |||||
__func__, cmd->data_size, aq_total_len); | |||||
cmd->data_size = aq_total_len; | |||||
} | |||||
i40e_memcpy(bytes, &hw->nvm_aq_event_desc, cmd->data_size, | |||||
I40E_NONDMA_TO_NONDMA); | |||||
return I40E_SUCCESS; | |||||
} | |||||
/** | |||||
* i40e_nvmupd_nvm_read - Read NVM | * i40e_nvmupd_nvm_read - Read NVM | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* @cmd: pointer to nvm update command buffer | * @cmd: pointer to nvm update command buffer | ||||
* @bytes: pointer to the data buffer | * @bytes: pointer to the data buffer | ||||
* @perrno: pointer to return error code | * @perrno: pointer to return error code | ||||
* | * | ||||
* cmd structure contains identifiers and data buffer | * cmd structure contains identifiers and data buffer | ||||
**/ | **/ | ||||
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines | |||||
**/ | **/ | ||||
static enum i40e_status_code i40e_nvmupd_nvm_write(struct i40e_hw *hw, | static enum i40e_status_code i40e_nvmupd_nvm_write(struct i40e_hw *hw, | ||||
struct i40e_nvm_access *cmd, | struct i40e_nvm_access *cmd, | ||||
u8 *bytes, int *perrno) | u8 *bytes, int *perrno) | ||||
{ | { | ||||
enum i40e_status_code status = I40E_SUCCESS; | enum i40e_status_code status = I40E_SUCCESS; | ||||
struct i40e_asq_cmd_details cmd_details; | struct i40e_asq_cmd_details cmd_details; | ||||
u8 module, transaction; | u8 module, transaction; | ||||
u8 preservation_flags; | |||||
bool last; | bool last; | ||||
transaction = i40e_nvmupd_get_transaction(cmd->config); | transaction = i40e_nvmupd_get_transaction(cmd->config); | ||||
module = i40e_nvmupd_get_module(cmd->config); | module = i40e_nvmupd_get_module(cmd->config); | ||||
last = (transaction & I40E_NVM_LCB); | last = (transaction & I40E_NVM_LCB); | ||||
preservation_flags = i40e_nvmupd_get_preservation_flags(cmd->config); | |||||
memset(&cmd_details, 0, sizeof(cmd_details)); | memset(&cmd_details, 0, sizeof(cmd_details)); | ||||
cmd_details.wb_desc = &hw->nvm_wb_desc; | cmd_details.wb_desc = &hw->nvm_wb_desc; | ||||
status = i40e_aq_update_nvm(hw, module, cmd->offset, | status = i40e_aq_update_nvm(hw, module, cmd->offset, | ||||
(u16)cmd->data_size, bytes, last, | (u16)cmd->data_size, bytes, last, | ||||
&cmd_details); | preservation_flags, &cmd_details); | ||||
if (status) { | if (status) { | ||||
i40e_debug(hw, I40E_DEBUG_NVM, | i40e_debug(hw, I40E_DEBUG_NVM, | ||||
"i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n", | "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n", | ||||
module, cmd->offset, cmd->data_size); | module, cmd->offset, cmd->data_size); | ||||
i40e_debug(hw, I40E_DEBUG_NVM, | i40e_debug(hw, I40E_DEBUG_NVM, | ||||
"i40e_nvmupd_nvm_write status %d aq %d\n", | "i40e_nvmupd_nvm_write status %d aq %d\n", | ||||
status, hw->aq.asq_last_status); | status, hw->aq.asq_last_status); | ||||
*perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); | *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); | ||||
} | } | ||||
return status; | return status; | ||||
} | } |