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sys/dev/ixl/i40e_common.c
/****************************************************************************** | /****************************************************************************** | ||||
Copyright (c) 2013-2015, Intel Corporation | Copyright (c) 2013-2017, Intel Corporation | ||||
All rights reserved. | All rights reserved. | ||||
Redistribution and use in source and binary forms, with or without | Redistribution and use in source and binary forms, with or without | ||||
modification, are permitted provided that the following conditions are met: | modification, are permitted provided that the following conditions are met: | ||||
1. Redistributions of source code must retain the above copyright notice, | 1. Redistributions of source code must retain the above copyright notice, | ||||
this list of conditions and the following disclaimer. | this list of conditions and the following disclaimer. | ||||
Show All 18 Lines | /****************************************************************************** | ||||
POSSIBILITY OF SUCH DAMAGE. | POSSIBILITY OF SUCH DAMAGE. | ||||
******************************************************************************/ | ******************************************************************************/ | ||||
/*$FreeBSD$*/ | /*$FreeBSD$*/ | ||||
#include "i40e_type.h" | #include "i40e_type.h" | ||||
#include "i40e_adminq.h" | #include "i40e_adminq.h" | ||||
#include "i40e_prototype.h" | #include "i40e_prototype.h" | ||||
#include "i40e_virtchnl.h" | #include "virtchnl.h" | ||||
/** | /** | ||||
* i40e_set_mac_type - Sets MAC type | * i40e_set_mac_type - Sets MAC type | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* | * | ||||
* This function sets the mac type of the adapter based on the | * This function sets the mac type of the adapter based on the | ||||
* vendor ID and device ID stored in the hw structure. | * vendor ID and device ID stored in the hw structure. | ||||
Show All 16 Lines | if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { | ||||
case I40E_DEV_ID_10G_BASE_T: | case I40E_DEV_ID_10G_BASE_T: | ||||
case I40E_DEV_ID_10G_BASE_T4: | case I40E_DEV_ID_10G_BASE_T4: | ||||
case I40E_DEV_ID_20G_KR2: | case I40E_DEV_ID_20G_KR2: | ||||
case I40E_DEV_ID_20G_KR2_A: | case I40E_DEV_ID_20G_KR2_A: | ||||
case I40E_DEV_ID_25G_B: | case I40E_DEV_ID_25G_B: | ||||
case I40E_DEV_ID_25G_SFP28: | case I40E_DEV_ID_25G_SFP28: | ||||
hw->mac.type = I40E_MAC_XL710; | hw->mac.type = I40E_MAC_XL710; | ||||
break; | break; | ||||
case I40E_DEV_ID_X722_A0: | |||||
case I40E_DEV_ID_KX_X722: | case I40E_DEV_ID_KX_X722: | ||||
case I40E_DEV_ID_QSFP_X722: | case I40E_DEV_ID_QSFP_X722: | ||||
case I40E_DEV_ID_SFP_X722: | case I40E_DEV_ID_SFP_X722: | ||||
case I40E_DEV_ID_1G_BASE_T_X722: | case I40E_DEV_ID_1G_BASE_T_X722: | ||||
case I40E_DEV_ID_10G_BASE_T_X722: | case I40E_DEV_ID_10G_BASE_T_X722: | ||||
case I40E_DEV_ID_SFP_I_X722: | case I40E_DEV_ID_SFP_I_X722: | ||||
hw->mac.type = I40E_MAC_X722; | hw->mac.type = I40E_MAC_X722; | ||||
break; | break; | ||||
case I40E_DEV_ID_X722_VF: | case I40E_DEV_ID_X722_VF: | ||||
case I40E_DEV_ID_X722_A0_VF: | |||||
hw->mac.type = I40E_MAC_X722_VF; | hw->mac.type = I40E_MAC_X722_VF; | ||||
break; | break; | ||||
case I40E_DEV_ID_VF: | case I40E_DEV_ID_VF: | ||||
case I40E_DEV_ID_VF_HV: | case I40E_DEV_ID_VF_HV: | ||||
case I40E_DEV_ID_ADAPTIVE_VF: | |||||
hw->mac.type = I40E_MAC_VF; | hw->mac.type = I40E_MAC_VF; | ||||
break; | break; | ||||
default: | default: | ||||
hw->mac.type = I40E_MAC_GENERIC; | hw->mac.type = I40E_MAC_GENERIC; | ||||
break; | break; | ||||
} | } | ||||
} else { | } else { | ||||
status = I40E_ERR_DEVICE_NOT_SUPPORTED; | status = I40E_ERR_DEVICE_NOT_SUPPORTED; | ||||
▲ Show 20 Lines • Show All 199 Lines • ▼ Show 20 Lines | const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err) | ||||
case I40E_ERR_DIAG_TEST_FAILED: | case I40E_ERR_DIAG_TEST_FAILED: | ||||
return "I40E_ERR_DIAG_TEST_FAILED"; | return "I40E_ERR_DIAG_TEST_FAILED"; | ||||
case I40E_ERR_NOT_READY: | case I40E_ERR_NOT_READY: | ||||
return "I40E_ERR_NOT_READY"; | return "I40E_ERR_NOT_READY"; | ||||
case I40E_NOT_SUPPORTED: | case I40E_NOT_SUPPORTED: | ||||
return "I40E_NOT_SUPPORTED"; | return "I40E_NOT_SUPPORTED"; | ||||
case I40E_ERR_FIRMWARE_API_VERSION: | case I40E_ERR_FIRMWARE_API_VERSION: | ||||
return "I40E_ERR_FIRMWARE_API_VERSION"; | return "I40E_ERR_FIRMWARE_API_VERSION"; | ||||
case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR: | |||||
return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR"; | |||||
} | } | ||||
snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); | snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); | ||||
return hw->err_str; | return hw->err_str; | ||||
} | } | ||||
/** | /** | ||||
* i40e_debug_aq | * i40e_debug_aq | ||||
* @hw: debug mask related to admin queue | * @hw: debug mask related to admin queue | ||||
* @mask: debug mask | * @mask: debug mask | ||||
* @desc: pointer to admin queue descriptor | * @desc: pointer to admin queue descriptor | ||||
* @buffer: pointer to command buffer | * @buffer: pointer to command buffer | ||||
* @buf_len: max length of buffer | * @buf_len: max length of buffer | ||||
* | * | ||||
* Dumps debug log about adminq command with descriptor contents. | * Dumps debug log about adminq command with descriptor contents. | ||||
**/ | **/ | ||||
void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, | void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, | ||||
void *buffer, u16 buf_len) | void *buffer, u16 buf_len) | ||||
{ | { | ||||
struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; | struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; | ||||
u16 len = LE16_TO_CPU(aq_desc->datalen); | |||||
u8 *buf = (u8 *)buffer; | u8 *buf = (u8 *)buffer; | ||||
u16 len; | |||||
u16 i = 0; | u16 i = 0; | ||||
if ((!(mask & hw->debug_mask)) || (desc == NULL)) | if ((!(mask & hw->debug_mask)) || (desc == NULL)) | ||||
return; | return; | ||||
len = LE16_TO_CPU(aq_desc->datalen); | |||||
i40e_debug(hw, mask, | i40e_debug(hw, mask, | ||||
"AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", | "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", | ||||
LE16_TO_CPU(aq_desc->opcode), | LE16_TO_CPU(aq_desc->opcode), | ||||
LE16_TO_CPU(aq_desc->flags), | LE16_TO_CPU(aq_desc->flags), | ||||
LE16_TO_CPU(aq_desc->datalen), | LE16_TO_CPU(aq_desc->datalen), | ||||
LE16_TO_CPU(aq_desc->retval)); | LE16_TO_CPU(aq_desc->retval)); | ||||
i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", | i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", | ||||
LE32_TO_CPU(aq_desc->cookie_high), | LE32_TO_CPU(aq_desc->cookie_high), | ||||
▲ Show 20 Lines • Show All 667 Lines • ▼ Show 20 Lines | ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> | ||||
I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; | I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; | ||||
func_rid = rd32(hw, I40E_PF_FUNC_RID); | func_rid = rd32(hw, I40E_PF_FUNC_RID); | ||||
if (ari) | if (ari) | ||||
hw->pf_id = (u8)(func_rid & 0xff); | hw->pf_id = (u8)(func_rid & 0xff); | ||||
else | else | ||||
hw->pf_id = (u8)(func_rid & 0x7); | hw->pf_id = (u8)(func_rid & 0x7); | ||||
if (hw->mac.type == I40E_MAC_X722) | if (hw->mac.type == I40E_MAC_X722) | ||||
hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE; | hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE | | ||||
I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; | |||||
status = i40e_init_nvm(hw); | status = i40e_init_nvm(hw); | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_aq_mac_address_read - Retrieve the MAC addresses | * i40e_aq_mac_address_read - Retrieve the MAC addresses | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
▲ Show 20 Lines • Show All 217 Lines • ▼ Show 20 Lines | static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) | ||||
case I40E_PHY_TYPE_10GBASE_CR1_CU: | case I40E_PHY_TYPE_10GBASE_CR1_CU: | ||||
case I40E_PHY_TYPE_40GBASE_CR4_CU: | case I40E_PHY_TYPE_40GBASE_CR4_CU: | ||||
case I40E_PHY_TYPE_10GBASE_CR1: | case I40E_PHY_TYPE_10GBASE_CR1: | ||||
case I40E_PHY_TYPE_40GBASE_CR4: | case I40E_PHY_TYPE_40GBASE_CR4: | ||||
case I40E_PHY_TYPE_10GBASE_SFPP_CU: | case I40E_PHY_TYPE_10GBASE_SFPP_CU: | ||||
case I40E_PHY_TYPE_40GBASE_AOC: | case I40E_PHY_TYPE_40GBASE_AOC: | ||||
case I40E_PHY_TYPE_10GBASE_AOC: | case I40E_PHY_TYPE_10GBASE_AOC: | ||||
case I40E_PHY_TYPE_25GBASE_CR: | case I40E_PHY_TYPE_25GBASE_CR: | ||||
case I40E_PHY_TYPE_25GBASE_AOC: | |||||
case I40E_PHY_TYPE_25GBASE_ACC: | |||||
media = I40E_MEDIA_TYPE_DA; | media = I40E_MEDIA_TYPE_DA; | ||||
break; | break; | ||||
case I40E_PHY_TYPE_1000BASE_KX: | case I40E_PHY_TYPE_1000BASE_KX: | ||||
case I40E_PHY_TYPE_10GBASE_KX4: | case I40E_PHY_TYPE_10GBASE_KX4: | ||||
case I40E_PHY_TYPE_10GBASE_KR: | case I40E_PHY_TYPE_10GBASE_KR: | ||||
case I40E_PHY_TYPE_40GBASE_KR4: | case I40E_PHY_TYPE_40GBASE_KR4: | ||||
case I40E_PHY_TYPE_20GBASE_KR2: | case I40E_PHY_TYPE_20GBASE_KR2: | ||||
case I40E_PHY_TYPE_25GBASE_KR: | case I40E_PHY_TYPE_25GBASE_KR: | ||||
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines | if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | | ||||
DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); | DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); | ||||
return I40E_ERR_RESET_FAILED; | return I40E_ERR_RESET_FAILED; | ||||
} | } | ||||
/* If there was a Global Reset in progress when we got here, | /* If there was a Global Reset in progress when we got here, | ||||
* we don't need to do the PF Reset | * we don't need to do the PF Reset | ||||
*/ | */ | ||||
if (!cnt) { | if (!cnt) { | ||||
u32 reg2 = 0; | |||||
reg = rd32(hw, I40E_PFGEN_CTRL); | reg = rd32(hw, I40E_PFGEN_CTRL); | ||||
wr32(hw, I40E_PFGEN_CTRL, | wr32(hw, I40E_PFGEN_CTRL, | ||||
(reg | I40E_PFGEN_CTRL_PFSWR_MASK)); | (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); | ||||
for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { | for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { | ||||
reg = rd32(hw, I40E_PFGEN_CTRL); | reg = rd32(hw, I40E_PFGEN_CTRL); | ||||
if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) | if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) | ||||
break; | break; | ||||
reg2 = rd32(hw, I40E_GLGEN_RSTAT); | |||||
if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { | |||||
DEBUGOUT("Core reset upcoming. Skipping PF reset request.\n"); | |||||
DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2); | |||||
return I40E_ERR_NOT_READY; | |||||
} | |||||
i40e_msec_delay(1); | i40e_msec_delay(1); | ||||
} | } | ||||
if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { | if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { | ||||
DEBUGOUT("PF reset polling failed to complete.\n"); | DEBUGOUT("PF reset polling failed to complete.\n"); | ||||
return I40E_ERR_RESET_FAILED; | return I40E_ERR_RESET_FAILED; | ||||
} | } | ||||
} | } | ||||
▲ Show 20 Lines • Show All 172 Lines • ▼ Show 20 Lines | for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { | ||||
* LEDs | * LEDs | ||||
*/ | */ | ||||
current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) | current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) | ||||
>> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); | >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); | ||||
switch (current_mode) { | switch (current_mode) { | ||||
case I40E_COMBINED_ACTIVITY: | case I40E_COMBINED_ACTIVITY: | ||||
case I40E_FILTER_ACTIVITY: | case I40E_FILTER_ACTIVITY: | ||||
case I40E_MAC_ACTIVITY: | case I40E_MAC_ACTIVITY: | ||||
case I40E_LINK_ACTIVITY: | |||||
continue; | continue; | ||||
default: | default: | ||||
break; | break; | ||||
} | } | ||||
mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> | mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> | ||||
I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; | I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; | ||||
break; | break; | ||||
Show All 32 Lines | for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { | ||||
* LEDs | * LEDs | ||||
*/ | */ | ||||
current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) | current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) | ||||
>> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); | >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); | ||||
switch (current_mode) { | switch (current_mode) { | ||||
case I40E_COMBINED_ACTIVITY: | case I40E_COMBINED_ACTIVITY: | ||||
case I40E_FILTER_ACTIVITY: | case I40E_FILTER_ACTIVITY: | ||||
case I40E_MAC_ACTIVITY: | case I40E_MAC_ACTIVITY: | ||||
case I40E_LINK_ACTIVITY: | |||||
continue; | continue; | ||||
default: | default: | ||||
break; | break; | ||||
} | } | ||||
gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; | gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; | ||||
/* this & is a bit of paranoia, but serves as a range check */ | /* this & is a bit of paranoia, but serves as a range check */ | ||||
gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & | gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & | ||||
I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); | I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); | ||||
if (mode == I40E_LINK_ACTIVITY) | |||||
blink = FALSE; | |||||
if (blink) | if (blink) | ||||
gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); | gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); | ||||
else | else | ||||
gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); | gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); | ||||
wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); | wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); | ||||
break; | break; | ||||
} | } | ||||
Show All 13 Lines | |||||
**/ | **/ | ||||
enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, | enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, | ||||
bool qualified_modules, bool report_init, | bool qualified_modules, bool report_init, | ||||
struct i40e_aq_get_phy_abilities_resp *abilities, | struct i40e_aq_get_phy_abilities_resp *abilities, | ||||
struct i40e_asq_cmd_details *cmd_details) | struct i40e_asq_cmd_details *cmd_details) | ||||
{ | { | ||||
struct i40e_aq_desc desc; | struct i40e_aq_desc desc; | ||||
enum i40e_status_code status; | enum i40e_status_code status; | ||||
u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; | |||||
u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); | u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); | ||||
if (!abilities) | if (!abilities) | ||||
return I40E_ERR_PARAM; | return I40E_ERR_PARAM; | ||||
do { | |||||
i40e_fill_default_direct_cmd_desc(&desc, | i40e_fill_default_direct_cmd_desc(&desc, | ||||
i40e_aqc_opc_get_phy_abilities); | i40e_aqc_opc_get_phy_abilities); | ||||
desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); | desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); | ||||
if (abilities_size > I40E_AQ_LARGE_BUF) | if (abilities_size > I40E_AQ_LARGE_BUF) | ||||
desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); | desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); | ||||
if (qualified_modules) | if (qualified_modules) | ||||
desc.params.external.param0 |= | desc.params.external.param0 |= | ||||
CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); | CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); | ||||
if (report_init) | if (report_init) | ||||
desc.params.external.param0 |= | desc.params.external.param0 |= | ||||
CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); | CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); | ||||
status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, | status = i40e_asq_send_command(hw, &desc, abilities, | ||||
cmd_details); | abilities_size, cmd_details); | ||||
if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) | if (status != I40E_SUCCESS) | ||||
break; | |||||
if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) { | |||||
status = I40E_ERR_UNKNOWN_PHY; | status = I40E_ERR_UNKNOWN_PHY; | ||||
break; | |||||
} else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) { | |||||
i40e_msec_delay(1); | |||||
total_delay++; | |||||
status = I40E_ERR_TIMEOUT; | |||||
} | |||||
} while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) && | |||||
(total_delay < max_delay)); | |||||
if (status != I40E_SUCCESS) | |||||
return status; | |||||
if (report_init) { | if (report_init) { | ||||
if (hw->mac.type == I40E_MAC_XL710 && | |||||
hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && | |||||
hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { | |||||
status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); | |||||
} else { | |||||
hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type); | hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type); | ||||
hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32); | hw->phy.phy_types |= | ||||
((u64)abilities->phy_type_ext << 32); | |||||
} | } | ||||
} | |||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_aq_set_phy_config | * i40e_aq_set_phy_config | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @config: structure with PHY configuration to be set | * @config: structure with PHY configuration to be set | ||||
Show All 25 Lines | enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, | ||||
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_set_fc | * i40e_set_fc | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @aq_failures: buffer to return AdminQ failure information | |||||
* @atomic_restart: whether to enable atomic link restart | |||||
* | * | ||||
* Set the requested flow control mode using set_phy_config. | * Set the requested flow control mode using set_phy_config. | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, | enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, | ||||
bool atomic_restart) | bool atomic_restart) | ||||
{ | { | ||||
enum i40e_fc_mode fc_mode = hw->fc.requested_mode; | enum i40e_fc_mode fc_mode = hw->fc.requested_mode; | ||||
struct i40e_aq_get_phy_abilities_resp abilities; | struct i40e_aq_get_phy_abilities_resp abilities; | ||||
▲ Show 20 Lines • Show All 203 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, | ||||
hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; | hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; | ||||
hw->phy.media_type = i40e_get_media_type(hw); | hw->phy.media_type = i40e_get_media_type(hw); | ||||
hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; | hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; | ||||
hw_link_info->link_info = resp->link_info; | hw_link_info->link_info = resp->link_info; | ||||
hw_link_info->an_info = resp->an_info; | hw_link_info->an_info = resp->an_info; | ||||
hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | | hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA | | ||||
I40E_AQ_CONFIG_FEC_RS_ENA); | I40E_AQ_CONFIG_FEC_RS_ENA); | ||||
hw_link_info->ext_info = resp->ext_info; | hw_link_info->ext_info = resp->ext_info; | ||||
hw_link_info->loopback = resp->loopback; | hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; | ||||
hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); | hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); | ||||
hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; | hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; | ||||
/* update fc info */ | /* update fc info */ | ||||
tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); | tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); | ||||
rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); | rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); | ||||
if (tx_pause & rx_pause) | if (tx_pause & rx_pause) | ||||
hw->fc.current_mode = I40E_FC_FULL; | hw->fc.current_mode = I40E_FC_FULL; | ||||
Show All 14 Lines | enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, | ||||
else | else | ||||
hw_link_info->lse_enable = FALSE; | hw_link_info->lse_enable = FALSE; | ||||
if ((hw->mac.type == I40E_MAC_XL710) && | if ((hw->mac.type == I40E_MAC_XL710) && | ||||
(hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && | (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && | ||||
hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) | hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) | ||||
hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; | hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; | ||||
if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && | |||||
hw->aq.api_min_ver >= 7) { | |||||
__le32 tmp; | |||||
i40e_memcpy(&tmp, resp->link_type, sizeof(tmp), | |||||
I40E_NONDMA_TO_NONDMA); | |||||
hw->phy.phy_types = LE32_TO_CPU(tmp); | |||||
hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); | |||||
} | |||||
/* save link status information */ | /* save link status information */ | ||||
if (link) | if (link) | ||||
i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info), | i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info), | ||||
I40E_NONDMA_TO_NONDMA); | I40E_NONDMA_TO_NONDMA); | ||||
/* flag cleared so helper functions don't call AQ again */ | /* flag cleared so helper functions don't call AQ again */ | ||||
hw->phy.get_link_info = FALSE; | hw->phy.get_link_info = FALSE; | ||||
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines | |||||
/** | /** | ||||
* i40e_aq_set_lb_modes | * i40e_aq_set_lb_modes | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @lb_modes: loopback mode to be set | * @lb_modes: loopback mode to be set | ||||
* @cmd_details: pointer to command details structure or NULL | * @cmd_details: pointer to command details structure or NULL | ||||
* | * | ||||
* Sets loopback modes. | * Sets loopback modes. | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, | enum i40e_status_code | ||||
u16 lb_modes, | i40e_aq_set_lb_modes(struct i40e_hw *hw, u8 lb_level, u8 lb_type, u8 speed, | ||||
struct i40e_asq_cmd_details *cmd_details) | struct i40e_asq_cmd_details *cmd_details) | ||||
{ | { | ||||
struct i40e_aq_desc desc; | struct i40e_aq_desc desc; | ||||
struct i40e_aqc_set_lb_mode *cmd = | struct i40e_aqc_set_lb_mode *cmd = | ||||
(struct i40e_aqc_set_lb_mode *)&desc.params.raw; | (struct i40e_aqc_set_lb_mode *)&desc.params.raw; | ||||
enum i40e_status_code status; | enum i40e_status_code status; | ||||
i40e_fill_default_direct_cmd_desc(&desc, | i40e_fill_default_direct_cmd_desc(&desc, | ||||
i40e_aqc_opc_set_lb_modes); | i40e_aqc_opc_set_lb_modes); | ||||
cmd->lb_mode = CPU_TO_LE16(lb_modes); | cmd->lb_level = lb_level; | ||||
cmd->lb_type = lb_type; | |||||
cmd->speed = speed; | |||||
if (speed) | |||||
cmd->force_speed = 1; | |||||
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_aq_set_phy_debug | * i40e_aq_set_phy_debug | ||||
▲ Show 20 Lines • Show All 509 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_aq_set_switch_config | * i40e_aq_set_switch_config | ||||
* @hw: pointer to the hardware structure | * @hw: pointer to the hardware structure | ||||
* @flags: bit flag values to set | * @flags: bit flag values to set | ||||
* @mode: cloud filter mode | |||||
* @valid_flags: which bit flags to set | * @valid_flags: which bit flags to set | ||||
* @cmd_details: pointer to command details structure or NULL | * @cmd_details: pointer to command details structure or NULL | ||||
* | * | ||||
* Set switch configuration bits | * Set switch configuration bits | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, | enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, | ||||
u16 flags, u16 valid_flags, | u16 flags, u16 valid_flags, u8 mode, | ||||
struct i40e_asq_cmd_details *cmd_details) | struct i40e_asq_cmd_details *cmd_details) | ||||
{ | { | ||||
struct i40e_aq_desc desc; | struct i40e_aq_desc desc; | ||||
struct i40e_aqc_set_switch_config *scfg = | struct i40e_aqc_set_switch_config *scfg = | ||||
(struct i40e_aqc_set_switch_config *)&desc.params.raw; | (struct i40e_aqc_set_switch_config *)&desc.params.raw; | ||||
enum i40e_status_code status; | enum i40e_status_code status; | ||||
i40e_fill_default_direct_cmd_desc(&desc, | i40e_fill_default_direct_cmd_desc(&desc, | ||||
i40e_aqc_opc_set_switch_config); | i40e_aqc_opc_set_switch_config); | ||||
scfg->flags = CPU_TO_LE16(flags); | scfg->flags = CPU_TO_LE16(flags); | ||||
scfg->valid_flags = CPU_TO_LE16(valid_flags); | scfg->valid_flags = CPU_TO_LE16(valid_flags); | ||||
scfg->mode = mode; | |||||
if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { | |||||
scfg->switch_tag = CPU_TO_LE16(hw->switch_tag); | |||||
scfg->first_tag = CPU_TO_LE16(hw->first_tag); | |||||
scfg->second_tag = CPU_TO_LE16(hw->second_tag); | |||||
} | |||||
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_aq_get_firmware_version | * i40e_aq_get_firmware_version | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
▲ Show 20 Lines • Show All 129 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw) | ||||
if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && | if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && | ||||
((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || | ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || | ||||
!(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { | !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { | ||||
status = i40e_aq_get_phy_capabilities(hw, FALSE, false, | status = i40e_aq_get_phy_capabilities(hw, FALSE, false, | ||||
&abilities, NULL); | &abilities, NULL); | ||||
if (status) | if (status) | ||||
return status; | return status; | ||||
hw->phy.link_info.req_fec_info = | |||||
abilities.fec_cfg_curr_mod_ext_info & | |||||
(I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS); | |||||
i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type, | i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type, | ||||
sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA); | sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA); | ||||
} | } | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
▲ Show 20 Lines • Show All 232 Lines • ▼ Show 20 Lines | |||||
* @opcode: AQ opcode for add or delete mirror rule | * @opcode: AQ opcode for add or delete mirror rule | ||||
* @sw_seid: Switch SEID (to which rule refers) | * @sw_seid: Switch SEID (to which rule refers) | ||||
* @rule_type: Rule Type (ingress/egress/VLAN) | * @rule_type: Rule Type (ingress/egress/VLAN) | ||||
* @id: Destination VSI SEID or Rule ID | * @id: Destination VSI SEID or Rule ID | ||||
* @count: length of the list | * @count: length of the list | ||||
* @mr_list: list of mirrored VSI SEIDs or VLAN IDs | * @mr_list: list of mirrored VSI SEIDs or VLAN IDs | ||||
* @cmd_details: pointer to command details structure or NULL | * @cmd_details: pointer to command details structure or NULL | ||||
* @rule_id: Rule ID returned from FW | * @rule_id: Rule ID returned from FW | ||||
* @rule_used: Number of rules used in internal switch | * @rules_used: Number of rules used in internal switch | ||||
* @rule_free: Number of rules free in internal switch | * @rules_free: Number of rules free in internal switch | ||||
* | * | ||||
* Add/Delete a mirror rule to a specific switch. Mirror rules are supported for | * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for | ||||
* VEBs/VEPA elements only | * VEBs/VEPA elements only | ||||
**/ | **/ | ||||
static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw, | static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw, | ||||
u16 opcode, u16 sw_seid, u16 rule_type, u16 id, | u16 opcode, u16 sw_seid, u16 rule_type, u16 id, | ||||
u16 count, __le16 *mr_list, | u16 count, __le16 *mr_list, | ||||
struct i40e_asq_cmd_details *cmd_details, | struct i40e_asq_cmd_details *cmd_details, | ||||
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines | |||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @sw_seid: Switch SEID (to which rule refers) | * @sw_seid: Switch SEID (to which rule refers) | ||||
* @rule_type: Rule Type (ingress/egress/VLAN) | * @rule_type: Rule Type (ingress/egress/VLAN) | ||||
* @dest_vsi: SEID of VSI to which packets will be mirrored | * @dest_vsi: SEID of VSI to which packets will be mirrored | ||||
* @count: length of the list | * @count: length of the list | ||||
* @mr_list: list of mirrored VSI SEIDs or VLAN IDs | * @mr_list: list of mirrored VSI SEIDs or VLAN IDs | ||||
* @cmd_details: pointer to command details structure or NULL | * @cmd_details: pointer to command details structure or NULL | ||||
* @rule_id: Rule ID returned from FW | * @rule_id: Rule ID returned from FW | ||||
* @rule_used: Number of rules used in internal switch | * @rules_used: Number of rules used in internal switch | ||||
* @rule_free: Number of rules free in internal switch | * @rules_free: Number of rules free in internal switch | ||||
* | * | ||||
* Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only | * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, | enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, | ||||
u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, | u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, | ||||
struct i40e_asq_cmd_details *cmd_details, | struct i40e_asq_cmd_details *cmd_details, | ||||
u16 *rule_id, u16 *rules_used, u16 *rules_free) | u16 *rule_id, u16 *rules_used, u16 *rules_free) | ||||
{ | { | ||||
Show All 13 Lines | |||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @sw_seid: Switch SEID (to which rule refers) | * @sw_seid: Switch SEID (to which rule refers) | ||||
* @rule_type: Rule Type (ingress/egress/VLAN) | * @rule_type: Rule Type (ingress/egress/VLAN) | ||||
* @count: length of the list | * @count: length of the list | ||||
* @rule_id: Rule ID that is returned in the receive desc as part of | * @rule_id: Rule ID that is returned in the receive desc as part of | ||||
* add_mirrorrule. | * add_mirrorrule. | ||||
* @mr_list: list of mirrored VLAN IDs to be removed | * @mr_list: list of mirrored VLAN IDs to be removed | ||||
* @cmd_details: pointer to command details structure or NULL | * @cmd_details: pointer to command details structure or NULL | ||||
* @rule_used: Number of rules used in internal switch | * @rules_used: Number of rules used in internal switch | ||||
* @rule_free: Number of rules free in internal switch | * @rules_free: Number of rules free in internal switch | ||||
* | * | ||||
* Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only | * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, | enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, | ||||
u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, | u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, | ||||
struct i40e_asq_cmd_details *cmd_details, | struct i40e_asq_cmd_details *cmd_details, | ||||
u16 *rules_used, u16 *rules_free) | u16 *rules_used, u16 *rules_free) | ||||
{ | { | ||||
▲ Show 20 Lines • Show All 386 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw, | ||||
status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); | status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_aq_oem_post_update - triggers an OEM specific flow after update | * i40e_aq_oem_post_update - triggers an OEM specific flow after update | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @buff: buffer for result | |||||
* @buff_size: buffer size | |||||
* @cmd_details: pointer to command details structure or NULL | * @cmd_details: pointer to command details structure or NULL | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw, | enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw, | ||||
void *buff, u16 buff_size, | void *buff, u16 buff_size, | ||||
struct i40e_asq_cmd_details *cmd_details) | struct i40e_asq_cmd_details *cmd_details) | ||||
{ | { | ||||
struct i40e_aq_desc desc; | struct i40e_aq_desc desc; | ||||
enum i40e_status_code status; | enum i40e_status_code status; | ||||
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines | |||||
static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, | static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, | ||||
u32 cap_count, | u32 cap_count, | ||||
enum i40e_admin_queue_opc list_type_opc) | enum i40e_admin_queue_opc list_type_opc) | ||||
{ | { | ||||
struct i40e_aqc_list_capabilities_element_resp *cap; | struct i40e_aqc_list_capabilities_element_resp *cap; | ||||
u32 valid_functions, num_functions; | u32 valid_functions, num_functions; | ||||
u32 number, logical_id, phys_id; | u32 number, logical_id, phys_id; | ||||
struct i40e_hw_capabilities *p; | struct i40e_hw_capabilities *p; | ||||
enum i40e_status_code status; | |||||
u16 id, ocp_cfg_word0; | |||||
u8 major_rev; | u8 major_rev; | ||||
u32 i = 0; | u32 i = 0; | ||||
u16 id; | |||||
cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; | cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; | ||||
if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) | if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) | ||||
p = (struct i40e_hw_capabilities *)&hw->dev_caps; | p = (struct i40e_hw_capabilities *)&hw->dev_caps; | ||||
else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) | else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) | ||||
p = (struct i40e_hw_capabilities *)&hw->func_caps; | p = (struct i40e_hw_capabilities *)&hw->func_caps; | ||||
else | else | ||||
▲ Show 20 Lines • Show All 275 Lines • ▼ Show 20 Lines | for (i = 0; i < 4; i++) { | ||||
/* use AQ read to get the physical register offset instead | /* use AQ read to get the physical register offset instead | ||||
* of the port relative offset | * of the port relative offset | ||||
*/ | */ | ||||
i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); | i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); | ||||
if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) | if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK)) | ||||
hw->num_ports++; | hw->num_ports++; | ||||
} | } | ||||
/* OCP cards case: if a mezz is removed the ethernet port is at | |||||
* disabled state in PRTGEN_CNF register. Additional NVM read is | |||||
* needed in order to check if we are dealing with OCP card. | |||||
* Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting | |||||
* physical ports results in wrong partition id calculation and thus | |||||
* not supporting WoL. | |||||
*/ | |||||
if (hw->mac.type == I40E_MAC_X722) { | |||||
if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) { | |||||
status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, | |||||
2 * I40E_SR_OCP_CFG_WORD0, | |||||
sizeof(ocp_cfg_word0), | |||||
&ocp_cfg_word0, TRUE, NULL); | |||||
if (status == I40E_SUCCESS && | |||||
(ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) | |||||
hw->num_ports = 4; | |||||
i40e_release_nvm(hw); | |||||
} | |||||
} | |||||
valid_functions = p->valid_functions; | valid_functions = p->valid_functions; | ||||
num_functions = 0; | num_functions = 0; | ||||
while (valid_functions) { | while (valid_functions) { | ||||
if (valid_functions & 1) | if (valid_functions & 1) | ||||
num_functions++; | num_functions++; | ||||
valid_functions >>= 1; | valid_functions >>= 1; | ||||
} | } | ||||
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines | |||||
/** | /** | ||||
* i40e_aq_update_nvm | * i40e_aq_update_nvm | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @module_pointer: module pointer location in words from the NVM beginning | * @module_pointer: module pointer location in words from the NVM beginning | ||||
* @offset: byte offset from the module beginning | * @offset: byte offset from the module beginning | ||||
* @length: length of the section to be written (in bytes from the offset) | * @length: length of the section to be written (in bytes from the offset) | ||||
* @data: command buffer (size [bytes] = length) | * @data: command buffer (size [bytes] = length) | ||||
* @last_command: tells if this is the last command in a series | * @last_command: tells if this is the last command in a series | ||||
* @preservation_flags: Preservation mode flags | |||||
* @cmd_details: pointer to command details structure or NULL | * @cmd_details: pointer to command details structure or NULL | ||||
* | * | ||||
* Update the NVM using the admin queue commands | * Update the NVM using the admin queue commands | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, | enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, | ||||
u32 offset, u16 length, void *data, | u32 offset, u16 length, void *data, | ||||
bool last_command, | bool last_command, u8 preservation_flags, | ||||
struct i40e_asq_cmd_details *cmd_details) | struct i40e_asq_cmd_details *cmd_details) | ||||
{ | { | ||||
struct i40e_aq_desc desc; | struct i40e_aq_desc desc; | ||||
struct i40e_aqc_nvm_update *cmd = | struct i40e_aqc_nvm_update *cmd = | ||||
(struct i40e_aqc_nvm_update *)&desc.params.raw; | (struct i40e_aqc_nvm_update *)&desc.params.raw; | ||||
enum i40e_status_code status; | enum i40e_status_code status; | ||||
DEBUGFUNC("i40e_aq_update_nvm"); | DEBUGFUNC("i40e_aq_update_nvm"); | ||||
/* In offset the highest byte must be zeroed. */ | /* In offset the highest byte must be zeroed. */ | ||||
if (offset & 0xFF000000) { | if (offset & 0xFF000000) { | ||||
status = I40E_ERR_PARAM; | status = I40E_ERR_PARAM; | ||||
goto i40e_aq_update_nvm_exit; | goto i40e_aq_update_nvm_exit; | ||||
} | } | ||||
i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); | ||||
/* If this is the last command in a series, set the proper flag. */ | /* If this is the last command in a series, set the proper flag. */ | ||||
if (last_command) | if (last_command) | ||||
cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; | cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; | ||||
if (hw->mac.type == I40E_MAC_X722) { | |||||
if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED) | |||||
cmd->command_flags |= | |||||
(I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED << | |||||
I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); | |||||
else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL) | |||||
cmd->command_flags |= | |||||
(I40E_AQ_NVM_PRESERVATION_FLAGS_ALL << | |||||
I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); | |||||
} | |||||
cmd->module_pointer = module_pointer; | cmd->module_pointer = module_pointer; | ||||
cmd->offset = CPU_TO_LE32(offset); | cmd->offset = CPU_TO_LE32(offset); | ||||
cmd->length = CPU_TO_LE16(length); | cmd->length = CPU_TO_LE16(length); | ||||
desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); | desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); | ||||
if (length > I40E_AQ_LARGE_BUF) | if (length > I40E_AQ_LARGE_BUF) | ||||
desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); | desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); | ||||
status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); | status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); | ||||
i40e_aq_update_nvm_exit: | i40e_aq_update_nvm_exit: | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_aq_nvm_progress | |||||
* @hw: pointer to the hw struct | |||||
* @progress: pointer to progress returned from AQ | |||||
* @cmd_details: pointer to command details structure or NULL | |||||
* | |||||
* Gets progress of flash rearrangement process | |||||
**/ | |||||
enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress, | |||||
struct i40e_asq_cmd_details *cmd_details) | |||||
{ | |||||
enum i40e_status_code status; | |||||
struct i40e_aq_desc desc; | |||||
DEBUGFUNC("i40e_aq_nvm_progress"); | |||||
i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress); | |||||
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |||||
*progress = desc.params.raw[0]; | |||||
return status; | |||||
} | |||||
/** | |||||
* i40e_aq_get_lldp_mib | * i40e_aq_get_lldp_mib | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @bridge_type: type of bridge requested | * @bridge_type: type of bridge requested | ||||
* @mib_type: Local, Remote or both Local and Remote MIBs | * @mib_type: Local, Remote or both Local and Remote MIBs | ||||
* @buff: pointer to a user supplied buffer to store the MIB block | * @buff: pointer to a user supplied buffer to store the MIB block | ||||
* @buff_size: size of the buffer (in bytes) | * @buff_size: size of the buffer (in bytes) | ||||
* @local_len : length of the returned Local LLDP MIB | * @local_len : length of the returned Local LLDP MIB | ||||
* @remote_len: length of the returned Remote LLDP MIB | * @remote_len: length of the returned Remote LLDP MIB | ||||
▲ Show 20 Lines • Show All 297 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw, | ||||
struct i40e_aq_desc desc; | struct i40e_aq_desc desc; | ||||
struct i40e_aqc_lldp_start *cmd = | struct i40e_aqc_lldp_start *cmd = | ||||
(struct i40e_aqc_lldp_start *)&desc.params.raw; | (struct i40e_aqc_lldp_start *)&desc.params.raw; | ||||
enum i40e_status_code status; | enum i40e_status_code status; | ||||
i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); | i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); | ||||
cmd->command = I40E_AQ_LLDP_AGENT_START; | cmd->command = I40E_AQ_LLDP_AGENT_START; | ||||
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |||||
return status; | |||||
} | |||||
/** | |||||
* i40e_aq_set_dcb_parameters | |||||
* @hw: pointer to the hw struct | |||||
* @cmd_details: pointer to command details structure or NULL | |||||
* @dcb_enable: True if DCB configuration needs to be applied | |||||
* | |||||
**/ | |||||
enum i40e_status_code | |||||
i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, | |||||
struct i40e_asq_cmd_details *cmd_details) | |||||
{ | |||||
struct i40e_aq_desc desc; | |||||
struct i40e_aqc_set_dcb_parameters *cmd = | |||||
(struct i40e_aqc_set_dcb_parameters *)&desc.params.raw; | |||||
enum i40e_status_code status; | |||||
if ((hw->mac.type != I40E_MAC_XL710) || | |||||
((hw->aq.api_maj_ver < 1) || | |||||
((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 6)))) | |||||
return I40E_ERR_DEVICE_NOT_SUPPORTED; | |||||
i40e_fill_default_direct_cmd_desc(&desc, | |||||
i40e_aqc_opc_set_dcb_parameters); | |||||
if (dcb_enable) { | |||||
cmd->valid_flags = I40E_DCB_VALID; | |||||
cmd->command = I40E_AQ_DCB_SET_AGENT; | |||||
} | |||||
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_aq_get_cee_dcb_config | * i40e_aq_get_cee_dcb_config | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw, | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_aq_add_udp_tunnel | * i40e_aq_add_udp_tunnel | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @udp_port: the UDP port to add in Host byte order | * @udp_port: the UDP port to add in Host byte order | ||||
* @header_len: length of the tunneling header length in DWords | |||||
* @protocol_index: protocol index type | * @protocol_index: protocol index type | ||||
* @filter_index: pointer to filter index | * @filter_index: pointer to filter index | ||||
* @cmd_details: pointer to command details structure or NULL | * @cmd_details: pointer to command details structure or NULL | ||||
* | * | ||||
* Note: Firmware expects the udp_port value to be in Little Endian format, | * Note: Firmware expects the udp_port value to be in Little Endian format, | ||||
* and this function will call CPU_TO_LE16 to convert from Host byte order to | * and this function will call CPU_TO_LE16 to convert from Host byte order to | ||||
* Little Endian order. | * Little Endian order. | ||||
**/ | **/ | ||||
▲ Show 20 Lines • Show All 1,030 Lines • ▼ Show 20 Lines | i40e_fill_default_direct_cmd_desc(&desc, | ||||
i40e_aqc_opc_add_control_packet_filter); | i40e_aqc_opc_add_control_packet_filter); | ||||
cmd->queue = CPU_TO_LE16(queue); | cmd->queue = CPU_TO_LE16(queue); | ||||
} else { | } else { | ||||
i40e_fill_default_direct_cmd_desc(&desc, | i40e_fill_default_direct_cmd_desc(&desc, | ||||
i40e_aqc_opc_remove_control_packet_filter); | i40e_aqc_opc_remove_control_packet_filter); | ||||
} | } | ||||
if (mac_addr) | if (mac_addr) | ||||
i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS, | i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN, | ||||
I40E_NONDMA_TO_NONDMA); | I40E_NONDMA_TO_NONDMA); | ||||
cmd->etype = CPU_TO_LE16(ethtype); | cmd->etype = CPU_TO_LE16(ethtype); | ||||
cmd->flags = CPU_TO_LE16(flags); | cmd->flags = CPU_TO_LE16(flags); | ||||
cmd->seid = CPU_TO_LE16(vsi_seid); | cmd->seid = CPU_TO_LE16(vsi_seid); | ||||
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | ||||
if (!status && stats) { | if (!status && stats) { | ||||
stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); | stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); | ||||
stats->etype_used = LE16_TO_CPU(resp->etype_used); | stats->etype_used = LE16_TO_CPU(resp->etype_used); | ||||
stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); | stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); | ||||
stats->etype_free = LE16_TO_CPU(resp->etype_free); | stats->etype_free = LE16_TO_CPU(resp->etype_free); | ||||
} | } | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control | * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @seid: VSI seid to add ethertype filter from | * @seid: VSI seid to add ethertype filter from | ||||
**/ | **/ | ||||
#define I40E_FLOW_CONTROL_ETHTYPE 0x8808 | |||||
void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, | void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, | ||||
u16 seid) | u16 seid) | ||||
{ | { | ||||
#define I40E_FLOW_CONTROL_ETHTYPE 0x8808 | |||||
u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | | u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | | ||||
I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | | I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | | ||||
I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; | I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; | ||||
u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; | u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; | ||||
enum i40e_status_code status; | enum i40e_status_code status; | ||||
status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, | status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, | ||||
seid, 0, TRUE, NULL, | seid, 0, TRUE, NULL, | ||||
▲ Show 20 Lines • Show All 414 Lines • ▼ Show 20 Lines | |||||
* @cluster_id: specific cluster to dump | * @cluster_id: specific cluster to dump | ||||
* @table_id: table id within cluster | * @table_id: table id within cluster | ||||
* @start_index: index of line in the block to read | * @start_index: index of line in the block to read | ||||
* @buff_size: dump buffer size | * @buff_size: dump buffer size | ||||
* @buff: dump buffer | * @buff: dump buffer | ||||
* @ret_buff_size: actual buffer size returned | * @ret_buff_size: actual buffer size returned | ||||
* @ret_next_table: next block to read | * @ret_next_table: next block to read | ||||
* @ret_next_index: next index to read | * @ret_next_index: next index to read | ||||
* @cmd_details: pointer to command details structure or NULL | |||||
* | * | ||||
* Dump internal FW/HW data for debug purposes. | * Dump internal FW/HW data for debug purposes. | ||||
* | * | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, | enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, | ||||
u8 table_id, u32 start_index, u16 buff_size, | u8 table_id, u32 start_index, u16 buff_size, | ||||
void *buff, u16 *ret_buff_size, | void *buff, u16 *ret_buff_size, | ||||
u8 *ret_next_table, u32 *ret_next_index, | u8 *ret_next_table, u32 *ret_next_index, | ||||
▲ Show 20 Lines • Show All 106 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw, | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_read_phy_register_clause22 | * i40e_read_phy_register_clause22 | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @reg: register address in the page | * @reg: register address in the page | ||||
* @phy_adr: PHY address on MDIO interface | * @phy_addr: PHY address on MDIO interface | ||||
* @value: PHY register value | * @value: PHY register value | ||||
* | * | ||||
* Reads specified PHY register value | * Reads specified PHY register value | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw, | enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw, | ||||
u16 reg, u8 phy_addr, u16 *value) | u16 reg, u8 phy_addr, u16 *value) | ||||
{ | { | ||||
enum i40e_status_code status = I40E_ERR_TIMEOUT; | enum i40e_status_code status = I40E_ERR_TIMEOUT; | ||||
Show All 28 Lines | enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw, | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_write_phy_register_clause22 | * i40e_write_phy_register_clause22 | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @reg: register address in the page | * @reg: register address in the page | ||||
* @phy_adr: PHY address on MDIO interface | * @phy_addr: PHY address on MDIO interface | ||||
* @value: PHY register value | * @value: PHY register value | ||||
* | * | ||||
* Writes specified PHY register value | * Writes specified PHY register value | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw, | enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw, | ||||
u16 reg, u8 phy_addr, u16 value) | u16 reg, u8 phy_addr, u16 value) | ||||
{ | { | ||||
enum i40e_status_code status = I40E_ERR_TIMEOUT; | enum i40e_status_code status = I40E_ERR_TIMEOUT; | ||||
Show All 24 Lines | enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw, | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_read_phy_register_clause45 | * i40e_read_phy_register_clause45 | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @page: registers page number | * @page: registers page number | ||||
* @reg: register address in the page | * @reg: register address in the page | ||||
* @phy_adr: PHY address on MDIO interface | * @phy_addr: PHY address on MDIO interface | ||||
* @value: PHY register value | * @value: PHY register value | ||||
* | * | ||||
* Reads specified PHY register value | * Reads specified PHY register value | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw, | enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw, | ||||
u8 page, u16 reg, u8 phy_addr, u16 *value) | u8 page, u16 reg, u8 phy_addr, u16 *value) | ||||
{ | { | ||||
enum i40e_status_code status = I40E_ERR_TIMEOUT; | enum i40e_status_code status = I40E_ERR_TIMEOUT; | ||||
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines | phy_read_end: | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_write_phy_register_clause45 | * i40e_write_phy_register_clause45 | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @page: registers page number | * @page: registers page number | ||||
* @reg: register address in the page | * @reg: register address in the page | ||||
* @phy_adr: PHY address on MDIO interface | * @phy_addr: PHY address on MDIO interface | ||||
* @value: PHY register value | * @value: PHY register value | ||||
* | * | ||||
* Writes value to specified PHY register | * Writes value to specified PHY register | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw, | enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw, | ||||
u8 page, u16 reg, u8 phy_addr, u16 value) | u8 page, u16 reg, u8 phy_addr, u16 value) | ||||
{ | { | ||||
enum i40e_status_code status = I40E_ERR_TIMEOUT; | enum i40e_status_code status = I40E_ERR_TIMEOUT; | ||||
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines | phy_write_end: | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_write_phy_register | * i40e_write_phy_register | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @page: registers page number | * @page: registers page number | ||||
* @reg: register address in the page | * @reg: register address in the page | ||||
* @phy_adr: PHY address on MDIO interface | * @phy_addr: PHY address on MDIO interface | ||||
* @value: PHY register value | * @value: PHY register value | ||||
* | * | ||||
* Writes value to specified PHY register | * Writes value to specified PHY register | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, | enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, | ||||
u8 page, u16 reg, u8 phy_addr, u16 value) | u8 page, u16 reg, u8 phy_addr, u16 value) | ||||
{ | { | ||||
enum i40e_status_code status; | enum i40e_status_code status; | ||||
Show All 19 Lines | enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_read_phy_register | * i40e_read_phy_register | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @page: registers page number | * @page: registers page number | ||||
* @reg: register address in the page | * @reg: register address in the page | ||||
* @phy_adr: PHY address on MDIO interface | * @phy_addr: PHY address on MDIO interface | ||||
* @value: PHY register value | * @value: PHY register value | ||||
* | * | ||||
* Reads specified PHY register value | * Reads specified PHY register value | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw, | enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw, | ||||
u8 page, u16 reg, u8 phy_addr, u16 *value) | u8 page, u16 reg, u8 phy_addr, u16 *value) | ||||
{ | { | ||||
enum i40e_status_code status; | enum i40e_status_code status; | ||||
Show All 18 Lines | enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw, | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_get_phy_address | * i40e_get_phy_address | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @dev_num: PHY port num that address we want | * @dev_num: PHY port num that address we want | ||||
* @phy_addr: Returned PHY address | |||||
* | * | ||||
* Gets PHY address for current port | * Gets PHY address for current port | ||||
**/ | **/ | ||||
u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) | u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) | ||||
{ | { | ||||
u8 port_num = (u8)hw->func_caps.mdio_port_num; | u8 port_num = (u8)hw->func_caps.mdio_port_num; | ||||
u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); | u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); | ||||
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines | status = i40e_write_phy_register_clause45(hw, | ||||
I40E_PHY_COM_REG_PAGE, | I40E_PHY_COM_REG_PAGE, | ||||
led_addr, phy_addr, led_ctl); | led_addr, phy_addr, led_ctl); | ||||
phy_blinking_end: | phy_blinking_end: | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_led_get_reg - read LED register | |||||
* @hw: pointer to the HW structure | |||||
* @led_addr: LED register address | |||||
* @reg_val: read register value | |||||
**/ | |||||
static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, | |||||
u32 *reg_val) | |||||
{ | |||||
enum i40e_status_code status; | |||||
u8 phy_addr = 0; | |||||
*reg_val = 0; | |||||
if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { | |||||
status = i40e_aq_get_phy_register(hw, | |||||
I40E_AQ_PHY_REG_ACCESS_EXTERNAL, | |||||
I40E_PHY_COM_REG_PAGE, | |||||
I40E_PHY_LED_PROV_REG_1, | |||||
reg_val, NULL); | |||||
} else { | |||||
phy_addr = i40e_get_phy_address(hw, hw->port); | |||||
status = i40e_read_phy_register_clause45(hw, | |||||
I40E_PHY_COM_REG_PAGE, | |||||
led_addr, phy_addr, | |||||
(u16 *)reg_val); | |||||
} | |||||
return status; | |||||
} | |||||
/** | |||||
* i40e_led_set_reg - write LED register | |||||
* @hw: pointer to the HW structure | |||||
* @led_addr: LED register address | |||||
* @reg_val: register value to write | |||||
**/ | |||||
static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, | |||||
u32 reg_val) | |||||
{ | |||||
enum i40e_status_code status; | |||||
u8 phy_addr = 0; | |||||
if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { | |||||
status = i40e_aq_set_phy_register(hw, | |||||
I40E_AQ_PHY_REG_ACCESS_EXTERNAL, | |||||
I40E_PHY_COM_REG_PAGE, | |||||
I40E_PHY_LED_PROV_REG_1, | |||||
reg_val, NULL); | |||||
} else { | |||||
phy_addr = i40e_get_phy_address(hw, hw->port); | |||||
status = i40e_write_phy_register_clause45(hw, | |||||
I40E_PHY_COM_REG_PAGE, | |||||
led_addr, phy_addr, | |||||
(u16)reg_val); | |||||
} | |||||
return status; | |||||
} | |||||
/** | |||||
* i40e_led_get_phy - return current on/off mode | * i40e_led_get_phy - return current on/off mode | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @led_addr: address of led register to use | * @led_addr: address of led register to use | ||||
* @val: original value of register to use | * @val: original value of register to use | ||||
* | * | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, | enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, | ||||
u16 *val) | u16 *val) | ||||
{ | { | ||||
enum i40e_status_code status = I40E_SUCCESS; | enum i40e_status_code status = I40E_SUCCESS; | ||||
u16 gpio_led_port; | u16 gpio_led_port; | ||||
u32 reg_val_aq; | |||||
u16 temp_addr; | |||||
u8 phy_addr = 0; | u8 phy_addr = 0; | ||||
u16 reg_val; | u16 reg_val; | ||||
u16 temp_addr; | |||||
u8 port_num; | |||||
u32 i; | |||||
if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { | |||||
status = i40e_aq_get_phy_register(hw, | |||||
I40E_AQ_PHY_REG_ACCESS_EXTERNAL, | |||||
I40E_PHY_COM_REG_PAGE, | |||||
I40E_PHY_LED_PROV_REG_1, | |||||
®_val_aq, NULL); | |||||
if (status == I40E_SUCCESS) | |||||
*val = (u16)reg_val_aq; | |||||
return status; | |||||
} | |||||
temp_addr = I40E_PHY_LED_PROV_REG_1; | temp_addr = I40E_PHY_LED_PROV_REG_1; | ||||
i = rd32(hw, I40E_PFGEN_PORTNUM); | phy_addr = i40e_get_phy_address(hw, hw->port); | ||||
port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); | |||||
phy_addr = i40e_get_phy_address(hw, port_num); | |||||
for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, | for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, | ||||
temp_addr++) { | temp_addr++) { | ||||
status = i40e_read_phy_register_clause45(hw, | status = i40e_read_phy_register_clause45(hw, | ||||
I40E_PHY_COM_REG_PAGE, | I40E_PHY_COM_REG_PAGE, | ||||
temp_addr, phy_addr, | temp_addr, phy_addr, | ||||
®_val); | ®_val); | ||||
if (status) | if (status) | ||||
return status; | return status; | ||||
*val = reg_val; | *val = reg_val; | ||||
if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { | if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { | ||||
*led_addr = temp_addr; | *led_addr = temp_addr; | ||||
break; | break; | ||||
} | } | ||||
} | } | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_led_set_phy | * i40e_led_set_phy | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @on: TRUE or FALSE | * @on: TRUE or FALSE | ||||
* @led_addr: address of led register to use | |||||
* @mode: original val plus bit for set or ignore | * @mode: original val plus bit for set or ignore | ||||
* | |||||
* Set led's on or off when controlled by the PHY | * Set led's on or off when controlled by the PHY | ||||
* | * | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on, | enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on, | ||||
u16 led_addr, u32 mode) | u16 led_addr, u32 mode) | ||||
{ | { | ||||
enum i40e_status_code status = I40E_SUCCESS; | enum i40e_status_code status = I40E_SUCCESS; | ||||
u16 led_ctl = 0; | u32 led_ctl = 0; | ||||
u16 led_reg = 0; | u32 led_reg = 0; | ||||
u8 phy_addr = 0; | |||||
u8 port_num; | |||||
u32 i; | |||||
i = rd32(hw, I40E_PFGEN_PORTNUM); | status = i40e_led_get_reg(hw, led_addr, &led_reg); | ||||
port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); | |||||
phy_addr = i40e_get_phy_address(hw, port_num); | |||||
status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, | |||||
led_addr, phy_addr, &led_reg); | |||||
if (status) | if (status) | ||||
return status; | return status; | ||||
led_ctl = led_reg; | led_ctl = led_reg; | ||||
if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { | if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { | ||||
led_reg = 0; | led_reg = 0; | ||||
status = i40e_write_phy_register_clause45(hw, | status = i40e_led_set_reg(hw, led_addr, led_reg); | ||||
I40E_PHY_COM_REG_PAGE, | |||||
led_addr, phy_addr, | |||||
led_reg); | |||||
if (status) | if (status) | ||||
return status; | return status; | ||||
} | } | ||||
status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, | status = i40e_led_get_reg(hw, led_addr, &led_reg); | ||||
led_addr, phy_addr, &led_reg); | |||||
if (status) | if (status) | ||||
goto restore_config; | goto restore_config; | ||||
if (on) | if (on) | ||||
led_reg = I40E_PHY_LED_MANUAL_ON; | led_reg = I40E_PHY_LED_MANUAL_ON; | ||||
else | else | ||||
led_reg = 0; | led_reg = 0; | ||||
status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, | status = i40e_led_set_reg(hw, led_addr, led_reg); | ||||
led_addr, phy_addr, led_reg); | |||||
if (status) | if (status) | ||||
goto restore_config; | goto restore_config; | ||||
if (mode & I40E_PHY_LED_MODE_ORIG) { | if (mode & I40E_PHY_LED_MODE_ORIG) { | ||||
led_ctl = (mode & I40E_PHY_LED_MODE_MASK); | led_ctl = (mode & I40E_PHY_LED_MODE_MASK); | ||||
status = i40e_write_phy_register_clause45(hw, | status = i40e_led_set_reg(hw, led_addr, led_ctl); | ||||
I40E_PHY_COM_REG_PAGE, | |||||
led_addr, phy_addr, led_ctl); | |||||
} | } | ||||
return status; | return status; | ||||
restore_config: | restore_config: | ||||
status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE, | status = i40e_led_set_reg(hw, led_addr, led_ctl); | ||||
led_addr, phy_addr, led_ctl); | |||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register | * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register | ||||
* @hw: pointer to the hw struct | * @hw: pointer to the hw struct | ||||
* @reg_addr: register address | * @reg_addr: register address | ||||
* @reg_val: ptr to register value | * @reg_val: ptr to register value | ||||
Show All 33 Lines | |||||
**/ | **/ | ||||
u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) | u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) | ||||
{ | { | ||||
enum i40e_status_code status = I40E_SUCCESS; | enum i40e_status_code status = I40E_SUCCESS; | ||||
bool use_register; | bool use_register; | ||||
int retry = 5; | int retry = 5; | ||||
u32 val = 0; | u32 val = 0; | ||||
use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5); | use_register = (((hw->aq.api_maj_ver == 1) && | ||||
(hw->aq.api_min_ver < 5)) || | |||||
(hw->mac.type == I40E_MAC_X722)); | |||||
if (!use_register) { | if (!use_register) { | ||||
do_retry: | do_retry: | ||||
status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); | status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); | ||||
if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { | if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { | ||||
i40e_msec_delay(1); | i40e_msec_delay(1); | ||||
retry--; | retry--; | ||||
goto do_retry; | goto do_retry; | ||||
} | } | ||||
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines | |||||
* @reg_val: register value | * @reg_val: register value | ||||
**/ | **/ | ||||
void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) | void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) | ||||
{ | { | ||||
enum i40e_status_code status = I40E_SUCCESS; | enum i40e_status_code status = I40E_SUCCESS; | ||||
bool use_register; | bool use_register; | ||||
int retry = 5; | int retry = 5; | ||||
use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5); | use_register = (((hw->aq.api_maj_ver == 1) && | ||||
(hw->aq.api_min_ver < 5)) || | |||||
(hw->mac.type == I40E_MAC_X722)); | |||||
if (!use_register) { | if (!use_register) { | ||||
do_retry: | do_retry: | ||||
status = i40e_aq_rx_ctl_write_register(hw, reg_addr, | status = i40e_aq_rx_ctl_write_register(hw, reg_addr, | ||||
reg_val, NULL); | reg_val, NULL); | ||||
if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { | if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { | ||||
i40e_msec_delay(1); | i40e_msec_delay(1); | ||||
retry--; | retry--; | ||||
goto do_retry; | goto do_retry; | ||||
} | } | ||||
} | } | ||||
/* if the AQ access failed, try the old-fashioned way */ | /* if the AQ access failed, try the old-fashioned way */ | ||||
if (status || use_register) | if (status || use_register) | ||||
wr32(hw, reg_addr, reg_val); | wr32(hw, reg_addr, reg_val); | ||||
} | } | ||||
/** | /** | ||||
* i40e_aq_set_phy_register | |||||
* @hw: pointer to the hw struct | |||||
* @phy_select: select which phy should be accessed | |||||
* @dev_addr: PHY device address | |||||
* @reg_addr: PHY register address | |||||
* @reg_val: new register value | |||||
* @cmd_details: pointer to command details structure or NULL | |||||
* | |||||
* Write the external PHY register. | |||||
**/ | |||||
enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw, | |||||
u8 phy_select, u8 dev_addr, | |||||
u32 reg_addr, u32 reg_val, | |||||
struct i40e_asq_cmd_details *cmd_details) | |||||
{ | |||||
struct i40e_aq_desc desc; | |||||
struct i40e_aqc_phy_register_access *cmd = | |||||
(struct i40e_aqc_phy_register_access *)&desc.params.raw; | |||||
enum i40e_status_code status; | |||||
i40e_fill_default_direct_cmd_desc(&desc, | |||||
i40e_aqc_opc_set_phy_register); | |||||
cmd->phy_interface = phy_select; | |||||
cmd->dev_addres = dev_addr; | |||||
cmd->reg_address = CPU_TO_LE32(reg_addr); | |||||
cmd->reg_value = CPU_TO_LE32(reg_val); | |||||
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |||||
return status; | |||||
} | |||||
/** | |||||
* i40e_aq_get_phy_register | |||||
* @hw: pointer to the hw struct | |||||
* @phy_select: select which phy should be accessed | |||||
* @dev_addr: PHY device address | |||||
* @reg_addr: PHY register address | |||||
* @reg_val: read register value | |||||
* @cmd_details: pointer to command details structure or NULL | |||||
* | |||||
* Read the external PHY register. | |||||
**/ | |||||
enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw, | |||||
u8 phy_select, u8 dev_addr, | |||||
u32 reg_addr, u32 *reg_val, | |||||
struct i40e_asq_cmd_details *cmd_details) | |||||
{ | |||||
struct i40e_aq_desc desc; | |||||
struct i40e_aqc_phy_register_access *cmd = | |||||
(struct i40e_aqc_phy_register_access *)&desc.params.raw; | |||||
enum i40e_status_code status; | |||||
i40e_fill_default_direct_cmd_desc(&desc, | |||||
i40e_aqc_opc_get_phy_register); | |||||
cmd->phy_interface = phy_select; | |||||
cmd->dev_addres = dev_addr; | |||||
cmd->reg_address = CPU_TO_LE32(reg_addr); | |||||
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); | |||||
if (!status) | |||||
*reg_val = LE32_TO_CPU(cmd->reg_value); | |||||
return status; | |||||
} | |||||
/** | |||||
* i40e_aq_send_msg_to_pf | * i40e_aq_send_msg_to_pf | ||||
* @hw: pointer to the hardware structure | * @hw: pointer to the hardware structure | ||||
* @v_opcode: opcodes for VF-PF communication | * @v_opcode: opcodes for VF-PF communication | ||||
* @v_retval: return error code | * @v_retval: return error code | ||||
* @msg: pointer to the msg buffer | * @msg: pointer to the msg buffer | ||||
* @msglen: msg length | * @msglen: msg length | ||||
* @cmd_details: pointer to command details | * @cmd_details: pointer to command details | ||||
* | * | ||||
* Send message to PF driver using admin queue. By default, this message | * Send message to PF driver using admin queue. By default, this message | ||||
* is sent asynchronously, i.e. i40e_asq_send_command() does not wait for | * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for | ||||
* completion before returning. | * completion before returning. | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw, | enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw, | ||||
enum i40e_virtchnl_ops v_opcode, | enum virtchnl_ops v_opcode, | ||||
enum i40e_status_code v_retval, | enum i40e_status_code v_retval, | ||||
u8 *msg, u16 msglen, | u8 *msg, u16 msglen, | ||||
struct i40e_asq_cmd_details *cmd_details) | struct i40e_asq_cmd_details *cmd_details) | ||||
{ | { | ||||
struct i40e_aq_desc desc; | struct i40e_aq_desc desc; | ||||
struct i40e_asq_cmd_details details; | struct i40e_asq_cmd_details details; | ||||
enum i40e_status_code status; | enum i40e_status_code status; | ||||
Show All 22 Lines | |||||
* i40e_vf_parse_hw_config | * i40e_vf_parse_hw_config | ||||
* @hw: pointer to the hardware structure | * @hw: pointer to the hardware structure | ||||
* @msg: pointer to the virtual channel VF resource structure | * @msg: pointer to the virtual channel VF resource structure | ||||
* | * | ||||
* Given a VF resource message from the PF, populate the hw struct | * Given a VF resource message from the PF, populate the hw struct | ||||
* with appropriate information. | * with appropriate information. | ||||
**/ | **/ | ||||
void i40e_vf_parse_hw_config(struct i40e_hw *hw, | void i40e_vf_parse_hw_config(struct i40e_hw *hw, | ||||
struct i40e_virtchnl_vf_resource *msg) | struct virtchnl_vf_resource *msg) | ||||
{ | { | ||||
struct i40e_virtchnl_vsi_resource *vsi_res; | struct virtchnl_vsi_resource *vsi_res; | ||||
int i; | int i; | ||||
vsi_res = &msg->vsi_res[0]; | vsi_res = &msg->vsi_res[0]; | ||||
hw->dev_caps.num_vsis = msg->num_vsis; | hw->dev_caps.num_vsis = msg->num_vsis; | ||||
hw->dev_caps.num_rx_qp = msg->num_queue_pairs; | hw->dev_caps.num_rx_qp = msg->num_queue_pairs; | ||||
hw->dev_caps.num_tx_qp = msg->num_queue_pairs; | hw->dev_caps.num_tx_qp = msg->num_queue_pairs; | ||||
hw->dev_caps.num_msix_vectors_vf = msg->max_vectors; | hw->dev_caps.num_msix_vectors_vf = msg->max_vectors; | ||||
hw->dev_caps.dcb = msg->vf_offload_flags & | hw->dev_caps.dcb = msg->vf_cap_flags & | ||||
I40E_VIRTCHNL_VF_OFFLOAD_L2; | VIRTCHNL_VF_OFFLOAD_L2; | ||||
hw->dev_caps.fcoe = (msg->vf_offload_flags & | hw->dev_caps.iwarp = (msg->vf_cap_flags & | ||||
I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0; | VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0; | ||||
hw->dev_caps.iwarp = (msg->vf_offload_flags & | |||||
I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0; | |||||
for (i = 0; i < msg->num_vsis; i++) { | for (i = 0; i < msg->num_vsis; i++) { | ||||
if (vsi_res->vsi_type == I40E_VSI_SRIOV) { | if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) { | ||||
i40e_memcpy(hw->mac.perm_addr, | i40e_memcpy(hw->mac.perm_addr, | ||||
vsi_res->default_mac_addr, | vsi_res->default_mac_addr, | ||||
I40E_ETH_LENGTH_OF_ADDRESS, | ETH_ALEN, | ||||
I40E_NONDMA_TO_NONDMA); | I40E_NONDMA_TO_NONDMA); | ||||
i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr, | i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr, | ||||
I40E_ETH_LENGTH_OF_ADDRESS, | ETH_ALEN, | ||||
I40E_NONDMA_TO_NONDMA); | I40E_NONDMA_TO_NONDMA); | ||||
} | } | ||||
vsi_res++; | vsi_res++; | ||||
} | } | ||||
} | } | ||||
/** | /** | ||||
* i40e_vf_reset | * i40e_vf_reset | ||||
* @hw: pointer to the hardware structure | * @hw: pointer to the hardware structure | ||||
* | * | ||||
* Send a VF_RESET message to the PF. Does not wait for response from PF | * Send a VF_RESET message to the PF. Does not wait for response from PF | ||||
* as none will be forthcoming. Immediately after calling this function, | * as none will be forthcoming. Immediately after calling this function, | ||||
* the admin queue should be shut down and (optionally) reinitialized. | * the admin queue should be shut down and (optionally) reinitialized. | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw) | enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw) | ||||
{ | { | ||||
return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF, | return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF, | ||||
I40E_SUCCESS, NULL, 0, NULL); | I40E_SUCCESS, NULL, 0, NULL); | ||||
} | } | ||||
/** | /** | ||||
* i40e_aq_set_arp_proxy_config | * i40e_aq_set_arp_proxy_config | ||||
* @hw: pointer to the HW structure | * @hw: pointer to the HW structure | ||||
* @proxy_config - pointer to proxy config command table struct | * @proxy_config: pointer to proxy config command table struct | ||||
* @cmd_details: pointer to command details | * @cmd_details: pointer to command details | ||||
* | * | ||||
* Set ARP offload parameters from pre-populated | * Set ARP offload parameters from pre-populated | ||||
* i40e_aqc_arp_proxy_data struct | * i40e_aqc_arp_proxy_data struct | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw, | enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw, | ||||
struct i40e_aqc_arp_proxy_data *proxy_config, | struct i40e_aqc_arp_proxy_data *proxy_config, | ||||
struct i40e_asq_cmd_details *cmd_details) | struct i40e_asq_cmd_details *cmd_details) | ||||
▲ Show 20 Lines • Show All 177 Lines • Show Last 20 Lines |