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head/sys/amd64/include/vmm_dev.h
Show First 20 Lines • Show All 203 Lines • ▼ Show 20 Lines | |||||
struct vm_cpuset { | struct vm_cpuset { | ||||
int which; | int which; | ||||
int cpusetsize; | int cpusetsize; | ||||
cpuset_t *cpus; | cpuset_t *cpus; | ||||
}; | }; | ||||
#define VM_ACTIVE_CPUS 0 | #define VM_ACTIVE_CPUS 0 | ||||
#define VM_SUSPENDED_CPUS 1 | #define VM_SUSPENDED_CPUS 1 | ||||
#define VM_DEBUG_CPUS 2 | |||||
struct vm_intinfo { | struct vm_intinfo { | ||||
int vcpuid; | int vcpuid; | ||||
uint64_t info1; | uint64_t info1; | ||||
uint64_t info2; | uint64_t info2; | ||||
}; | }; | ||||
struct vm_rtc_time { | struct vm_rtc_time { | ||||
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines | enum { | ||||
IOCNUM_ISA_ASSERT_IRQ = 80, | IOCNUM_ISA_ASSERT_IRQ = 80, | ||||
IOCNUM_ISA_DEASSERT_IRQ = 81, | IOCNUM_ISA_DEASSERT_IRQ = 81, | ||||
IOCNUM_ISA_PULSE_IRQ = 82, | IOCNUM_ISA_PULSE_IRQ = 82, | ||||
IOCNUM_ISA_SET_IRQ_TRIGGER = 83, | IOCNUM_ISA_SET_IRQ_TRIGGER = 83, | ||||
/* vm_cpuset */ | /* vm_cpuset */ | ||||
IOCNUM_ACTIVATE_CPU = 90, | IOCNUM_ACTIVATE_CPU = 90, | ||||
IOCNUM_GET_CPUSET = 91, | IOCNUM_GET_CPUSET = 91, | ||||
IOCNUM_SUSPEND_CPU = 92, | |||||
IOCNUM_RESUME_CPU = 93, | |||||
/* RTC */ | /* RTC */ | ||||
IOCNUM_RTC_READ = 100, | IOCNUM_RTC_READ = 100, | ||||
IOCNUM_RTC_WRITE = 101, | IOCNUM_RTC_WRITE = 101, | ||||
IOCNUM_RTC_SETTIME = 102, | IOCNUM_RTC_SETTIME = 102, | ||||
IOCNUM_RTC_GETTIME = 103, | IOCNUM_RTC_GETTIME = 103, | ||||
}; | }; | ||||
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines | |||||
#define VM_GLA2GPA \ | #define VM_GLA2GPA \ | ||||
_IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa) | _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa) | ||||
#define VM_GLA2GPA_NOFAULT \ | #define VM_GLA2GPA_NOFAULT \ | ||||
_IOWR('v', IOCNUM_GLA2GPA_NOFAULT, struct vm_gla2gpa) | _IOWR('v', IOCNUM_GLA2GPA_NOFAULT, struct vm_gla2gpa) | ||||
#define VM_ACTIVATE_CPU \ | #define VM_ACTIVATE_CPU \ | ||||
_IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu) | _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu) | ||||
#define VM_GET_CPUS \ | #define VM_GET_CPUS \ | ||||
_IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset) | _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset) | ||||
#define VM_SUSPEND_CPU \ | |||||
_IOW('v', IOCNUM_SUSPEND_CPU, struct vm_activate_cpu) | |||||
#define VM_RESUME_CPU \ | |||||
_IOW('v', IOCNUM_RESUME_CPU, struct vm_activate_cpu) | |||||
#define VM_SET_INTINFO \ | #define VM_SET_INTINFO \ | ||||
_IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo) | _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo) | ||||
#define VM_GET_INTINFO \ | #define VM_GET_INTINFO \ | ||||
_IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo) | _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo) | ||||
#define VM_RTC_WRITE \ | #define VM_RTC_WRITE \ | ||||
_IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data) | _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data) | ||||
#define VM_RTC_READ \ | #define VM_RTC_READ \ | ||||
_IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data) | _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data) | ||||
#define VM_RTC_SETTIME \ | #define VM_RTC_SETTIME \ | ||||
_IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time) | _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time) | ||||
#define VM_RTC_GETTIME \ | #define VM_RTC_GETTIME \ | ||||
_IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time) | _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time) | ||||
#define VM_RESTART_INSTRUCTION \ | #define VM_RESTART_INSTRUCTION \ | ||||
_IOW('v', IOCNUM_RESTART_INSTRUCTION, int) | _IOW('v', IOCNUM_RESTART_INSTRUCTION, int) | ||||
#endif | #endif |