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head/sys/dts/arm/armada-385.dtsi
| Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines | pcie-controller { | ||||
| */ | */ | ||||
| pcie@1,0 { | pcie@1,0 { | ||||
| device_type = "pci"; | device_type = "pci"; | ||||
| assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; | assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; | ||||
| reg = <0x0800 0 0 0 0>; | reg = <0x0800 0 0 0 0>; | ||||
| #address-cells = <3>; | #address-cells = <3>; | ||||
| #size-cells = <2>; | #size-cells = <2>; | ||||
| #interrupt-cells = <1>; | #interrupt-cells = <1>; | ||||
| ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1200000 0x0 0x00100000 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 | ||||
| 0x81000000 0x0 0x0 0x81000000 0x0 0xf1300000 0x0 0x00100000>; | 0x81000000 0 0 0x81000000 0x1 0 1 0>; | ||||
| interrupt-map-mask = <0 0 0 0>; | interrupt-map-mask = <0 0 0 0>; | ||||
| interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | ||||
| marvell,pcie-port = <0>; | marvell,pcie-port = <0>; | ||||
| marvell,pcie-lane = <0>; | marvell,pcie-lane = <0>; | ||||
| clocks = <&gateclk 8>; | clocks = <&gateclk 8>; | ||||
| status = "disabled"; | status = "disabled"; | ||||
| }; | }; | ||||
| /* x1 port */ | /* x1 port */ | ||||
| pcie@2,0 { | pcie@2,0 { | ||||
| device_type = "pci"; | device_type = "pci"; | ||||
| assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; | ||||
| reg = <0x1000 0 0 0 0>; | reg = <0x1000 0 0 0 0>; | ||||
| #address-cells = <3>; | #address-cells = <3>; | ||||
| #size-cells = <2>; | #size-cells = <2>; | ||||
| #interrupt-cells = <1>; | #interrupt-cells = <1>; | ||||
| ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1400000 0x0 0x00100000 | ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 | ||||
| 0x81000000 0x0 0x0 0x81000000 0x0 0xf1500000 0x0 0x00100000>; | 0x81000000 0 0 0x81000000 0x2 0 1 0>; | ||||
| interrupt-map-mask = <0 0 0 0>; | interrupt-map-mask = <0 0 0 0>; | ||||
| interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | ||||
| marvell,pcie-port = <1>; | marvell,pcie-port = <1>; | ||||
| marvell,pcie-lane = <0>; | marvell,pcie-lane = <0>; | ||||
| clocks = <&gateclk 5>; | clocks = <&gateclk 5>; | ||||
| status = "disabled"; | status = "disabled"; | ||||
| }; | }; | ||||
| /* x1 port */ | /* x1 port */ | ||||
| pcie@3,0 { | pcie@3,0 { | ||||
| device_type = "pci"; | device_type = "pci"; | ||||
| assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; | ||||
| reg = <0x1800 0 0 0 0>; | reg = <0x1800 0 0 0 0>; | ||||
| #address-cells = <3>; | #address-cells = <3>; | ||||
| #size-cells = <2>; | #size-cells = <2>; | ||||
| #interrupt-cells = <1>; | #interrupt-cells = <1>; | ||||
| ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1600000 0x0 0x00100000 | ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 | ||||
| 0x81000000 0x0 0x0 0x81000000 0x0 0xf1700000 0x0 0x00100000>; | 0x81000000 0 0 0x81000000 0x3 0 1 0>; | ||||
| interrupt-map-mask = <0 0 0 0>; | interrupt-map-mask = <0 0 0 0>; | ||||
| interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; | interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; | ||||
| marvell,pcie-port = <2>; | marvell,pcie-port = <2>; | ||||
| marvell,pcie-lane = <0>; | marvell,pcie-lane = <0>; | ||||
| clocks = <&gateclk 6>; | clocks = <&gateclk 6>; | ||||
| status = "disabled"; | status = "disabled"; | ||||
| }; | }; | ||||
| /* | /* | ||||
| * x1 port only available when pcie@1,0 is | * x1 port only available when pcie@1,0 is | ||||
| * configured as a x1 port | * configured as a x1 port | ||||
| */ | */ | ||||
| pcie@4,0 { | pcie@4,0 { | ||||
| device_type = "pci"; | device_type = "pci"; | ||||
| assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; | assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; | ||||
| reg = <0x2000 0 0 0 0>; | reg = <0x2000 0 0 0 0>; | ||||
| #address-cells = <3>; | #address-cells = <3>; | ||||
| #size-cells = <2>; | #size-cells = <2>; | ||||
| #interrupt-cells = <1>; | #interrupt-cells = <1>; | ||||
| ranges = <0x82000000 0x0 0x0 0x82000000 0x0 0xf1800000 0x0 0x00100000 | ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 | ||||
| 0x81000000 0x0 0x0 0x81000000 0x0 0xf1900000 0x0 0x00100000>; | 0x81000000 0 0 0x81000000 0x4 0 1 0>; | ||||
| interrupt-map-mask = <0 0 0 0>; | interrupt-map-mask = <0 0 0 0>; | ||||
| interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | ||||
| marvell,pcie-port = <3>; | marvell,pcie-port = <3>; | ||||
| marvell,pcie-lane = <0>; | marvell,pcie-lane = <0>; | ||||
| clocks = <&gateclk 7>; | clocks = <&gateclk 7>; | ||||
| status = "disabled"; | status = "disabled"; | ||||
| }; | }; | ||||
| }; | }; | ||||
| }; | }; | ||||
| }; | }; | ||||