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head/sys/arm/mv/timer.c
Show First 20 Lines • Show All 405 Lines • ▼ Show 20 Lines | mv_watchdog_enable_armadaxp(void) | ||||
irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); | irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); | ||||
irq_cause &= IRQ_TIMER_WD_CLR; | irq_cause &= IRQ_TIMER_WD_CLR; | ||||
write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); | write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); | ||||
val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); | val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); | ||||
val |= (WD_GLOBAL_MASK | WD_CPU0_MASK); | val |= (WD_GLOBAL_MASK | WD_CPU0_MASK); | ||||
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); | write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); | ||||
val = read_cpu_misc(RSTOUTn_MASK); | val = read_cpu_misc(RSTOUTn_MASK_ARMV7); | ||||
val &= ~RSTOUTn_MASK_WD; | val &= ~RSTOUTn_MASK_WD; | ||||
write_cpu_misc(RSTOUTn_MASK, val); | write_cpu_misc(RSTOUTn_MASK_ARMV7, val); | ||||
val = mv_get_timer_control(); | val = mv_get_timer_control(); | ||||
val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN; | val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN; | ||||
mv_set_timer_control(val); | mv_set_timer_control(val); | ||||
} | } | ||||
static void | static void | ||||
mv_watchdog_disable_armv5(void) | mv_watchdog_disable_armv5(void) | ||||
Show All 21 Lines | |||||
mv_watchdog_disable_armadaxp(void) | mv_watchdog_disable_armadaxp(void) | ||||
{ | { | ||||
uint32_t val, irq_cause; | uint32_t val, irq_cause; | ||||
val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); | val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); | ||||
val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK); | val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK); | ||||
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); | write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); | ||||
val = read_cpu_misc(RSTOUTn_MASK); | val = read_cpu_misc(RSTOUTn_MASK_ARMV7); | ||||
val |= RSTOUTn_MASK_WD; | val |= RSTOUTn_MASK_WD; | ||||
write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD); | write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD); | ||||
irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); | irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); | ||||
irq_cause &= IRQ_TIMER_WD_CLR; | irq_cause &= IRQ_TIMER_WD_CLR; | ||||
write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); | write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); | ||||
val = mv_get_timer_control(); | val = mv_get_timer_control(); | ||||
val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); | val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); | ||||
mv_set_timer_control(val); | mv_set_timer_control(val); | ||||
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