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head/sys/arm/mv/mvreg.h
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#define IRQ_CPU_SELF_CLR (~IRQ_CPU_SELF) | #define IRQ_CPU_SELF_CLR (~IRQ_CPU_SELF) | ||||
#define IRQ_TIMER0_CLR (~IRQ_TIMER0) | #define IRQ_TIMER0_CLR (~IRQ_TIMER0) | ||||
#define IRQ_TIMER1_CLR (~IRQ_TIMER1) | #define IRQ_TIMER1_CLR (~IRQ_TIMER1) | ||||
#define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) | #define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) | ||||
/* | /* | ||||
* System reset | * System reset | ||||
*/ | */ | ||||
#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) | #define RSTOUTn_MASK_ARMV7 0x60 | ||||
#define RSTOUTn_MASK 0x60 | #define SYSTEM_SOFT_RESET_ARMV7 0x64 | ||||
#define SYSTEM_SOFT_RESET 0x64 | #define SOFT_RST_OUT_EN_ARMV7 0x00000001 | ||||
#define SOFT_RST_OUT_EN 0x00000001 | #define SYS_SOFT_RST_ARMV7 0x00000001 | ||||
#define SYS_SOFT_RST 0x00000001 | |||||
#else | |||||
#define RSTOUTn_MASK 0x8 | #define RSTOUTn_MASK 0x8 | ||||
#define SOFT_RST_OUT_EN 0x00000004 | #define SOFT_RST_OUT_EN 0x00000004 | ||||
#define SYSTEM_SOFT_RESET 0xc | #define SYSTEM_SOFT_RESET 0xc | ||||
#define SYS_SOFT_RST 0x00000001 | #define SYS_SOFT_RST 0x00000001 | ||||
#endif | |||||
#define RSTOUTn_MASK_WD 0x400 | #define RSTOUTn_MASK_WD 0x400 | ||||
#define WD_RSTOUTn_MASK 0x4 | #define WD_RSTOUTn_MASK 0x4 | ||||
#define WD_GLOBAL_MASK 0x00000100 | #define WD_GLOBAL_MASK 0x00000100 | ||||
#define WD_CPU0_MASK 0x00000001 | #define WD_CPU0_MASK 0x00000001 | ||||
#define WD_RST_OUT_EN 0x00000002 | #define WD_RST_OUT_EN 0x00000002 | ||||
/* | /* | ||||
* Power Control | * Power Control | ||||
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