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head/sys/arm/mv/mvwin.h
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#define MV_DEV_CS2_BASE 0xFB500000 | #define MV_DEV_CS2_BASE 0xFB500000 | ||||
#define MV_DEV_CS2_SIZE (1024 * 1024) /* 1 MB */ | #define MV_DEV_CS2_SIZE (1024 * 1024) /* 1 MB */ | ||||
/* | /* | ||||
* Integrated SoC peripherals addresses | * Integrated SoC peripherals addresses | ||||
*/ | */ | ||||
#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ | #define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ | ||||
#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) | #define MV_DDR_CADR_BASE_ARMV7 (MV_BASE + 0x20180) | ||||
#define MV_DDR_CADR_BASE (MV_BASE + 0x20180) | |||||
#else | |||||
#define MV_DDR_CADR_BASE (MV_BASE + 0x1500) | #define MV_DDR_CADR_BASE (MV_BASE + 0x1500) | ||||
#endif | |||||
#define MV_MPP_BASE (MV_BASE + 0x10000) | #define MV_MPP_BASE (MV_BASE + 0x10000) | ||||
#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) | |||||
#define MV_MISC_BASE (MV_BASE + 0x18200) | #define MV_MISC_BASE (MV_BASE + 0x18200) | ||||
#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) | #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) | ||||
#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) | #define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) | ||||
#define MV_MP_CLOCKS_BASE (MV_MBUS_BRIDGE_BASE + 0x700) | #define MV_MP_CLOCKS_BASE (MV_MBUS_BRIDGE_BASE + 0x700) | ||||
#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x1800) | |||||
#else | #define MV_CPU_CONTROL_BASE_ARMV7 (MV_MBUS_BRIDGE_BASE + 0x1800) | ||||
#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) | |||||
#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) | |||||
#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) | #define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) | ||||
#endif | |||||
#define MV_PCI_BASE (MV_BASE + 0x30000) | #define MV_PCI_BASE (MV_BASE + 0x30000) | ||||
#define MV_PCI_SIZE 0x2000 | #define MV_PCI_SIZE 0x2000 | ||||
#define MV_PCIE_BASE_ARMADA38X (MV_BASE + 0x80000) | #define MV_PCIE_BASE_ARMADA38X (MV_BASE + 0x80000) | ||||
#define MV_PCIE_BASE (MV_BASE + 0x40000) | #define MV_PCIE_BASE (MV_BASE + 0x40000) | ||||
#define MV_PCIE_SIZE 0x2000 | #define MV_PCIE_SIZE 0x2000 | ||||
#define MV_SDIO_BASE (MV_BASE + 0x90000) | #define MV_SDIO_BASE (MV_BASE + 0x90000) | ||||
#define MV_SDIO_SIZE 0x10000 | #define MV_SDIO_SIZE 0x10000 | ||||
/* | /* | ||||
* Decode windows definitions and macros | * Decode windows definitions and macros | ||||
*/ | */ | ||||
#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) | #define MV_WIN_CPU_CTRL_ARMV7(n) (((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) | ||||
#define MV_WIN_CPU_CTRL(n) (((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) | #define MV_WIN_CPU_BASE_ARMV7(n) ((((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) + 0x4) | ||||
#define MV_WIN_CPU_BASE(n) ((((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) + 0x4) | #define MV_WIN_CPU_REMAP_LO_ARMV7(n) (0x10 * (n) + 0x008) | ||||
#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + 0x008) | #define MV_WIN_CPU_REMAP_HI_ARMV7(n) (0x10 * (n) + 0x00C) | ||||
#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + 0x00C) | |||||
#else | |||||
#define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) | |||||
#define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) | |||||
#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) | |||||
#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) | |||||
#endif | |||||
#define MV_WIN_CPU_CTRL_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) | |||||
#define MV_WIN_CPU_BASE_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) | |||||
#define MV_WIN_CPU_REMAP_LO_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) | |||||
#define MV_WIN_CPU_REMAP_HI_ARMV5(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) | |||||
#if defined(SOC_MV_DISCOVERY) | #if defined(SOC_MV_DISCOVERY) | ||||
#define MV_WIN_CPU_MAX 14 | #define MV_WIN_CPU_MAX 14 | ||||
#elif defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) | |||||
#define MV_WIN_CPU_MAX 20 | |||||
#else | #else | ||||
#define MV_WIN_CPU_MAX 8 | #define MV_WIN_CPU_MAX 8 | ||||
#endif | #endif | ||||
#define MV_WIN_CPU_MAX_ARMV7 20 | |||||
#define MV_WIN_CPU_ATTR_SHIFT 8 | #define MV_WIN_CPU_ATTR_SHIFT 8 | ||||
#define MV_WIN_CPU_TARGET_SHIFT 4 | #define MV_WIN_CPU_TARGET_SHIFT 4 | ||||
#define MV_WIN_CPU_ENABLE_BIT 1 | #define MV_WIN_CPU_ENABLE_BIT 1 | ||||
#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) | #define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) | ||||
#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) | #define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) | ||||
#define MV_WIN_DDR_MAX 4 | #define MV_WIN_DDR_MAX 4 | ||||
/* | /* | ||||
* These values are valid only for peripherals decoding windows | * These values are valid only for peripherals decoding windows | ||||
* Bit in ATTR is zeroed according to CS bank number | * Bit in ATTR is zeroed according to CS bank number | ||||
*/ | */ | ||||
#define MV_WIN_DDR_ATTR(cs) (0x0F & ~(0x01 << (cs))) | #define MV_WIN_DDR_ATTR(cs) (0x0F & ~(0x01 << (cs))) | ||||
#define MV_WIN_DDR_TARGET 0x0 | #define MV_WIN_DDR_TARGET 0x0 | ||||
#if defined(SOC_MV_DISCOVERY) | #if defined(SOC_MV_DISCOVERY) | ||||
#define MV_WIN_CESA_TARGET 9 | #define MV_WIN_CESA_TARGET 9 | ||||
#define MV_WIN_CESA_ATTR(eng_sel) 1 | #define MV_WIN_CESA_ATTR(eng_sel) 1 | ||||
#elif defined(SOC_MV_ARMADAXP) | #else | ||||
#define MV_WIN_CESA_TARGET 9 | #define MV_WIN_CESA_TARGET 3 | ||||
#define MV_WIN_CESA_ATTR(eng_sel) 0 | |||||
#endif | |||||
#define MV_WIN_CESA_TARGET_ARMADAXP 9 | |||||
/* | /* | ||||
* Bits [2:3] of cesa attribute select engine: | * Bits [2:3] of cesa attribute select engine: | ||||
* eng_sel: | * eng_sel: | ||||
* 1: engine1 | * 1: engine1 | ||||
* 2: engine0 | * 2: engine0 | ||||
*/ | */ | ||||
#define MV_WIN_CESA_ATTR(eng_sel) (1 | ((eng_sel) << 2)) | #define MV_WIN_CESA_ATTR_ARMADAXP(eng_sel) (1 | ((eng_sel) << 2)) | ||||
#elif defined(SOC_MV_ARMADA38X) | #define MV_WIN_CESA_TARGET_ARMADA38X 9 | ||||
#define MV_WIN_CESA_TARGET 9 | |||||
/* | /* | ||||
* Bits [1:0] = Data swapping | * Bits [1:0] = Data swapping | ||||
* 0x0 = Byte swap | * 0x0 = Byte swap | ||||
* 0x1 = No swap | * 0x1 = No swap | ||||
* 0x2 = Byte and word swap | * 0x2 = Byte and word swap | ||||
* 0x3 = Word swap | * 0x3 = Word swap | ||||
* Bits [4:2] = CESA select: | * Bits [4:2] = CESA select: | ||||
* 0x6 = CESA0 | * 0x6 = CESA0 | ||||
* 0x5 = CESA1 | * 0x5 = CESA1 | ||||
*/ | */ | ||||
#define MV_WIN_CESA_ATTR(eng_sel) (0x11 | (1 << (3 - (eng_sel)))) | #define MV_WIN_CESA_ATTR_ARMADA38X(eng_sel) (0x11 | (1 << (3 - (eng_sel)))) | ||||
#else | |||||
#define MV_WIN_CESA_TARGET 3 | |||||
#define MV_WIN_CESA_ATTR(eng_sel) 0 | |||||
#endif | |||||
/* CESA TDMA address decoding registers */ | /* CESA TDMA address decoding registers */ | ||||
#define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xA04) | #define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xA04) | ||||
#define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xA00) | #define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xA00) | ||||
#define MV_WIN_CESA_MAX 4 | #define MV_WIN_CESA_MAX 4 | ||||
#define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320) | #define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320) | ||||
#define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324) | #define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324) | ||||
#define MV_WIN_USB_MAX 4 | #define MV_WIN_USB_MAX 4 | ||||
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#define MV_PCIE_BAR_BASE_H(n) (0x08 * (n) + 0x0014) | #define MV_PCIE_BAR_BASE_H(n) (0x08 * (n) + 0x0014) | ||||
#define MV_PCIE_BAR_MAX 4 | #define MV_PCIE_BAR_MAX 4 | ||||
#define MV_PCIE_BAR_64BIT (0x4) | #define MV_PCIE_BAR_64BIT (0x4) | ||||
#define MV_PCIE_BAR_PREFETCH_EN (0x8) | #define MV_PCIE_BAR_PREFETCH_EN (0x8) | ||||
#define MV_PCIE_CONTROL (0x1a00) | #define MV_PCIE_CONTROL (0x1a00) | ||||
#define MV_PCIE_ROOT_CMPLX (1 << 1) | #define MV_PCIE_ROOT_CMPLX (1 << 1) | ||||
#if defined(SOC_MV_ARMADA38X) | #define MV_WIN_SATA_CTRL_ARMADA38X(n) (0x10 * (n) + 0x60) | ||||
#define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x60) | #define MV_WIN_SATA_BASE_ARMADA38X(n) (0x10 * (n) + 0x64) | ||||
#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x64) | #define MV_WIN_SATA_SIZE_ARMADA38X(n) (0x10 * (n) + 0x68) | ||||
#define MV_WIN_SATA_SIZE(n) (0x10 * (n) + 0x68) | #define MV_WIN_SATA_MAX_ARMADA38X 4 | ||||
#define MV_WIN_SATA_MAX 4 | |||||
#else | |||||
#define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30) | #define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30) | ||||
#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) | #define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) | ||||
#define MV_WIN_SATA_MAX 4 | #define MV_WIN_SATA_MAX 4 | ||||
#endif | |||||
#define MV_WIN_SDHCI_CTRL(n) (0x8 * (n) + 0x4080) | #define MV_WIN_SDHCI_CTRL(n) (0x8 * (n) + 0x4080) | ||||
#define MV_WIN_SDHCI_BASE(n) (0x8 * (n) + 0x4084) | #define MV_WIN_SDHCI_BASE(n) (0x8 * (n) + 0x4084) | ||||
#define MV_WIN_SDHCI_MAX 8 | #define MV_WIN_SDHCI_MAX 8 | ||||
#if defined(SOC_MV_ARMADA38X) | |||||
#define MV_BOOTROM_MEM_ADDR 0xFFF00000 | #define MV_BOOTROM_MEM_ADDR 0xFFF00000 | ||||
#define MV_BOOTROM_WIN_SIZE 0xF | #define MV_BOOTROM_WIN_SIZE 0xF | ||||
#define MV_CPU_SUBSYS_REGS_LEN 0x100 | #define MV_CPU_SUBSYS_REGS_LEN 0x100 | ||||
#define IO_WIN_9_CTRL_OFFSET 0x98 | #define IO_WIN_9_CTRL_OFFSET 0x98 | ||||
#define IO_WIN_9_BASE_OFFSET 0x9C | #define IO_WIN_9_BASE_OFFSET 0x9C | ||||
/* Mbus decoding unit IDs and attributes */ | /* Mbus decoding unit IDs and attributes */ | ||||
#define MBUS_BOOTROM_TGT_ID 0x1 | #define MBUS_BOOTROM_TGT_ID 0x1 | ||||
#define MBUS_BOOTROM_ATTR 0x1D | #define MBUS_BOOTROM_ATTR 0x1D | ||||
/* Internal Units Sync Barrier Control Register */ | /* Internal Units Sync Barrier Control Register */ | ||||
#define MV_SYNC_BARRIER_CTRL 0x84 | #define MV_SYNC_BARRIER_CTRL 0x84 | ||||
#define MV_SYNC_BARRIER_CTRL_ALL 0xFFFF | #define MV_SYNC_BARRIER_CTRL_ALL 0xFFFF | ||||
#endif | |||||
/* IO Window Control Register fields */ | /* IO Window Control Register fields */ | ||||
#define IO_WIN_SIZE_SHIFT 16 | #define IO_WIN_SIZE_SHIFT 16 | ||||
#define IO_WIN_SIZE_MASK 0xFFFF | #define IO_WIN_SIZE_MASK 0xFFFF | ||||
#define IO_WIN_COH_ATTR_MASK (0xF << 12) | #define IO_WIN_COH_ATTR_MASK (0xF << 12) | ||||
#define IO_WIN_ATTR_SHIFT 8 | #define IO_WIN_ATTR_SHIFT 8 | ||||
#define IO_WIN_ATTR_MASK 0xFF | #define IO_WIN_ATTR_MASK 0xFF | ||||
#define IO_WIN_TGT_SHIFT 4 | #define IO_WIN_TGT_SHIFT 4 | ||||
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