Differential D14738 Diff 41064 head/sys/arm/mv/mv_common.c

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head/sys/arm/mv/mv_common.c

Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
#endif		#endif

#ifdef DEBUG		#ifdef DEBUG
#define MV_DUMP_WIN 1		#define MV_DUMP_WIN 1
#else		#else
#define MV_DUMP_WIN 0		#define MV_DUMP_WIN 0
#endif		#endif

		static enum soc_family soc_family;

		static int mv_win_cesa_attr(int wng_sel);
		static int mv_win_cesa_attr_armv5(int eng_sel);
		static int mv_win_cesa_attr_armada38x(int eng_sel);
		static int mv_win_cesa_attr_armadaxp(int eng_sel);

		uint32_t read_cpu_ctrl_armv5(uint32_t reg);
		uint32_t read_cpu_ctrl_armv7(uint32_t reg);

		void write_cpu_ctrl_armv5(uint32_t reg, uint32_t val);
		void write_cpu_ctrl_armv7(uint32_t reg, uint32_t val);

static int win_eth_can_remap(int i);		static int win_eth_can_remap(int i);

static int decode_win_cesa_valid(void);		static int decode_win_cesa_valid(void);
static int decode_win_cpu_valid(void);		static int decode_win_cpu_valid(void);
static int decode_win_usb_valid(void);		static int decode_win_usb_valid(void);
static int decode_win_usb3_valid(void);		static int decode_win_usb3_valid(void);
static int decode_win_eth_valid(void);		static int decode_win_eth_valid(void);
static int decode_win_pcie_valid(void);		static int decode_win_pcie_valid(void);
static int decode_win_sata_valid(void);		static int decode_win_sata_valid(void);
static int decode_win_sdhci_valid(void);		static int decode_win_sdhci_valid(void);

static int decode_win_idma_valid(void);		static int decode_win_idma_valid(void);
static int decode_win_xor_valid(void);		static int decode_win_xor_valid(void);

static void decode_win_cpu_setup(void);		static void decode_win_cpu_setup(void);
#ifdef SOC_MV_ARMADAXP
static int decode_win_sdram_fixup(void);		static int decode_win_sdram_fixup(void);
#endif
static void decode_win_cesa_setup(u_long);		static void decode_win_cesa_setup(u_long);
static void decode_win_usb_setup(u_long);		static void decode_win_usb_setup(u_long);
static void decode_win_usb3_setup(u_long);		static void decode_win_usb3_setup(u_long);
static void decode_win_eth_setup(u_long);		static void decode_win_eth_setup(u_long);
static void decode_win_neta_setup(u_long);		static void decode_win_neta_setup(u_long);
static void decode_win_sata_setup(u_long);		static void decode_win_sata_setup(u_long);
static void decode_win_ahci_setup(u_long);		static void decode_win_ahci_setup(u_long);
static void decode_win_sdhci_setup(u_long);		static void decode_win_sdhci_setup(u_long);

static void decode_win_idma_setup(u_long);		static void decode_win_idma_setup(u_long);
static void decode_win_xor_setup(u_long);		static void decode_win_xor_setup(u_long);

static void decode_win_cesa_dump(u_long);		static void decode_win_cesa_dump(u_long);
static void decode_win_usb_dump(u_long);		static void decode_win_usb_dump(u_long);
static void decode_win_usb3_dump(u_long);		static void decode_win_usb3_dump(u_long);
static void decode_win_eth_dump(u_long base);		static void decode_win_eth_dump(u_long base);
static void decode_win_neta_dump(u_long base);		static void decode_win_neta_dump(u_long base);
static void decode_win_idma_dump(u_long base);		static void decode_win_idma_dump(u_long base);
static void decode_win_xor_dump(u_long base);		static void decode_win_xor_dump(u_long base);
static void decode_win_ahci_dump(u_long base);		static void decode_win_ahci_dump(u_long base);
static void decode_win_sdhci_dump(u_long);		static void decode_win_sdhci_dump(u_long);
static void decode_win_pcie_dump(u_long);		static void decode_win_pcie_dump(u_long);

		static uint32_t win_cpu_cr_read(int);
		static uint32_t win_cpu_armv5_cr_read(int);
		static uint32_t win_cpu_armv7_cr_read(int);
		static uint32_t win_cpu_br_read(int);
		static uint32_t win_cpu_armv5_br_read(int);
		static uint32_t win_cpu_armv7_br_read(int);
		static uint32_t win_cpu_remap_l_read(int);
		static uint32_t win_cpu_armv5_remap_l_read(int);
		static uint32_t win_cpu_armv7_remap_l_read(int);
		static uint32_t win_cpu_remap_h_read(int);
		static uint32_t win_cpu_armv5_remap_h_read(int);
		static uint32_t win_cpu_armv7_remap_h_read(int);

		static void win_cpu_cr_write(int, uint32_t);
		static void win_cpu_armv5_cr_write(int, uint32_t);
		static void win_cpu_armv7_cr_write(int, uint32_t);
		static void win_cpu_br_write(int, uint32_t);
		static void win_cpu_armv5_br_write(int, uint32_t);
		static void win_cpu_armv7_br_write(int, uint32_t);
		static void win_cpu_remap_l_write(int, uint32_t);
		static void win_cpu_armv5_remap_l_write(int, uint32_t);
		static void win_cpu_armv7_remap_l_write(int, uint32_t);
		static void win_cpu_remap_h_write(int, uint32_t);
		static void win_cpu_armv5_remap_h_write(int, uint32_t);
		static void win_cpu_armv7_remap_h_write(int, uint32_t);

		static uint32_t ddr_br_read(int);
		static uint32_t ddr_sz_read(int);
		static uint32_t ddr_armv5_br_read(int);
		static uint32_t ddr_armv5_sz_read(int);
		static uint32_t ddr_armv7_br_read(int);
		static uint32_t ddr_armv7_sz_read(int);
		static void ddr_br_write(int, uint32_t);
		static void ddr_sz_write(int, uint32_t);
		static void ddr_armv5_br_write(int, uint32_t);
		static void ddr_armv5_sz_write(int, uint32_t);
		static void ddr_armv7_br_write(int, uint32_t);
		static void ddr_armv7_sz_write(int, uint32_t);

static int fdt_get_ranges(const char , void , int, int , int );		static int fdt_get_ranges(const char , void , int, int , int );
#ifdef SOC_MV_ARMADA38X
int gic_decode_fdt(phandle_t iparent, pcell_t intr, int interrupt,		int gic_decode_fdt(phandle_t iparent, pcell_t intr, int interrupt,
int trig, int pol);		int trig, int pol);
#endif

static int win_cpu_from_dt(void);		static int win_cpu_from_dt(void);
static int fdt_win_setup(void);		static int fdt_win_setup(void);

static uint32_t dev_mask = 0;		static uint32_t dev_mask = 0;
static int cpu_wins_no = 0;		static int cpu_wins_no = 0;
static int eth_port = 0;		static int eth_port = 0;
static int usb_port = 0;		static int usb_port = 0;
Show All 39 Lines	static struct soc_node_spec soc_nodes[] = {
{ "mrvl,sata", &decode_win_sata_setup, NULL, &decode_win_sata_valid},		{ "mrvl,sata", &decode_win_sata_setup, NULL, &decode_win_sata_valid},
{ "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump, &decode_win_xor_valid},		{ "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump, &decode_win_xor_valid},
{ "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump, &decode_win_idma_valid},		{ "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump, &decode_win_idma_valid},
{ "mrvl,cesa", &decode_win_cesa_setup, &decode_win_cesa_dump, &decode_win_cesa_valid},		{ "mrvl,cesa", &decode_win_cesa_setup, &decode_win_cesa_dump, &decode_win_cesa_valid},
{ "mrvl,pcie", &decode_win_pcie_setup, &decode_win_pcie_dump, &decode_win_pcie_valid},		{ "mrvl,pcie", &decode_win_pcie_setup, &decode_win_pcie_dump, &decode_win_pcie_valid},
{ NULL, NULL, NULL, NULL },		{ NULL, NULL, NULL, NULL },
};		};

		typedef uint32_t(*read_cpu_ctrl_t)(uint32_t);
		typedef void(*write_cpu_ctrl_t)(uint32_t, uint32_t);
		typedef uint32_t (*win_read_t)(int);
		typedef void (*win_write_t)(int, uint32_t);
		typedef int (*win_cesa_attr_t)(int);

		struct decode_win_spec {
		read_cpu_ctrl_t read_cpu_ctrl;
		write_cpu_ctrl_t write_cpu_ctrl;
		win_read_t cr_read;
		win_read_t br_read;
		win_read_t remap_l_read;
		win_read_t remap_h_read;
		win_write_t cr_write;
		win_write_t br_write;
		win_write_t remap_l_write;
		win_write_t remap_h_write;
		uint32_t mv_win_cpu_max;
		win_cesa_attr_t win_cesa_attr;
		int win_cesa_target;
		win_read_t ddr_br_read;
		win_read_t ddr_sz_read;
		win_write_t ddr_br_write;
		win_write_t ddr_sz_write;
		};

		struct decode_win_spec *soc_decode_win_spec;

		static struct decode_win_spec decode_win_specs[] =
		{
		{
		&read_cpu_ctrl_armv7,
		&write_cpu_ctrl_armv7,
		&win_cpu_armv7_cr_read,
		&win_cpu_armv7_br_read,
		&win_cpu_armv7_remap_l_read,
		&win_cpu_armv7_remap_h_read,
		&win_cpu_armv7_cr_write,
		&win_cpu_armv7_br_write,
		&win_cpu_armv7_remap_l_write,
		&win_cpu_armv7_remap_h_write,
		MV_WIN_CPU_MAX_ARMV7,
		&mv_win_cesa_attr_armada38x,
		MV_WIN_CESA_TARGET_ARMADA38X,
		&ddr_armv7_br_read,
		&ddr_armv7_sz_read,
		&ddr_armv7_br_write,
		&ddr_armv7_sz_write,
		},
		{
		&read_cpu_ctrl_armv7,
		&write_cpu_ctrl_armv7,
		&win_cpu_armv7_cr_read,
		&win_cpu_armv7_br_read,
		&win_cpu_armv7_remap_l_read,
		&win_cpu_armv7_remap_h_read,
		&win_cpu_armv7_cr_write,
		&win_cpu_armv7_br_write,
		&win_cpu_armv7_remap_l_write,
		&win_cpu_armv7_remap_h_write,
		MV_WIN_CPU_MAX_ARMV7,
		&mv_win_cesa_attr_armadaxp,
		MV_WIN_CESA_TARGET_ARMADAXP,
		&ddr_armv7_br_read,
		&ddr_armv7_sz_read,
		&ddr_armv7_br_write,
		&ddr_armv7_sz_write,
		},
		{
		&read_cpu_ctrl_armv5,
		&write_cpu_ctrl_armv5,
		&win_cpu_armv5_cr_read,
		&win_cpu_armv5_br_read,
		&win_cpu_armv5_remap_l_read,
		&win_cpu_armv5_remap_h_read,
		&win_cpu_armv5_cr_write,
		&win_cpu_armv5_br_write,
		&win_cpu_armv5_remap_l_write,
		&win_cpu_armv5_remap_h_write,
		MV_WIN_CPU_MAX,
		&mv_win_cesa_attr_armv5,
		MV_WIN_CESA_TARGET,
		&ddr_armv5_br_read,
		&ddr_armv5_sz_read,
		&ddr_armv5_br_write,
		&ddr_armv5_sz_write,
		},
		};

struct fdt_pm_mask_entry {		struct fdt_pm_mask_entry {
char *compat;		char *compat;
uint32_t mask;		uint32_t mask;
};		};

static struct fdt_pm_mask_entry fdt_pm_mask_table[] = {		static struct fdt_pm_mask_entry fdt_pm_mask_table[] = {
{ "mrvl,ge", CPU_PM_CTRL_GE(0) },		{ "mrvl,ge", CPU_PM_CTRL_GE(0) },
{ "mrvl,ge", CPU_PM_CTRL_GE(1) },		{ "mrvl,ge", CPU_PM_CTRL_GE(1) },
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
* \|-------------------------------\|		* \|-------------------------------\|
* \| CESA \| 0x20000 \| 0x400000 \|		* \| CESA \| 0x20000 \| 0x400000 \|
* \|-------------------------------\|		* \|-------------------------------\|
* \| SATA \| 0x04000 \| 0x004000 \|		* \| SATA \| 0x04000 \| 0x004000 \|
* --------------------------------\|		* --------------------------------\|
* This feature can be used only on Kirkwood and Discovery		* This feature can be used only on Kirkwood and Discovery
* machines.		* machines.
*/		*/

		static int mv_win_cesa_attr(int eng_sel)
		{

		if (soc_decode_win_spec->win_cesa_attr != NULL)
		return (soc_decode_win_spec->win_cesa_attr(eng_sel));

		return (-1);
		}

		static int mv_win_cesa_attr_armv5(int eng_sel)
		{

		return MV_WIN_CESA_ATTR(eng_sel);
		}

		static int mv_win_cesa_attr_armada38x(int eng_sel)
		{

		return MV_WIN_CESA_ATTR_ARMADA38X(eng_sel);
		}

		static int mv_win_cesa_attr_armadaxp(int eng_sel)
		{

		return MV_WIN_CESA_ATTR_ARMADAXP(eng_sel);
		}

		enum soc_family
		mv_check_soc_family()
		{
		uint32_t dev, rev;

		soc_id(&dev, &rev);
		switch (dev) {
		case MV_DEV_MV78230:
		case MV_DEV_MV78260:
		case MV_DEV_MV78460:
		soc_decode_win_spec = &decode_win_specs[MV_SOC_ARMADA_XP];
		soc_family = MV_SOC_ARMADA_XP;
		return (MV_SOC_ARMADA_XP);
		case MV_DEV_88F6828:
		case MV_DEV_88F6820:
		case MV_DEV_88F6810:
		soc_decode_win_spec = &decode_win_specs[MV_SOC_ARMADA_38X];
		soc_family = MV_SOC_ARMADA_38X;
		return (MV_SOC_ARMADA_38X);
		case MV_DEV_88F5181:
		case MV_DEV_88F5182:
		case MV_DEV_88F5281:
		case MV_DEV_88F6281:
		case MV_DEV_88RC8180:
		case MV_DEV_88RC9480:
		case MV_DEV_88RC9580:
		case MV_DEV_88F6781:
		case MV_DEV_88F6282:
		case MV_DEV_MV78100_Z0:
		case MV_DEV_MV78100:
		case MV_DEV_MV78160:
		soc_decode_win_spec = &decode_win_specs[MV_SOC_ARMV5];
		soc_family = MV_SOC_ARMV5;
		return (MV_SOC_ARMV5);
		default:
		soc_family = MV_SOC_UNSUPPORTED;
		return (MV_SOC_UNSUPPORTED);
		}
		}

static __inline void		static __inline void
pm_disable_device(int mask)		pm_disable_device(int mask)
{		{
#ifdef DIAGNOSTIC		#ifdef DIAGNOSTIC
uint32_t reg;		uint32_t reg;

reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL);		reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL);
printf("Power Management Register: 0%x\n", reg);		printf("Power Management Register: 0%x\n", reg);
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines	#endif

return (ena);		return (ena);
}		}

uint32_t		uint32_t
read_cpu_ctrl(uint32_t reg)		read_cpu_ctrl(uint32_t reg)
{		{

		if (soc_decode_win_spec->read_cpu_ctrl != NULL)
		return (soc_decode_win_spec->read_cpu_ctrl(reg));
		return (-1);
		}

		uint32_t
		read_cpu_ctrl_armv5(uint32_t reg)
		{

return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg));		return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg));
}		}

		uint32_t
		read_cpu_ctrl_armv7(uint32_t reg)
		{

		return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE_ARMV7, reg));
		}

void		void
write_cpu_ctrl(uint32_t reg, uint32_t val)		write_cpu_ctrl(uint32_t reg, uint32_t val)
{		{

		if (soc_decode_win_spec->write_cpu_ctrl != NULL)
		soc_decode_win_spec->write_cpu_ctrl(reg, val);
		}

		void
		write_cpu_ctrl_armv5(uint32_t reg, uint32_t val)
		{

bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val);		bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val);
}		}

#if defined(SOC_MV_ARMADAXP) \|\| defined(SOC_MV_ARMADA38X)		void
		write_cpu_ctrl_armv7(uint32_t reg, uint32_t val)
		{

		bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE_ARMV7, reg, val);
		}

uint32_t		uint32_t
read_cpu_mp_clocks(uint32_t reg)		read_cpu_mp_clocks(uint32_t reg)
{		{

return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg));		return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg));
}		}

void		void
Show All 11 Lines
}		}

void		void
write_cpu_misc(uint32_t reg, uint32_t val)		write_cpu_misc(uint32_t reg, uint32_t val)
{		{

bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val);		bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val);
}		}
#endif

void		void
cpu_reset(void)		cpu_reset(void)
{		{

#if defined(SOC_MV_ARMADAXP) \|\| defined (SOC_MV_ARMADA38X)		#if defined(SOC_MV_ARMADAXP) \|\| defined (SOC_MV_ARMADA38X)
write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN);		write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN);
write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST);		write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines	#if !defined(SOC_MV_ORION)
if (mask != CPU_PM_CTRL_NONE)		if (mask != CPU_PM_CTRL_NONE)
write_cpu_ctrl(CPU_PM_CTRL, mask);		write_cpu_ctrl(CPU_PM_CTRL, mask);
#endif		#endif
}		}

void		void
soc_id(uint32_t dev, uint32_t rev)		soc_id(uint32_t dev, uint32_t rev)
{		{
		uint64_t mv_pcie_base = MV_PCIE_BASE;
		phandle_t node;

/*		/*
* Notice: system identifiers are available in the registers range of		* Notice: system identifiers are available in the registers range of
* PCIE controller, so using this function is only allowed (and		* PCIE controller, so using this function is only allowed (and
* possible) after the internal registers range has been mapped in via		* possible) after the internal registers range has been mapped in via
* devmap_bootstrap().		* devmap_bootstrap().
*/		*/
*dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16;		*dev = 0;
*rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff;		*rev = 0;
		if ((node = OF_finddevice("/")) == -1)
		return;
		if (ofw_bus_node_is_compatible(node, "marvell,armada380"))
		mv_pcie_base = MV_PCIE_BASE_ARMADA38X;

		*dev = bus_space_read_4(fdtbus_bs_tag, mv_pcie_base, 0) >> 16;
		*rev = bus_space_read_4(fdtbus_bs_tag, mv_pcie_base, 8) & 0xff;
}		}

static void		static void
soc_identify(void)		soc_identify(void)
{		{
uint32_t d, r, size, mode, freq;		uint32_t d, r, size, mode, freq;
const char *dev;		const char *dev;
const char *rev;		const char *rev;
▲ Show 20 Lines • Show All 157 Lines • ▼ Show 20 Lines	soc_decode_win(void)

/* Retrieve data about physical addresses from device tree. */		/* Retrieve data about physical addresses from device tree. */
if ((err = win_cpu_from_dt()) != 0)		if ((err = win_cpu_from_dt()) != 0)
return (err);		return (err);

/* Retrieve our ID: some windows facilities vary between SoC models */		/* Retrieve our ID: some windows facilities vary between SoC models */
soc_id(&dev, &rev);		soc_id(&dev, &rev);

#ifdef SOC_MV_ARMADAXP		if (soc_family == MV_SOC_ARMADA_XP)
if ((err = decode_win_sdram_fixup()) != 0)		if ((err = decode_win_sdram_fixup()) != 0)
return(err);		return(err);
#endif


decode_win_cpu_setup();		decode_win_cpu_setup();
if (MV_DUMP_WIN)		if (MV_DUMP_WIN)
soc_dump_decode_win();		soc_dump_decode_win();

eth_port = 0;		eth_port = 0;
usb_port = 0;		usb_port = 0;
if ((err = fdt_win_setup()) != 0)		if ((err = fdt_win_setup()) != 0)
return (err);		return (err);

return (0);		return (0);
}		}

/**************************************************************************		/**************************************************************************
* Decode windows registers accessors		* Decode windows registers accessors
**************************************************************************/		**************************************************************************/
WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)		WIN_REG_IDX_RD(win_cpu_armv5, cr, MV_WIN_CPU_CTRL_ARMV5, MV_MBUS_BRIDGE_BASE)
WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)		WIN_REG_IDX_RD(win_cpu_armv5, br, MV_WIN_CPU_BASE_ARMV5, MV_MBUS_BRIDGE_BASE)
WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)		WIN_REG_IDX_RD(win_cpu_armv5, remap_l, MV_WIN_CPU_REMAP_LO_ARMV5, MV_MBUS_BRIDGE_BASE)
WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)		WIN_REG_IDX_RD(win_cpu_armv5, remap_h, MV_WIN_CPU_REMAP_HI_ARMV5, MV_MBUS_BRIDGE_BASE)
WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)		WIN_REG_IDX_WR(win_cpu_armv5, cr, MV_WIN_CPU_CTRL_ARMV5, MV_MBUS_BRIDGE_BASE)
WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)		WIN_REG_IDX_WR(win_cpu_armv5, br, MV_WIN_CPU_BASE_ARMV5, MV_MBUS_BRIDGE_BASE)
WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)		WIN_REG_IDX_WR(win_cpu_armv5, remap_l, MV_WIN_CPU_REMAP_LO_ARMV5, MV_MBUS_BRIDGE_BASE)
WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)		WIN_REG_IDX_WR(win_cpu_armv5, remap_h, MV_WIN_CPU_REMAP_HI_ARMV5, MV_MBUS_BRIDGE_BASE)

		WIN_REG_IDX_RD(win_cpu_armv7, cr, MV_WIN_CPU_CTRL_ARMV7, MV_MBUS_BRIDGE_BASE)
		WIN_REG_IDX_RD(win_cpu_armv7, br, MV_WIN_CPU_BASE_ARMV7, MV_MBUS_BRIDGE_BASE)
		WIN_REG_IDX_RD(win_cpu_armv7, remap_l, MV_WIN_CPU_REMAP_LO_ARMV7, MV_MBUS_BRIDGE_BASE)
		WIN_REG_IDX_RD(win_cpu_armv7, remap_h, MV_WIN_CPU_REMAP_HI_ARMV7, MV_MBUS_BRIDGE_BASE)
		WIN_REG_IDX_WR(win_cpu_armv7, cr, MV_WIN_CPU_CTRL_ARMV7, MV_MBUS_BRIDGE_BASE)
		WIN_REG_IDX_WR(win_cpu_armv7, br, MV_WIN_CPU_BASE_ARMV7, MV_MBUS_BRIDGE_BASE)
		WIN_REG_IDX_WR(win_cpu_armv7, remap_l, MV_WIN_CPU_REMAP_LO_ARMV7, MV_MBUS_BRIDGE_BASE)
		WIN_REG_IDX_WR(win_cpu_armv7, remap_h, MV_WIN_CPU_REMAP_HI_ARMV7, MV_MBUS_BRIDGE_BASE)

		static uint32_t
		win_cpu_cr_read(int i)
		{

		if (soc_decode_win_spec->cr_read != NULL)
		return (soc_decode_win_spec->cr_read(i));
		return (-1);
		}

		static uint32_t
		win_cpu_br_read(int i)
		{

		if (soc_decode_win_spec->br_read != NULL)
		return (soc_decode_win_spec->br_read(i));
		return (-1);
		}

		static uint32_t
		win_cpu_remap_l_read(int i)
		{

		if (soc_decode_win_spec->remap_l_read != NULL)
		return (soc_decode_win_spec->remap_l_read(i));
		return (-1);
		}

		static uint32_t
		win_cpu_remap_h_read(int i)
		{

		if (soc_decode_win_spec->remap_h_read != NULL)
		return soc_decode_win_spec->remap_h_read(i);
		return (-1);
		}

		static void
		win_cpu_cr_write(int i, uint32_t val)
		{

		if (soc_decode_win_spec->cr_write != NULL)
		soc_decode_win_spec->cr_write(i, val);
		}

		static void
		win_cpu_br_write(int i, uint32_t val)
		{

		if (soc_decode_win_spec->br_write != NULL)
		soc_decode_win_spec->br_write(i, val);
		}

		static void
		win_cpu_remap_l_write(int i, uint32_t val)
		{

		if (soc_decode_win_spec->remap_l_write != NULL)
		soc_decode_win_spec->remap_l_write(i, val);
		}

		static void
		win_cpu_remap_h_write(int i, uint32_t val)
		{

		if (soc_decode_win_spec->remap_h_write != NULL)
		soc_decode_win_spec->remap_h_write(i, val);
		}

WIN_REG_BASE_IDX_RD(win_cesa, cr, MV_WIN_CESA_CTRL)		WIN_REG_BASE_IDX_RD(win_cesa, cr, MV_WIN_CESA_CTRL)
WIN_REG_BASE_IDX_RD(win_cesa, br, MV_WIN_CESA_BASE)		WIN_REG_BASE_IDX_RD(win_cesa, br, MV_WIN_CESA_BASE)
WIN_REG_BASE_IDX_WR(win_cesa, cr, MV_WIN_CESA_CTRL)		WIN_REG_BASE_IDX_WR(win_cesa, cr, MV_WIN_CESA_CTRL)
WIN_REG_BASE_IDX_WR(win_cesa, br, MV_WIN_CESA_BASE)		WIN_REG_BASE_IDX_WR(win_cesa, br, MV_WIN_CESA_BASE)

WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL)		WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL)
WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE)		WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE)
WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL)		WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL)
WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE)		WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE)

#ifdef SOC_MV_ARMADA38X
WIN_REG_BASE_IDX_RD(win_usb3, cr, MV_WIN_USB3_CTRL)		WIN_REG_BASE_IDX_RD(win_usb3, cr, MV_WIN_USB3_CTRL)
WIN_REG_BASE_IDX_RD(win_usb3, br, MV_WIN_USB3_BASE)		WIN_REG_BASE_IDX_RD(win_usb3, br, MV_WIN_USB3_BASE)
WIN_REG_BASE_IDX_WR(win_usb3, cr, MV_WIN_USB3_CTRL)		WIN_REG_BASE_IDX_WR(win_usb3, cr, MV_WIN_USB3_CTRL)
WIN_REG_BASE_IDX_WR(win_usb3, br, MV_WIN_USB3_BASE)		WIN_REG_BASE_IDX_WR(win_usb3, br, MV_WIN_USB3_BASE)
#endif

WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE)		WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE)
WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE)		WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE)
WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP)		WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP)
WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE)		WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE)
WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE)		WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE)
WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP)		WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP)

Show All 34 Lines
WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP)		WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP)
WIN_REG_BASE_RD(win_idma, bare, 0xa80)		WIN_REG_BASE_RD(win_idma, bare, 0xa80)
WIN_REG_BASE_WR(win_idma, bare, 0xa80)		WIN_REG_BASE_WR(win_idma, bare, 0xa80)

WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL);		WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL);
WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE);		WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE);
WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL);		WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL);
WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE);		WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE);
#if defined(SOC_MV_ARMADA38X)
WIN_REG_BASE_IDX_RD(win_sata, sz, MV_WIN_SATA_SIZE);
WIN_REG_BASE_IDX_WR(win_sata, sz, MV_WIN_SATA_SIZE);
#endif

		WIN_REG_BASE_IDX_RD(win_sata_armada38x, sz, MV_WIN_SATA_SIZE_ARMADA38X);
		WIN_REG_BASE_IDX_WR(win_sata_armada38x, sz, MV_WIN_SATA_SIZE_ARMADA38X);
		WIN_REG_BASE_IDX_RD(win_sata_armada38x, cr, MV_WIN_SATA_CTRL_ARMADA38X);
		WIN_REG_BASE_IDX_RD(win_sata_armada38x, br, MV_WIN_SATA_BASE_ARMADA38X);
		WIN_REG_BASE_IDX_WR(win_sata_armada38x, cr, MV_WIN_SATA_CTRL_ARMADA38X);
		WIN_REG_BASE_IDX_WR(win_sata_armada38x, br, MV_WIN_SATA_BASE_ARMADA38X);

WIN_REG_BASE_IDX_RD(win_sdhci, cr, MV_WIN_SDHCI_CTRL);		WIN_REG_BASE_IDX_RD(win_sdhci, cr, MV_WIN_SDHCI_CTRL);
WIN_REG_BASE_IDX_RD(win_sdhci, br, MV_WIN_SDHCI_BASE);		WIN_REG_BASE_IDX_RD(win_sdhci, br, MV_WIN_SDHCI_BASE);
WIN_REG_BASE_IDX_WR(win_sdhci, cr, MV_WIN_SDHCI_CTRL);		WIN_REG_BASE_IDX_WR(win_sdhci, cr, MV_WIN_SDHCI_CTRL);
WIN_REG_BASE_IDX_WR(win_sdhci, br, MV_WIN_SDHCI_BASE);		WIN_REG_BASE_IDX_WR(win_sdhci, br, MV_WIN_SDHCI_BASE);

#ifndef SOC_MV_DOVE		#ifndef SOC_MV_DOVE
WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)		WIN_REG_IDX_RD(ddr_armv5, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)		WIN_REG_IDX_RD(ddr_armv5, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
WIN_REG_IDX_WR(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)		WIN_REG_IDX_WR(ddr_armv5, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
WIN_REG_IDX_WR(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)		WIN_REG_IDX_WR(ddr_armv5, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)

		WIN_REG_IDX_RD(ddr_armv7, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE_ARMV7)
		WIN_REG_IDX_RD(ddr_armv7, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE_ARMV7)
		WIN_REG_IDX_WR(ddr_armv7, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE_ARMV7)
		WIN_REG_IDX_WR(ddr_armv7, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE_ARMV7)

		static inline uint32_t
		ddr_br_read(int i)
		{

		if (soc_decode_win_spec->ddr_br_read != NULL)
		return (soc_decode_win_spec->ddr_br_read(i));
		return (-1);
		}

		static inline uint32_t
		ddr_sz_read(int i)
		{

		if (soc_decode_win_spec->ddr_sz_read != NULL)
		return (soc_decode_win_spec->ddr_sz_read(i));
		return (-1);
		}

		static inline void
		ddr_br_write(int i, uint32_t val)
		{

		if (soc_decode_win_spec->ddr_br_write != NULL)
		soc_decode_win_spec->ddr_br_write(i, val);
		}

		static inline void
		ddr_sz_write(int i, uint32_t val)
		{

		if (soc_decode_win_spec->ddr_sz_write != NULL)
		soc_decode_win_spec->ddr_sz_write(i, val);
		}
#else		#else
/*		/*
* On 88F6781 (Dove) SoC DDR Controller is accessed through		* On 88F6781 (Dove) SoC DDR Controller is accessed through
* single MBUS <-> AXI bridge. In this case we provide emulated		* single MBUS <-> AXI bridge. In this case we provide emulated
* ddr_br_read() and ddr_sz_read() functions to keep compatibility		* ddr_br_read() and ddr_sz_read() functions to keep compatibility
* with common decoding windows setup code.		* with common decoding windows setup code.
*/		*/

Show All 24 Lines
#endif		#endif

/**************************************************************************		/**************************************************************************
* Decode windows helper routines		* Decode windows helper routines
**************************************************************************/		**************************************************************************/
void		void
soc_dump_decode_win(void)		soc_dump_decode_win(void)
{		{
uint32_t dev, rev;
int i;		int i;

soc_id(&dev, &rev);		for (i = 0; i < soc_decode_win_spec->mv_win_cpu_max; i++) {

for (i = 0; i < MV_WIN_CPU_MAX; i++) {
printf("CPU window#%d: c 0x%08x, b 0x%08x", i,		printf("CPU window#%d: c 0x%08x, b 0x%08x", i,
win_cpu_cr_read(i),		win_cpu_cr_read(i),
win_cpu_br_read(i));		win_cpu_br_read(i));

if (win_cpu_can_remap(i))		if (win_cpu_can_remap(i))
printf(", rl 0x%08x, rh 0x%08x",		printf(", rl 0x%08x, rh 0x%08x",
win_cpu_remap_l_read(i),		win_cpu_remap_l_read(i),
win_cpu_remap_h_read(i));		win_cpu_remap_h_read(i));
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
}		}

static int		static int
decode_win_cpu_valid(void)		decode_win_cpu_valid(void)
{		{
int i, j, rv;		int i, j, rv;
uint32_t b, e, s;		uint32_t b, e, s;

if (cpu_wins_no > MV_WIN_CPU_MAX) {		if (cpu_wins_no > soc_decode_win_spec->mv_win_cpu_max) {
printf("CPU windows: too many entries: %d\n", cpu_wins_no);		printf("CPU windows: too many entries: %d\n", cpu_wins_no);
return (0);		return (0);
}		}

rv = 1;		rv = 1;
for (i = 0; i < cpu_wins_no; i++) {		for (i = 0; i < cpu_wins_no; i++) {

if (cpu_wins[i].target == 0) {		if (cpu_wins[i].target == 0) {
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
int		int
decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,		decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
vm_paddr_t remap)		vm_paddr_t remap)
{		{
uint32_t br, cr;		uint32_t br, cr;
int win, i;		int win, i;

if (remap == ~0) {		if (remap == ~0) {
win = MV_WIN_CPU_MAX - 1;		win = soc_decode_win_spec->mv_win_cpu_max - 1;
i = -1;		i = -1;
} else {		} else {
win = 0;		win = 0;
i = 1;		i = 1;
}		}

while ((win >= 0) && (win < MV_WIN_CPU_MAX)) {		while ((win >= 0) && (win < soc_decode_win_spec->mv_win_cpu_max)) {
cr = win_cpu_cr_read(win);		cr = win_cpu_cr_read(win);
if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0)		if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0)
break;		break;
if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) \|		if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) \|
(0x1f << MV_WIN_CPU_TARGET_SHIFT))) ==		(0x1f << MV_WIN_CPU_TARGET_SHIFT))) ==
((attr << MV_WIN_CPU_ATTR_SHIFT) \|		((attr << MV_WIN_CPU_ATTR_SHIFT) \|
(target << MV_WIN_CPU_TARGET_SHIFT)))		(target << MV_WIN_CPU_TARGET_SHIFT)))
break;		break;
win += i;		win += i;
}		}
if ((win < 0) \|\| (win >= MV_WIN_CPU_MAX) \|\|		if ((win < 0) \|\| (win >= soc_decode_win_spec->mv_win_cpu_max) \|\|
((remap != ~0) && (win_cpu_can_remap(win) == 0)))		((remap != ~0) && (win_cpu_can_remap(win) == 0)))
return (-1);		return (-1);

br = base & 0xffff0000;		br = base & 0xffff0000;
win_cpu_br_write(win, br);		win_cpu_br_write(win, br);

if (win_cpu_can_remap(win)) {		if (win_cpu_can_remap(win)) {
if (remap != ~0) {		if (remap != ~0) {
Show All 18 Lines
}		}

static void		static void
decode_win_cpu_setup(void)		decode_win_cpu_setup(void)
{		{
int i;		int i;

/* Disable all CPU windows */		/* Disable all CPU windows */
for (i = 0; i < MV_WIN_CPU_MAX; i++) {		for (i = 0; i < soc_decode_win_spec->mv_win_cpu_max; i++) {
win_cpu_cr_write(i, 0);		win_cpu_cr_write(i, 0);
win_cpu_br_write(i, 0);		win_cpu_br_write(i, 0);
if (win_cpu_can_remap(i)) {		if (win_cpu_can_remap(i)) {
win_cpu_remap_l_write(i, 0);		win_cpu_remap_l_write(i, 0);
win_cpu_remap_h_write(i, 0);		win_cpu_remap_h_write(i, 0);
}		}
}		}

for (i = 0; i < cpu_wins_no; i++)		for (i = 0; i < cpu_wins_no; i++)
if (cpu_wins[i].target > 0)		if (cpu_wins[i].target > 0)
decode_win_cpu_set(cpu_wins[i].target,		decode_win_cpu_set(cpu_wins[i].target,
cpu_wins[i].attr, cpu_wins[i].base,		cpu_wins[i].attr, cpu_wins[i].base,
cpu_wins[i].size, cpu_wins[i].remap);		cpu_wins[i].size, cpu_wins[i].remap);

}		}

#ifdef SOC_MV_ARMADAXP
static int		static int
decode_win_sdram_fixup(void)		decode_win_sdram_fixup(void)
{		{
struct mem_region mr[FDT_MEM_REGIONS];		struct mem_region mr[FDT_MEM_REGIONS];
uint8_t window_valid[MV_WIN_DDR_MAX];		uint8_t window_valid[MV_WIN_DDR_MAX];
int mr_cnt, err, i, j;		int mr_cnt, err, i, j;
uint32_t valid_win_num = 0;		uint32_t valid_win_num = 0;

Show All 25 Lines	for (j = 0; j < MV_WIN_DDR_MAX; j++) {
if (ddr_is_active(j) && (window_valid[j] != 1)) {		if (ddr_is_active(j) && (window_valid[j] != 1)) {
printf("Disabling SDRAM decoding window: %d\n", j);		printf("Disabling SDRAM decoding window: %d\n", j);
ddr_disable(j);		ddr_disable(j);
}		}
}		}

return (0);		return (0);
}		}
#endif
/*		/*
* Check if we're able to cover all active DDR banks.		* Check if we're able to cover all active DDR banks.
*/		*/
static int		static int
decode_win_can_cover_ddr(int max)		decode_win_can_cover_ddr(int max)
{		{
int i, c;		int i, c;

▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines	decode_win_cesa_setup(u_long base)
}		}

/* Only access to active DRAM banks is required */		/* Only access to active DRAM banks is required */
for (i = 0; i < MV_WIN_DDR_MAX; i++) {		for (i = 0; i < MV_WIN_DDR_MAX; i++) {
if (ddr_is_active(i)) {		if (ddr_is_active(i)) {
br = ddr_base(i);		br = ddr_base(i);

size = ddr_size(i);		size = ddr_size(i);
#ifdef SOC_MV_ARMADA38X
/*		/*
* Armada 38x SoC's equipped with 4GB DRAM		* Armada 38x SoC's equipped with 4GB DRAM
* suffer freeze during CESA operation, if		* suffer freeze during CESA operation, if
* MBUS window opened at given DRAM CS reaches		* MBUS window opened at given DRAM CS reaches
* end of the address space. Apply a workaround		* end of the address space. Apply a workaround
* by setting the window size to the closest possible		* by setting the window size to the closest possible
* value, i.e. divide it by 2.		* value, i.e. divide it by 2.
*/		*/
if (size + ddr_base(i) == 0x100000000ULL)		if ((soc_family == MV_SOC_ARMADA_38X) &&
		(size + ddr_base(i) == 0x100000000ULL))
size /= 2;		size /= 2;
#endif

cr = (((size - 1) & 0xffff0000) \|		cr = (((size - 1) & 0xffff0000) \|
(ddr_attr(i) << IO_WIN_ATTR_SHIFT) \|		(ddr_attr(i) << IO_WIN_ATTR_SHIFT) \|
(ddr_target(i) << IO_WIN_TGT_SHIFT) \|		(ddr_target(i) << IO_WIN_TGT_SHIFT) \|
IO_WIN_ENA_MASK);		IO_WIN_ENA_MASK);

/* Set the first free CESA window */		/* Set the first free CESA window */
for (j = 0; j < MV_WIN_CESA_MAX; j++) {		for (j = 0; j < MV_WIN_CESA_MAX; j++) {
▲ Show 20 Lines • Show All 73 Lines • ▼ Show 20 Lines	if (ddr_is_active(i)) {
}		}
}		}
}		}
}		}

/**************************************************************************		/**************************************************************************
* USB3 windows routines		* USB3 windows routines
**************************************************************************/		**************************************************************************/
#ifdef SOC_MV_ARMADA38X
static int		static int
decode_win_usb3_valid(void)		decode_win_usb3_valid(void)
{		{

return (decode_win_can_cover_ddr(MV_WIN_USB3_MAX));		return (decode_win_can_cover_ddr(MV_WIN_USB3_MAX));
}		}

static void		static void
Show All 37 Lines	if (ddr_is_active(i)) {

win_usb3_br_write(base, j, br);		win_usb3_br_write(base, j, br);
win_usb3_cr_write(base, j, cr);		win_usb3_cr_write(base, j, cr);
break;		break;
}		}
}		}
}		}
}		}
#else
/*
* Provide dummy functions to satisfy the build
* for SoCs not equipped with USB3
*/
static int
decode_win_usb3_valid(void)
{

return (1);
}

static void
decode_win_usb3_setup(u_long base)
{
}

static void
decode_win_usb3_dump(u_long base)
{
}
#endif
/**************************************************************************		/**************************************************************************
* ETH windows routines		* ETH windows routines
**************************************************************************/		**************************************************************************/

static int		static int
win_eth_can_remap(int i)		win_eth_can_remap(int i)
{		{

▲ Show 20 Lines • Show All 800 Lines • ▼ Show 20 Lines	if (ddr_is_active(i)) {

win_sata_br_write(base, j, br);		win_sata_br_write(base, j, br);
win_sata_cr_write(base, j, cr);		win_sata_cr_write(base, j, cr);
break;		break;
}		}
}		}
}		}

#ifdef SOC_MV_ARMADA38X
/*		/*
* Configure AHCI decoding windows		* Configure AHCI decoding windows
*/		*/
static void		static void
decode_win_ahci_setup(u_long base)		decode_win_ahci_setup(u_long base)
{		{
uint32_t br, cr, sz;		uint32_t br, cr, sz;
int i, j;		int i, j;

for (i = 0; i < MV_WIN_SATA_MAX; i++) {		for (i = 0; i < MV_WIN_SATA_MAX_ARMADA38X; i++) {
win_sata_cr_write(base, i, 0);		win_sata_armada38x_cr_write(base, i, 0);
win_sata_br_write(base, i, 0);		win_sata_armada38x_br_write(base, i, 0);
win_sata_sz_write(base, i, 0);		win_sata_armada38x_sz_write(base, i, 0);
}		}

for (i = 0; i < MV_WIN_DDR_MAX; i++) {		for (i = 0; i < MV_WIN_DDR_MAX; i++) {
if (ddr_is_active(i)) {		if (ddr_is_active(i)) {
cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) \|		cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) \|
(ddr_target(i) << IO_WIN_TGT_SHIFT) \|		(ddr_target(i) << IO_WIN_TGT_SHIFT) \|
IO_WIN_ENA_MASK;		IO_WIN_ENA_MASK;
br = ddr_base(i);		br = ddr_base(i);
sz = (ddr_size(i) - 1) &		sz = (ddr_size(i) - 1) &
(IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT);		(IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT);

/* Use first available SATA window */		/* Use first available SATA window */
for (j = 0; j < MV_WIN_SATA_MAX; j++) {		for (j = 0; j < MV_WIN_SATA_MAX_ARMADA38X; j++) {
if (win_sata_cr_read(base, j) & IO_WIN_ENA_MASK)		if (win_sata_armada38x_cr_read(base, j) & IO_WIN_ENA_MASK)
continue;		continue;

/* BASE is set to DRAM base (0x00000000) */		/* BASE is set to DRAM base (0x00000000) */
win_sata_br_write(base, j, br);		win_sata_armada38x_br_write(base, j, br);
/* CTRL targets DRAM ctrl with 0x0E or 0x0D */		/* CTRL targets DRAM ctrl with 0x0E or 0x0D */
win_sata_cr_write(base, j, cr);		win_sata_armada38x_cr_write(base, j, cr);
/* SIZE is set to 16MB - max value */		/* SIZE is set to 16MB - max value */
win_sata_sz_write(base, j, sz);		win_sata_armada38x_sz_write(base, j, sz);
break;		break;
}		}
}		}
}		}
}		}

static void		static void
decode_win_ahci_dump(u_long base)		decode_win_ahci_dump(u_long base)
{		{
int i;		int i;

for (i = 0; i < MV_WIN_SATA_MAX; i++)		for (i = 0; i < MV_WIN_SATA_MAX_ARMADA38X; i++)
printf("SATA window#%d: cr 0x%08x, br 0x%08x, sz 0x%08x\n", i,		printf("SATA window#%d: cr 0x%08x, br 0x%08x, sz 0x%08x\n", i,
win_sata_cr_read(base, i), win_sata_br_read(base, i),		win_sata_armada38x_cr_read(base, i), win_sata_br_read(base, i),
win_sata_sz_read(base,i));		win_sata_armada38x_sz_read(base,i));
}		}

#else
/*
* Provide dummy functions to satisfy the build
* for SoC's not equipped with AHCI controller
*/
static void
decode_win_ahci_setup(u_long base)
{
}

static void
decode_win_ahci_dump(u_long base)
{
}
#endif

static int		static int
decode_win_sata_valid(void)		decode_win_sata_valid(void)
{		{
uint32_t dev, rev;		uint32_t dev, rev;

soc_id(&dev, &rev);		soc_id(&dev, &rev);
if (dev == MV_DEV_88F5281)		if (dev == MV_DEV_88F5281)
return (1);		return (1);
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines	for (i = 0; i < MV_WIN_SDHCI_MAX; i++)
printf("SDHCI window#%d: c 0x%08x, b 0x%08x\n", i,		printf("SDHCI window#%d: c 0x%08x, b 0x%08x\n", i,
win_sdhci_cr_read(base, i), win_sdhci_br_read(base, i));		win_sdhci_cr_read(base, i), win_sdhci_br_read(base, i));
}		}

static int		static int
decode_win_sdhci_valid(void)		decode_win_sdhci_valid(void)
{		{

#ifdef SOC_MV_ARMADA38X
return (decode_win_can_cover_ddr(MV_WIN_SDHCI_MAX));		return (decode_win_can_cover_ddr(MV_WIN_SDHCI_MAX));
#endif

/* Satisfy platforms not equipped with this controller. */
return (1);
}		}

/**************************************************************************		/**************************************************************************
* FDT parsing routines.		* FDT parsing routines.
**************************************************************************/		**************************************************************************/

static int		static int
fdt_get_ranges(const char nodename, void buf, int size, int *tuples,		fdt_get_ranges(const char nodename, void buf, int size, int *tuples,
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines	if (fdt_regsize(node, &sram_base, &sram_size) != 0)
return (EINVAL);		return (EINVAL);

/* Check range */		/* Check range */
if (t >= nitems(cpu_win_tbl)) {		if (t >= nitems(cpu_win_tbl)) {
debugf("cannot fit CESA tuple into cpu_win_tbl\n");		debugf("cannot fit CESA tuple into cpu_win_tbl\n");
return (ENOMEM);		return (ENOMEM);
}		}

cpu_win_tbl[t].target = MV_WIN_CESA_TARGET;		cpu_win_tbl[t].target = soc_decode_win_spec->win_cesa_target;
#ifdef SOC_MV_ARMADA38X		if (soc_family == MV_SOC_ARMADA_38X)
cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(0);		cpu_win_tbl[t].attr = soc_decode_win_spec->win_cesa_attr(0);
#else		else
cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1);		cpu_win_tbl[t].attr = soc_decode_win_spec->win_cesa_attr(1);
#endif
cpu_win_tbl[t].base = sram_base;		cpu_win_tbl[t].base = sram_base;
cpu_win_tbl[t].size = sram_size;		cpu_win_tbl[t].size = sram_size;
cpu_win_tbl[t].remap = ~0;		cpu_win_tbl[t].remap = ~0;
cpu_wins_no++;		cpu_wins_no++;
debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size);		debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size);

/* Check if there is a second CESA node */		/* Check if there is a second CESA node */
while ((node = OF_peer(node)) != 0) {		while ((node = OF_peer(node)) != 0) {
Show All 9 Lines	moveon:

t++;		t++;
if (t >= nitems(cpu_win_tbl)) {		if (t >= nitems(cpu_win_tbl)) {
debugf("cannot fit CESA tuple into cpu_win_tbl\n");		debugf("cannot fit CESA tuple into cpu_win_tbl\n");
return (ENOMEM);		return (ENOMEM);
}		}

/* Configure window for CESA1 */		/* Configure window for CESA1 */
cpu_win_tbl[t].target = MV_WIN_CESA_TARGET;		cpu_win_tbl[t].target = soc_decode_win_spec->win_cesa_target;
cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1);		cpu_win_tbl[t].attr = soc_decode_win_spec->win_cesa_attr(1);
cpu_win_tbl[t].base = sram_base;		cpu_win_tbl[t].base = sram_base;
cpu_win_tbl[t].size = sram_size;		cpu_win_tbl[t].size = sram_size;
cpu_win_tbl[t].remap = ~0;		cpu_win_tbl[t].remap = ~0;
cpu_wins_no++;		cpu_wins_no++;
debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size);		debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size);

return (0);		return (0);
}		}
▲ Show 20 Lines • Show All 228 Lines • ▼ Show 20 Lines	fdt_pic_decode_ic(phandle_t node, pcell_t intr, int interrupt, int *trig,
*interrupt = fdt32_to_cpu(intr[0]);		*interrupt = fdt32_to_cpu(intr[0]);
*trig = INTR_TRIGGER_CONFORM;		*trig = INTR_TRIGGER_CONFORM;
*pol = INTR_POLARITY_CONFORM;		*pol = INTR_POLARITY_CONFORM;

return (0);		return (0);
}		}

fdt_pic_decode_t fdt_pic_table[] = {		fdt_pic_decode_t fdt_pic_table[] = {
#ifdef SOC_MV_ARMADA38X
&gic_decode_fdt,
#endif
&fdt_pic_decode_ic,		&fdt_pic_decode_ic,
NULL		NULL
};		};
#endif		#endif