Differential D14736 Diff 41061 head/sys/arm/mv/armadaxp/armadaxp.c

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head/sys/arm/mv/armadaxp/armadaxp.c

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines	#define CPU_FREQ_FIELD(sar) (((0x01 & (sar >> 52)) << 3) \| \
(0x07 & (sar >> 21)))		(0x07 & (sar >> 21)))
#define FAB_FREQ_FIELD(sar) (((0x01 & (sar >> 51)) << 4) \| \		#define FAB_FREQ_FIELD(sar) (((0x01 & (sar >> 51)) << 4) \| \
(0x0F & (sar >> 24)))		(0x0F & (sar >> 24)))

static uint32_t count_l2clk(void);		static uint32_t count_l2clk(void);
void armadaxp_l2_init(void);		void armadaxp_l2_init(void);
void armadaxp_init_coher_fabric(void);		void armadaxp_init_coher_fabric(void);
int platform_get_ncpus(void);		int platform_get_ncpus(void);
		static uint64_t get_sar_value_armadaxp(void);

#define ARMADAXP_L2_BASE (MV_BASE + 0x8000)		#define ARMADAXP_L2_BASE (MV_BASE + 0x8000)
#define ARMADAXP_L2_CTRL 0x100		#define ARMADAXP_L2_CTRL 0x100
#define L2_ENABLE (1 << 0)		#define L2_ENABLE (1 << 0)
#define ARMADAXP_L2_AUX_CTRL 0x104		#define ARMADAXP_L2_AUX_CTRL 0x104
#define L2_WBWT_MODE_MASK (3 << 0)		#define L2_WBWT_MODE_MASK (3 << 0)
#define L2_WBWT_MODE_PAGE 0		#define L2_WBWT_MODE_PAGE 0
#define L2_WBWT_MODE_WB 1		#define L2_WBWT_MODE_WB 1
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/21/ { 1, 2, 8, 4 },		/21/ { 1, 2, 8, 4 },
/22/ { 2, 5, 10, 5 }		/22/ { 2, 5, 10, 5 }
};		};

static uint16_t cpu_clock_table[] = {		static uint16_t cpu_clock_table[] = {
1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000, 600, 667, 800, 1600,		1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000, 600, 667, 800, 1600,
2133, 2200, 2400 };		2133, 2200, 2400 };

		static uint64_t
		get_sar_value_armadaxp(void)
		{
		uint32_t sar_low, sar_high;

		sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
		SAMPLE_AT_RESET_HI);
		sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
		SAMPLE_AT_RESET_LO);
		return (((uint64_t)sar_high << 32) \| sar_low);
		}

uint32_t		uint32_t
get_tclk(void)		get_tclk(void)
{		{
uint32_t cputype;		uint32_t cputype;

cputype = cpu_ident();		cputype = cpu_ident();
cputype &= CPU_ID_CPU_MASK;		cputype &= CPU_ID_CPU_MASK;

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static uint32_t		static uint32_t
count_l2clk(void)		count_l2clk(void)
{		{
uint64_t sar_reg;		uint64_t sar_reg;
uint32_t freq_vco, freq_l2clk;		uint32_t freq_vco, freq_l2clk;
uint8_t sar_cpu_freq, sar_fab_freq, array_size;		uint8_t sar_cpu_freq, sar_fab_freq, array_size;

/* Get value of the SAR register and process it */		/* Get value of the SAR register and process it */
sar_reg = get_sar_value();		sar_reg = get_sar_value_armadaxp();
sar_cpu_freq = CPU_FREQ_FIELD(sar_reg);		sar_cpu_freq = CPU_FREQ_FIELD(sar_reg);
sar_fab_freq = FAB_FREQ_FIELD(sar_reg);		sar_fab_freq = FAB_FREQ_FIELD(sar_reg);

/* Check if CPU frequency field has correct value */		/* Check if CPU frequency field has correct value */
array_size = nitems(cpu_clock_table);		array_size = nitems(cpu_clock_table);
if (sar_cpu_freq >= array_size)		if (sar_cpu_freq >= array_size)
panic("Reserved value in cpu frequency configuration field: "		panic("Reserved value in cpu frequency configuration field: "
"%d", sar_cpu_freq);		"%d", sar_cpu_freq);
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