Differential D14736 Diff 41061 head/sys/arm/mv/armada38x/armada38x.c

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head/sys/arm/mv/armada38x/armada38x.c

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	#include <arm/mv/mvwin.h>			#include <arm/mv/mvwin.h>
	#include <arm/mv/mvreg.h>			#include <arm/mv/mvreg.h>
	#include <arm/mv/mvvar.h>			#include <arm/mv/mvvar.h>

	int armada38x_open_bootrom_win(void);			int armada38x_open_bootrom_win(void);
	int armada38x_scu_enable(void);			int armada38x_scu_enable(void);
	int armada38x_win_set_iosync_barrier(void);			int armada38x_win_set_iosync_barrier(void);
	int armada38x_mbus_optimization(void);			int armada38x_mbus_optimization(void);
				static uint64_t get_sar_value_armada38x(void);

	static int hw_clockrate;			static int hw_clockrate;
	SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,			SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
	&hw_clockrate, 0, "CPU instruction clock rate");			&hw_clockrate, 0, "CPU instruction clock rate");

				static uint64_t
				get_sar_value_armada38x(void)
				{
				uint32_t sar_low, sar_high;

				sar_high = 0;
				sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
				SAMPLE_AT_RESET_ARMADA38X);
				return (((uint64_t)sar_high << 32) \| sar_low);
				}

	uint32_t			uint32_t
	get_tclk(void)			get_tclk(void)
	{			{
	uint32_t sar;			uint32_t sar;

	/*			/*
	* On Armada38x TCLK can be configured to 250 MHz or 200 MHz.			* On Armada38x TCLK can be configured to 250 MHz or 200 MHz.
	* Current setting is read from Sample At Reset register.			* Current setting is read from Sample At Reset register.
	*/			*/
	sar = (uint32_t)get_sar_value();			sar = (uint32_t)get_sar_value_armada38x();
	sar = (sar & TCLK_MASK) >> TCLK_SHIFT;			sar = (sar & TCLK_MASK_ARMADA38X) >> TCLK_SHIFT_ARMADA38X;
	if (sar == 0)			if (sar == 0)
	return (TCLK_250MHZ);			return (TCLK_250MHZ);
	else			else
	return (TCLK_200MHZ);			return (TCLK_200MHZ);
	}			}

	uint32_t			uint32_t
	get_cpu_freq(void)			get_cpu_freq(void)
	{			{
	uint32_t sar;			uint32_t sar;

	static const uint32_t cpu_frequencies[] = {			static const uint32_t cpu_frequencies[] = {
	0, 0, 0, 0,			0, 0, 0, 0,
	1066, 0, 0, 0,			1066, 0, 0, 0,
	1332, 0, 0, 0,			1332, 0, 0, 0,
	1600, 0, 0, 0,			1600, 0, 0, 0,
	1866, 0, 0, 2000			1866, 0, 0, 2000
	};			};

	sar = (uint32_t)get_sar_value();			sar = (uint32_t)get_sar_value_armada38x();
	sar = (sar & A38X_CPU_DDR_CLK_MASK) >> A38X_CPU_DDR_CLK_SHIFT;			sar = (sar & A38X_CPU_DDR_CLK_MASK) >> A38X_CPU_DDR_CLK_SHIFT;
	if (sar >= nitems(cpu_frequencies))			if (sar >= nitems(cpu_frequencies))
	return (0);			return (0);

	hw_clockrate = cpu_frequencies[sar];			hw_clockrate = cpu_frequencies[sar];

	return (hw_clockrate * 1000 * 1000);			return (hw_clockrate * 1000 * 1000);
	}			}
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