Differential D14734 Diff 41056 head/sys/arm/mv/mpic.c

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head/sys/arm/mv/mpic.c

Show First 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
#define MPIC_ISM 0x48		#define MPIC_ISM 0x48
#define MPIC_ICM 0x4c		#define MPIC_ICM 0x4c
#define MPIC_ERR_MASK 0x50		#define MPIC_ERR_MASK 0x50
#define MPIC_LOCAL_MASK 0x54		#define MPIC_LOCAL_MASK 0x54
#define MPIC_CPU(n) (n) * 0x100		#define MPIC_CPU(n) (n) * 0x100

#define MPIC_PPI 32		#define MPIC_PPI 32

#ifdef INTRNG
struct mv_mpic_irqsrc {		struct mv_mpic_irqsrc {
struct intr_irqsrc mmi_isrc;		struct intr_irqsrc mmi_isrc;
u_int mmi_irq;		u_int mmi_irq;
};		};
#endif

struct mv_mpic_softc {		struct mv_mpic_softc {
device_t sc_dev;		device_t sc_dev;
struct resource * mpic_res[4];		struct resource * mpic_res[4];
bus_space_tag_t mpic_bst;		bus_space_tag_t mpic_bst;
bus_space_handle_t mpic_bsh;		bus_space_handle_t mpic_bsh;
bus_space_tag_t cpu_bst;		bus_space_tag_t cpu_bst;
bus_space_handle_t cpu_bsh;		bus_space_handle_t cpu_bsh;
bus_space_tag_t drbl_bst;		bus_space_tag_t drbl_bst;
bus_space_handle_t drbl_bsh;		bus_space_handle_t drbl_bsh;
struct mtx mtx;		struct mtx mtx;
#ifdef INTRNG
struct mv_mpic_irqsrc * mpic_isrcs;		struct mv_mpic_irqsrc * mpic_isrcs;
#endif
int nirqs;		int nirqs;
void * intr_hand;		void * intr_hand;
};		};

static struct resource_spec mv_mpic_spec[] = {		static struct resource_spec mv_mpic_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },		{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ SYS_RES_MEMORY, 1, RF_ACTIVE },		{ SYS_RES_MEMORY, 1, RF_ACTIVE },
{ SYS_RES_MEMORY, 2, RF_ACTIVE \| RF_OPTIONAL },		{ SYS_RES_MEMORY, 2, RF_ACTIVE \| RF_OPTIONAL },
Show All 16 Lines
uint32_t mv_mpic_get_cause(void);		uint32_t mv_mpic_get_cause(void);
uint32_t mv_mpic_get_cause_err(void);		uint32_t mv_mpic_get_cause_err(void);
uint32_t mv_mpic_get_msi(void);		uint32_t mv_mpic_get_msi(void);
static void mpic_unmask_irq(uintptr_t nb);		static void mpic_unmask_irq(uintptr_t nb);
static void mpic_mask_irq(uintptr_t nb);		static void mpic_mask_irq(uintptr_t nb);
static void mpic_mask_irq_err(uintptr_t nb);		static void mpic_mask_irq_err(uintptr_t nb);
static void mpic_unmask_irq_err(uintptr_t nb);		static void mpic_unmask_irq_err(uintptr_t nb);
static boolean_t mpic_irq_is_percpu(uintptr_t);		static boolean_t mpic_irq_is_percpu(uintptr_t);
#ifdef INTRNG
static int mpic_intr(void *arg);		static int mpic_intr(void *arg);
#endif
static void mpic_unmask_msi(void);		static void mpic_unmask_msi(void);
		void mpic_init_secondary(device_t);
		void mpic_ipi_send(device_t, struct intr_irqsrc*, cpuset_t, u_int);
		int mpic_ipi_read(int);
		void mpic_ipi_clear(int);

#define MPIC_WRITE(softc, reg, val) \		#define MPIC_WRITE(softc, reg, val) \
bus_space_write_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg), (val))		bus_space_write_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg), (val))
#define MPIC_READ(softc, reg) \		#define MPIC_READ(softc, reg) \
bus_space_read_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg))		bus_space_read_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg))

#define MPIC_CPU_WRITE(softc, reg, val) \		#define MPIC_CPU_WRITE(softc, reg, val) \
bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val))		bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val))
Show All 14 Lines	mv_mpic_probe(device_t dev)

if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)		if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
return (ENXIO);		return (ENXIO);

device_set_desc(dev, "Marvell Integrated Interrupt Controller");		device_set_desc(dev, "Marvell Integrated Interrupt Controller");
return (0);		return (0);
}		}

#ifdef INTRNG
static int		static int
mv_mpic_register_isrcs(struct mv_mpic_softc *sc)		mv_mpic_register_isrcs(struct mv_mpic_softc *sc)
{		{
int error;		int error;
uint32_t irq;		uint32_t irq;
struct intr_irqsrc *isrc;		struct intr_irqsrc *isrc;
const char *name;		const char *name;

Show All 15 Lines	for (irq = 0; irq < sc->nirqs; irq++) {
if (error != 0) {		if (error != 0) {
/* XXX call intr_isrc_deregister() */		/* XXX call intr_isrc_deregister() */
device_printf(sc->sc_dev, "%s failed", __func__);		device_printf(sc->sc_dev, "%s failed", __func__);
return (error);		return (error);
}		}
}		}
return (0);		return (0);
}		}
#endif

static int		static int
mv_mpic_attach(device_t dev)		mv_mpic_attach(device_t dev)
{		{
struct mv_mpic_softc *sc;		struct mv_mpic_softc *sc;
int error;		int error;
uint32_t val;		uint32_t val;
int cpu;		int cpu;

sc = (struct mv_mpic_softc *)device_get_softc(dev);		sc = (struct mv_mpic_softc *)device_get_softc(dev);

if (mv_mpic_sc != NULL)		if (mv_mpic_sc != NULL)
return (ENXIO);		return (ENXIO);
mv_mpic_sc = sc;		mv_mpic_sc = sc;

sc->sc_dev = dev;		sc->sc_dev = dev;

mtx_init(&sc->mtx, "MPIC lock", NULL, MTX_SPIN);		mtx_init(&sc->mtx, "MPIC lock", NULL, MTX_SPIN);

error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res);		error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res);
if (error) {		if (error) {
device_printf(dev, "could not allocate resources\n");		device_printf(dev, "could not allocate resources\n");
return (ENXIO);		return (ENXIO);
}		}
#ifdef INTRNG
if (sc->mpic_res[3] == NULL)		if (sc->mpic_res[3] == NULL)
device_printf(dev, "No interrupt to use.\n");		device_printf(dev, "No interrupt to use.\n");
else		else
bus_setup_intr(dev, sc->mpic_res[3], INTR_TYPE_CLK,		bus_setup_intr(dev, sc->mpic_res[3], INTR_TYPE_CLK,
mpic_intr, NULL, sc, &sc->intr_hand);		mpic_intr, NULL, sc, &sc->intr_hand);
#endif

sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]);		sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]);
sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]);		sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]);

sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]);		sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]);
sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]);		sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]);

if (sc->mpic_res[2] != NULL) {		if (sc->mpic_res[2] != NULL) {
/* This is required only if MSIs are used. */		/* This is required only if MSIs are used. */
sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]);		sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]);
sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]);		sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]);
}		}

MPIC_WRITE(mv_mpic_sc, MPIC_CTRL, 1);		MPIC_WRITE(mv_mpic_sc, MPIC_CTRL, 1);
MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0);		MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0);

val = MPIC_READ(mv_mpic_sc, MPIC_CTRL);		val = MPIC_READ(mv_mpic_sc, MPIC_CTRL);
sc->nirqs = MPIC_CTRL_NIRQS(val);		sc->nirqs = MPIC_CTRL_NIRQS(val);

#ifdef INTRNG
if (mv_mpic_register_isrcs(sc) != 0) {		if (mv_mpic_register_isrcs(sc) != 0) {
device_printf(dev, "could not register PIC ISRCs\n");		device_printf(dev, "could not register PIC ISRCs\n");
bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);		bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
return (ENXIO);		return (ENXIO);
}		}

OF_device_register_xref(OF_xref_from_node(ofw_bus_get_node(dev)), dev);		OF_device_register_xref(OF_xref_from_node(ofw_bus_get_node(dev)), dev);

if (intr_pic_register(dev, OF_xref_from_device(dev)) == NULL) {		if (intr_pic_register(dev, OF_xref_from_device(dev)) == NULL) {
device_printf(dev, "could not register PIC\n");		device_printf(dev, "could not register PIC\n");
bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);		bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
return (ENXIO);		return (ENXIO);
}		}
#endif

mpic_unmask_msi();		mpic_unmask_msi();

/* Unmask CPU performance counters overflow irq */		/* Unmask CPU performance counters overflow irq */
for (cpu = 0; cpu < mp_ncpus; cpu++)		for (cpu = 0; cpu < mp_ncpus; cpu++)
MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CPU(cpu) + MPIC_LOCAL_MASK,		MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CPU(cpu) + MPIC_LOCAL_MASK,
(1 << cpu) \| MPIC_CPU_READ(mv_mpic_sc,		(1 << cpu) \| MPIC_CPU_READ(mv_mpic_sc,
MPIC_CPU(cpu) + MPIC_LOCAL_MASK));		MPIC_CPU(cpu) + MPIC_LOCAL_MASK));

return (0);		return (0);
}		}

#ifdef INTRNG
static int		static int
mpic_intr(void *arg)		mpic_intr(void *arg)
{		{
struct mv_mpic_softc *sc;		struct mv_mpic_softc *sc;
uint32_t cause, irqsrc;		uint32_t cause, irqsrc;
unsigned int irq;		unsigned int irq;
u_int cpuid;		u_int cpuid;

▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines	mpic_post_ithread(device_t dev, struct intr_irqsrc *isrc)

mpic_enable_intr(dev, isrc);		mpic_enable_intr(dev, isrc);
}		}

static void		static void
mpic_post_filter(device_t dev, struct intr_irqsrc *isrc)		mpic_post_filter(device_t dev, struct intr_irqsrc *isrc)
{		{
}		}
#endif

static device_method_t mv_mpic_methods[] = {		static device_method_t mv_mpic_methods[] = {
DEVMETHOD(device_probe, mv_mpic_probe),		DEVMETHOD(device_probe, mv_mpic_probe),
DEVMETHOD(device_attach, mv_mpic_attach),		DEVMETHOD(device_attach, mv_mpic_attach),

#ifdef INTRNG
DEVMETHOD(pic_disable_intr, mpic_disable_intr),		DEVMETHOD(pic_disable_intr, mpic_disable_intr),
DEVMETHOD(pic_enable_intr, mpic_enable_intr),		DEVMETHOD(pic_enable_intr, mpic_enable_intr),
DEVMETHOD(pic_map_intr, mpic_map_intr),		DEVMETHOD(pic_map_intr, mpic_map_intr),
DEVMETHOD(pic_post_filter, mpic_post_filter),		DEVMETHOD(pic_post_filter, mpic_post_filter),
DEVMETHOD(pic_post_ithread, mpic_post_ithread),		DEVMETHOD(pic_post_ithread, mpic_post_ithread),
DEVMETHOD(pic_pre_ithread, mpic_pre_ithread),		DEVMETHOD(pic_pre_ithread, mpic_pre_ithread),
#endif		DEVMETHOD(pic_init_secondary, mpic_init_secondary),
		DEVMETHOD(pic_ipi_send, mpic_ipi_send),
{ 0, 0 }		{ 0, 0 }
};		};

static driver_t mv_mpic_driver = {		static driver_t mv_mpic_driver = {
"mpic",		"mpic",
mv_mpic_methods,		mv_mpic_methods,
sizeof(struct mv_mpic_softc),		sizeof(struct mv_mpic_softc),
};		};

static devclass_t mv_mpic_devclass;		static devclass_t mv_mpic_devclass;

EARLY_DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0,		EARLY_DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0,
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);		BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);

#ifndef INTRNG
int
arm_get_next_irq(int last)
{
u_int irq, next = -1;

irq = mv_mpic_get_cause() & MPIC_IRQ_MASK;
CTR2(KTR_INTR, "%s: irq:%#x", __func__, irq);

if (irq != MPIC_IRQ_MASK) {
if (irq == MPIC_INT_ERR)
irq = mv_mpic_get_cause_err();
if (irq == MPIC_INT_MSI)
irq = mv_mpic_get_msi();
next = irq;
}

CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next);
return (next);
}

/*
* XXX We can make arm_enable_irq to operate on ICE and then mask/unmask only
* by ISM/ICM and remove access to ICE in masking operation
*/
void
arm_mask_irq(uintptr_t nb)
{

mpic_mask_irq(nb);
}

void
arm_unmask_irq(uintptr_t nb)
{

mpic_unmask_irq(nb);
}
#endif

static void		static void
mpic_unmask_msi(void)		mpic_unmask_msi(void)
{		{

mpic_unmask_irq(MPIC_INT_MSI);		mpic_unmask_irq(MPIC_INT_MSI);
}		}

static void		static void
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Lines	mv_msi_data(int irq, uint64_t addr, uint32_t data)
}		}

*addr = phys + base + MPIC_SOFT_INT;		*addr = phys + base + MPIC_SOFT_INT;
*data = MPIC_SOFT_INT_DRBL1 \| irq;		*data = MPIC_SOFT_INT_DRBL1 \| irq;

return (0);		return (0);
}		}


#if defined(SMP) && defined(SOC_MV_ARMADAXP)
void		void
intr_pic_init_secondary(void)		mpic_init_secondary(device_t dev)
{		{
}		}

void		void
pic_ipi_send(cpuset_t cpus, u_int ipi)		mpic_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus, u_int ipi)
{		{
uint32_t val, i;		uint32_t val, i;

val = 0x00000000;		val = 0x00000000;
for (i = 0; i < MAXCPU; i++)		for (i = 0; i < MAXCPU; i++)
if (CPU_ISSET(i, &cpus))		if (CPU_ISSET(i, &cpus))
val \|= (1 << (8 + i));		val \|= (1 << (8 + i));
val \|= ipi;		val \|= ipi;
MPIC_WRITE(mv_mpic_sc, MPIC_SOFT_INT, val);		MPIC_WRITE(mv_mpic_sc, MPIC_SOFT_INT, val);
}		}

int		int
pic_ipi_read(int i __unused)		mpic_ipi_read(int i __unused)
{		{
uint32_t val;		uint32_t val;
int ipi;		int ipi;

val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL);		val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL);
if (val) {		if (val) {
ipi = ffs(val) - 1;		ipi = ffs(val) - 1;
MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, ~(1 << ipi));		MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, ~(1 << ipi));
return (ipi);		return (ipi);
}		}

return (0x3ff);		return (0x3ff);
}		}

void		void
pic_ipi_clear(int ipi)		mpic_ipi_clear(int ipi)
{		{
}		}

#endif