Differential D14761 Diff 40475 sys/dts/arm/armada-38x.dtsi

Changeset View

Standalone View

sys/dts/arm/armada-38x.dtsi

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines	/ {
model = "Marvell Armada 38x family SoC";		model = "Marvell Armada 38x family SoC";
compatible = "marvell,armada380";		compatible = "marvell,armada380";

aliases {		aliases {
gpio0 = &gpio0;		gpio0 = &gpio0;
gpio1 = &gpio1;		gpio1 = &gpio1;
serial0 = &uart0;		serial0 = &uart0;
serial1 = &uart1;		serial1 = &uart1;
sram0 = &SRAM0;
sram1 = &SRAM1;
};		};

pmu {		pmu {
compatible = "arm,cortex-a9-pmu";		compatible = "arm,cortex-a9-pmu";
interrupts-extended = <&mpic 3>;		interrupts-extended = <&mpic 3>;
};		};

SRAM0: sram@f1100000 {
compatible = "mrvl,cesa-sram";
reg = <0xf1100000 0x0010000>;
};

SRAM1: sram@f1110000 {
compatible = "mrvl,cesa-sram";
reg = <0xf1110000 0x0010000>;
};

soc {		soc {
compatible = "marvell,armada380-mbus", "simple-bus";		compatible = "marvell,armada380-mbus", "simple-bus";
#address-cells = <2>;		#address-cells = <2>;
#size-cells = <1>;		#size-cells = <1>;
controller = <&mbusc>;		controller = <&mbusc>;
interrupt-parent = <&gic>;		interrupt-parent = <&gic>;
pcie-mem-aperture = <0xe0000000 0x8000000>;		pcie-mem-aperture = <0xe0000000 0x8000000>;
pcie-io-aperture = <0xe8000000 0x100000>;		pcie-io-aperture = <0xe8000000 0x100000>;
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines	soc {
};		};

internal-regs {		internal-regs {
compatible = "simple-bus";		compatible = "simple-bus";
#address-cells = <1>;		#address-cells = <1>;
#size-cells = <1>;		#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;		ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

crypto@90000 {
compatible = "mrvl,cesa";
reg = <0x90000 0x1000 /* tdma base reg chan 0 */
0x9D000 0x1000>; /* cesa base reg chan 0 */
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
sram-handle = <&SRAM0>;
status = "disabled";
};

crypto@92000 {
compatible = "mrvl,cesa";
reg = <0x92000 0x1000 /* tdma base reg chan 1 */
0x9F000 0x1000>; /* cesa base reg chan 1 */
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
sram-handle = <&SRAM1>;
status = "disabled";
};

L2: cache-controller@8000 {		L2: cache-controller@8000 {
compatible = "arm,pl310-cache";		compatible = "arm,pl310-cache";
reg = <0x8000 0x1000>;		reg = <0x8000 0x1000>;
cache-unified;		cache-unified;
cache-level = <2>;		cache-level = <2>;
arm,double-linefill-incr = <1>;		arm,double-linefill-incr = <1>;
arm,double-linefill-wrap = <0>;		arm,double-linefill-wrap = <0>;
arm,double-linefill = <1>;		arm,double-linefill = <1>;
▲ Show 20 Lines • Show All 362 Lines • ▼ Show 20 Lines	internal-regs {
mdio: mdio@72004 {		mdio: mdio@72004 {
#address-cells = <1>;		#address-cells = <1>;
#size-cells = <0>;		#size-cells = <0>;
compatible = "marvell,orion-mdio";		compatible = "marvell,orion-mdio";
reg = <0x72004 0x4>;		reg = <0x72004 0x4>;
clocks = <&gateclk 4>;		clocks = <&gateclk 4>;
};		};

rtc@a3800 {		cesa: crypto@90000 {
		compatible = "marvell,armada-38x-crypto";
		reg = <0x90000 0x10000>;
		reg-names = "regs";
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&gateclk 23>, <&gateclk 21>,
		<&gateclk 14>, <&gateclk 16>;
		clock-names = "cesa0", "cesa1",
		"cesaz0", "cesaz1";
		marvell,crypto-srams = <&crypto_sram0>,
		<&crypto_sram1>;
		marvell,crypto-sram-size = <0x800>;
		};

		rtc: rtc@a3800 {
compatible = "marvell,armada-380-rtc";		compatible = "marvell,armada-380-rtc";
reg = <0xa3800 0x20>, <0x184a0 0x0c>;		reg = <0xa3800 0x20>, <0x184a0 0x0c>;
reg-names = "rtc", "rtc-soc";		reg-names = "rtc", "rtc-soc";
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
};		};

sata@a8000 {		sata@a8000 {
compatible = "marvell,armada-380-ahci";		compatible = "marvell,armada-380-ahci";
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines	internal-regs {

usb3@f8000 {		usb3@f8000 {
compatible = "marvell,armada-380-xhci";		compatible = "marvell,armada-380-xhci";
reg = <0xf8000 0x4000>,<0xfc000 0x4000>;		reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 10>;		clocks = <&gateclk 10>;
status = "disabled";		status = "disabled";
};		};
		};

		crypto_sram0: sa-sram0 {
		compatible = "mmio-sram";
		reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
		clocks = <&gateclk 23>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
		};

		crypto_sram1: sa-sram1 {
		compatible = "mmio-sram";
		reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
		clocks = <&gateclk 21>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
};		};

bm_bppi: bm-bppi {		bm_bppi: bm-bppi {
compatible = "mmio-sram";		compatible = "mmio-sram";
reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;		reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;		ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
#address-cells = <1>;		#address-cells = <1>;
#size-cells = <1>;		#size-cells = <1>;
Show All 22 Lines