Differential D14752 Diff 40465 sys/arm/mv/mv_pci_ctrl.c

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sys/arm/mv/mv_pci_ctrl.c

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static int mv_pcib_ofw_bus_attach(device_t);		static int mv_pcib_ofw_bus_attach(device_t);

struct mv_pcib_ctrl_range {		struct mv_pcib_ctrl_range {
uint64_t bus;		uint64_t bus;
uint64_t host;		uint64_t host;
uint64_t size;		uint64_t size;
};		};

		typedef int (*get_rl_t)(device_t dev, phandle_t node, pcell_t acells,
		pcell_t scells, struct resource_list *rl);

struct mv_pcib_ctrl_softc {		struct mv_pcib_ctrl_softc {
pcell_t addr_cells;		pcell_t addr_cells;
pcell_t size_cells;		pcell_t size_cells;
int nranges;		int nranges;
struct mv_pcib_ctrl_range *ranges;		struct mv_pcib_ctrl_range *ranges;
};		};

struct mv_pcib_ctrl_devinfo {		struct mv_pcib_ctrl_devinfo {
Show All 24 Lines	static device_method_t mv_pcib_ctrl_methods[] = {
DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),		DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),		DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),		DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),		DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),

DEVMETHOD_END		DEVMETHOD_END
};		};

		static struct ofw_compat_data mv_pcib_ctrl_compat[] = {
		{"mrvl,pcie-ctrl", (uintptr_t)&ofw_bus_reg_to_rl},
		{"marvell,armada-370-pcie",
		(uintptr_t)&ofw_bus_assigned_addresses_to_rl},
		{NULL, (uintptr_t)NULL},
		};

static driver_t mv_pcib_ctrl_driver = {		static driver_t mv_pcib_ctrl_driver = {
"pcib_ctrl",		"pcib_ctrl",
mv_pcib_ctrl_methods,		mv_pcib_ctrl_methods,
sizeof(struct mv_pcib_ctrl_softc),		sizeof(struct mv_pcib_ctrl_softc),
};		};

devclass_t pcib_ctrl_devclass;		devclass_t pcib_ctrl_devclass;

DRIVER_MODULE(pcib_ctrl, simplebus, mv_pcib_ctrl_driver, pcib_ctrl_devclass, 0, 0);		DRIVER_MODULE(pcib_ctrl, simplebus, mv_pcib_ctrl_driver, pcib_ctrl_devclass, 0, 0);

MALLOC_DEFINE(M_PCIB_CTRL, "PCIe Bus Controller",		MALLOC_DEFINE(M_PCIB_CTRL, "PCIe Bus Controller",
"Marvell Integrated PCIe Bus Controller");		"Marvell Integrated PCIe Bus Controller");

static int		static int
mv_pcib_ctrl_probe(device_t dev)		mv_pcib_ctrl_probe(device_t dev)
{		{

if (!ofw_bus_is_compatible(dev, "mrvl,pcie-ctrl") &&		if (!ofw_bus_status_okay(dev))
!ofw_bus_is_compatible(dev, "marvell,armada-370-pcie"))
return (ENXIO);		return (ENXIO);

		if (!ofw_bus_search_compatible(dev, mv_pcib_ctrl_compat)->ocd_data)
		return (ENXIO);

device_set_desc(dev, "Marvell Integrated PCIe Bus Controller");		device_set_desc(dev, "Marvell Integrated PCIe Bus Controller");
return (BUS_PROBE_DEFAULT);		return (BUS_PROBE_DEFAULT);
}		}

static int		static int
mv_pcib_ctrl_attach(device_t dev)		mv_pcib_ctrl_attach(device_t dev)
{		{
int err;		int err;

err = mv_pcib_ofw_bus_attach(dev);		err = mv_pcib_ofw_bus_attach(dev);
if (err != 0)		if (err != 0)
return (err);		return (err);

return (bus_generic_attach(dev));		return (bus_generic_attach(dev));
}		}

static int		static int
mv_pcib_ofw_bus_attach(device_t dev)		mv_pcib_ofw_bus_attach(device_t dev)
{		{
struct mv_pcib_ctrl_devinfo *di;		struct mv_pcib_ctrl_devinfo *di;
struct mv_pcib_ctrl_softc *sc;		struct mv_pcib_ctrl_softc *sc;
device_t child;		device_t child;
phandle_t parent, node;		phandle_t parent, node;
		get_rl_t get_rl;

parent = ofw_bus_get_node(dev);		parent = ofw_bus_get_node(dev);
sc = device_get_softc(dev);		sc = device_get_softc(dev);
if (parent > 0) {		if (parent > 0) {
sc->addr_cells = 1;		sc->addr_cells = 1;
if (OF_getencprop(parent, "#address-cells", &(sc->addr_cells),		if (OF_getencprop(parent, "#address-cells", &(sc->addr_cells),
sizeof(sc->addr_cells)) <= 0)		sizeof(sc->addr_cells)) <= 0)
return(ENXIO);		return(ENXIO);
Show All 22 Lines	for (node = OF_child(parent); node > 0; node = OF_peer(node)) {
di->di_dinfo.obd_name);		di->di_dinfo.obd_name);
}		}
ofw_bus_gen_destroy_devinfo(&di->di_dinfo);		ofw_bus_gen_destroy_devinfo(&di->di_dinfo);
free(di, M_PCIB_CTRL);		free(di, M_PCIB_CTRL);
continue;		continue;
}		}

resource_list_init(&di->di_rl);		resource_list_init(&di->di_rl);
ofw_bus_reg_to_rl(child, node, sc->addr_cells,		get_rl = (get_rl_t) ofw_bus_search_compatible(dev,
		mv_pcib_ctrl_compat)->ocd_data;
		if (get_rl != NULL)
		get_rl(child, node, sc->addr_cells,
sc->size_cells, &di->di_rl);		sc->size_cells, &di->di_rl);

device_set_ivars(child, di);		device_set_ivars(child, di);
}		}
}		}

if (mv_pcib_ctrl_fill_ranges(parent, sc) < 0) {		if (mv_pcib_ctrl_fill_ranges(parent, sc) < 0) {
device_printf(dev, "could not get ranges\n");		device_printf(dev, "could not get ranges\n");
return (ENXIO);		return (ENXIO);
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