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Differential D14752 Diff 40465 sys/arm/mv/mv_common.c

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sys/arm/mv/mv_common.c

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static int fdt_get_ranges(const char *, void *, int, int *, int *); static int fdt_get_ranges(const char *, void *, int, int *, int *);
int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt, int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt,
int *trig, int *pol); int *trig, int *pol);
static int win_cpu_from_dt(void); static int win_cpu_from_dt(void);
static int fdt_win_setup(void); static int fdt_win_setup(void);
static int fdt_win_process_child(phandle_t, struct soc_node_spec *); static int fdt_win_process_child(phandle_t, struct soc_node_spec *, const char*);
static uint32_t dev_mask = 0; static uint32_t dev_mask = 0;
static int cpu_wins_no = 0; static int cpu_wins_no = 0;
static int eth_port = 0; static int eth_port = 0;
static int usb_port = 0; static int usb_port = 0;
static boolean_t platform_io_coherent = false; static boolean_t platform_io_coherent = false;
static struct decode_win cpu_win_tbl[MAX_CPU_WIN]; static struct decode_win cpu_win_tbl[MAX_CPU_WIN];
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for (i = 0; soc_nodes[i].compat != NULL; i++) { for (i = 0; soc_nodes[i].compat != NULL; i++) {
/* Setup only for enabled devices */ /* Setup only for enabled devices */
if (ofw_bus_node_status_okay(child) == 0) if (ofw_bus_node_status_okay(child) == 0)
continue; continue;
if (!ofw_bus_node_is_compatible(child, soc_nodes[i].compat)) if (!ofw_bus_node_is_compatible(child, soc_nodes[i].compat))
continue; continue;
ret = fdt_win_process_child(child, &soc_nodes[i]); ret = fdt_win_process_child(child, &soc_nodes[i], "reg");
if (ret != 0) if (ret != 0)
return (ret); return (ret);
} }
return (0); return (0);
} }
static int static int
fdt_win_process_child(phandle_t child, struct soc_node_spec *soc_node) fdt_win_process_child(phandle_t child, struct soc_node_spec *soc_node,
const char* mimo_reg_source)
{ {
int addr_cells, size_cells; int addr_cells, size_cells;
pcell_t reg[8]; pcell_t reg[8];
u_long size, base; u_long size, base;
if (fdt_addrsize_cells(OF_parent(child), &addr_cells, if (fdt_addrsize_cells(OF_parent(child), &addr_cells,
&size_cells)) &size_cells))
return (ENXIO); return (ENXIO);
if ((sizeof(pcell_t) * (addr_cells + size_cells)) > sizeof(reg)) if ((sizeof(pcell_t) * (addr_cells + size_cells)) > sizeof(reg))
return (ENOMEM); return (ENOMEM);
if (OF_getprop(child, mimo_reg_source, &reg, sizeof(reg)) <= 0)
if (OF_getprop(child, "reg", &reg, sizeof(reg)) <= 0)
return (EINVAL); return (EINVAL);
if (addr_cells <= 2) if (addr_cells <= 2)
base = fdt_data_get(&reg[0], addr_cells); base = fdt_data_get(&reg[0], addr_cells);
else else
base = fdt_data_get(&reg[addr_cells - 2], 2); base = fdt_data_get(&reg[addr_cells - 2], 2);
size = fdt_data_get(&reg[addr_cells], size_cells); size = fdt_data_get(&reg[addr_cells], size_cells);
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if (err != 0) if (err != 0)
return (err); return (err);
/* Process Marvell Armada-XP/38x PCIe controllers */ /* Process Marvell Armada-XP/38x PCIe controllers */
if (ofw_bus_node_is_compatible(child, "marvell,armada-370-pcie")) { if (ofw_bus_node_is_compatible(child, "marvell,armada-370-pcie")) {
child_pci = OF_child(child); child_pci = OF_child(child);
while (child_pci != 0) { while (child_pci != 0) {
err = fdt_win_process_child(child_pci, err = fdt_win_process_child(child_pci,
&soc_nodes[SOC_NODE_PCIE_ENTRY_IDX]); &soc_nodes[SOC_NODE_PCIE_ENTRY_IDX],
"assigned-addresses");
if (err != 0) if (err != 0)
return (err); return (err);
child_pci = OF_peer(child_pci); child_pci = OF_peer(child_pci);
} }
} }
/* /*
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