Page MenuHomeFreeBSD
Differential D14647 Diff 40247 head/sys/powerpc/aim/aim_machdep.c

Changeset View

Standalone View

View Options

head/sys/powerpc/aim/aim_machdep.c

Show First 20 Lines • Show All 154 Lines • ▼ Show 20 Lines
extern void *decrint, *decrsize; extern void *decrint, *decrsize;
extern void *extint, *extsize; extern void *extint, *extsize;
extern void *dblow, *dbend; extern void *dblow, *dbend;
extern void *imisstrap, *imisssize; extern void *imisstrap, *imisssize;
extern void *dlmisstrap, *dlmisssize; extern void *dlmisstrap, *dlmisssize;
extern void *dsmisstrap, *dsmisssize; extern void *dsmisstrap, *dsmisssize;
extern void *ap_pcpu; extern void *ap_pcpu;
extern void __restartkernel(vm_offset_t, vm_offset_t, vm_offset_t, void *, uint32_t, register_t offset, register_t msr);
void aim_early_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry,
void *mdp, uint32_t mdp_cookie);
void aim_cpu_init(vm_offset_t toc); void aim_cpu_init(vm_offset_t toc);
void void
aim_early_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp,
uint32_t mdp_cookie)
{
register_t scratch;
/*
* If running from an FDT, make sure we are in real mode to avoid
* tromping on firmware page tables. Everything in the kernel assumes
* 1:1 mappings out of firmware, so this won't break anything not
* already broken. This doesn't work if there is live OF, since OF
* may internally use non-1:1 mappings.
*/
if (ofentry == 0)
mtmsr(mfmsr() & ~(PSL_IR | PSL_DR));
#ifdef __powerpc64__
/*
* If in real mode, relocate to high memory so that the kernel
* can execute from the direct map.
*/
if (!(mfmsr() & PSL_DR) &&
(vm_offset_t)&aim_early_init < DMAP_BASE_ADDRESS)
__restartkernel(fdt, 0, ofentry, mdp, mdp_cookie,
DMAP_BASE_ADDRESS, mfmsr());
#endif
/* Various very early CPU fix ups */
switch (mfpvr() >> 16) {
/*
* PowerPC 970 CPUs have a misfeature requested by Apple that
* makes them pretend they have a 32-byte cacheline. Turn this
* off before we measure the cacheline size.
*/
case IBM970:
case IBM970FX:
case IBM970MP:
case IBM970GX:
scratch = mfspr(SPR_HID5);
scratch &= ~HID5_970_DCBZ_SIZE_HI;
mtspr(SPR_HID5, scratch);
break;
#ifdef __powerpc64__
case IBMPOWER7:
case IBMPOWER7PLUS:
case IBMPOWER8:
case IBMPOWER8E:
/* XXX: get from ibm,slb-size in device tree */
n_slbs = 32;
break;
#endif
}
}
void
aim_cpu_init(vm_offset_t toc) aim_cpu_init(vm_offset_t toc)
{ {
size_t trap_offset, trapsize; size_t trap_offset, trapsize;
vm_offset_t trap; vm_offset_t trap;
register_t msr, scratch; register_t msr;
uint8_t *cache_check; uint8_t *cache_check;
int cacheline_warn; int cacheline_warn;
#ifndef __powerpc64__ #ifndef __powerpc64__
int ppc64; int ppc64;
#endif #endif
trap_offset = 0; trap_offset = 0;
cacheline_warn = 0; cacheline_warn = 0;
Show All 13 Lines#endif
/* Bits that users aren't allowed to change */ /* Bits that users aren't allowed to change */
psl_userstatic = ~(PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1); psl_userstatic = ~(PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1);
/* /*
* Mask bits from the SRR1 that aren't really the MSR: * Mask bits from the SRR1 that aren't really the MSR:
* Bits 1-4, 10-15 (ppc32), 33-36, 42-47 (ppc64) * Bits 1-4, 10-15 (ppc32), 33-36, 42-47 (ppc64)
*/ */
psl_userstatic &= ~0x783f0000UL; psl_userstatic &= ~0x783f0000UL;
/* Various very early CPU fix ups */
switch (mfpvr() >> 16) {
/*
* PowerPC 970 CPUs have a misfeature requested by Apple that
* makes them pretend they have a 32-byte cacheline. Turn this
* off before we measure the cacheline size.
*/
case IBM970:
case IBM970FX:
case IBM970MP:
case IBM970GX:
scratch = mfspr(SPR_HID5);
scratch &= ~HID5_970_DCBZ_SIZE_HI;
mtspr(SPR_HID5, scratch);
break;
#ifdef __powerpc64__
case IBMPOWER7:
case IBMPOWER7PLUS:
case IBMPOWER8:
case IBMPOWER8E:
/* XXX: get from ibm,slb-size in device tree */
n_slbs = 32;
break;
#endif
}
/* /*
* Initialize the interrupt tables and figure out our cache line * Initialize the interrupt tables and figure out our cache line
* size and whether or not we need the 64-bit bridge code. * size and whether or not we need the 64-bit bridge code.
*/ */
/* /*
* Disable translation in case the vector area hasn't been * Disable translation in case the vector area hasn't been
▲ Show 20 Lines • Show All 421 Lines • Show Last 20 Lines