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	#define FSL_E6500 0x8040			#define FSL_E6500 0x8040
	#define FSL_E300C1 0x8083			#define FSL_E300C1 0x8083
	#define FSL_E300C2 0x8084			#define FSL_E300C2 0x8084
	#define FSL_E300C3 0x8085			#define FSL_E300C3 0x8085
	#define FSL_E300C4 0x8086			#define FSL_E300C4 0x8086

	#define SPR_LPCR 0x13e /* Logical Partitioning Control */			#define SPR_LPCR 0x13e /* Logical Partitioning Control */
	#define LPCR_LPES 0x008 /* Bit 60 */			#define LPCR_LPES 0x008 /* Bit 60 */
				#define LPCR_PECE_DRBL (1ULL << 16) /* Directed Privileged Doorbell */
				#define LPCR_PECE_HDRBL (1ULL << 15) /* Directed Hypervisor Doorbell */
				#define LPCR_PECE_EXT (1ULL << 14) /* External exceptions */
				#define LPCR_PECE_DECR (1ULL << 13) /* Decrementer exceptions */
				#define LPCR_PECE_ME (1ULL << 12) /* Machine Check and Hypervisor */
				/* Maintenance exceptions */
				#define LPCR_PECE_WAKESET (LPCR_PECE_EXT \| LPCR_PECE_DECR \| LPCR_PECE_ME)

	#define SPR_EPCR 0x133			#define SPR_EPCR 0x133
	#define EPCR_EXTGS 0x80000000			#define EPCR_EXTGS 0x80000000
	#define EPCR_DTLBGS 0x40000000			#define EPCR_DTLBGS 0x40000000
	#define EPCR_ITLBGS 0x20000000			#define EPCR_ITLBGS 0x20000000
	#define EPCR_DSIGS 0x10000000			#define EPCR_DSIGS 0x10000000
	#define EPCR_ISIGS 0x08000000			#define EPCR_ISIGS 0x08000000
	#define EPCR_DUVGS 0x04000000			#define EPCR_DUVGS 0x04000000
	#define EPCR_ICM 0x02000000			#define EPCR_ICM 0x02000000
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