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Show First 20 Lines • Show All 392 Lines • ▼ Show 20 Lines	case MPC7457:
reg = mpc74xx_l1i_enable();		reg = mpc74xx_l1i_enable();

break;		break;
case IBMPOWER7:		case IBMPOWER7:
case IBMPOWER7PLUS:		case IBMPOWER7PLUS:
case IBMPOWER8:		case IBMPOWER8:
case IBMPOWER8E:		case IBMPOWER8E:
#ifdef __powerpc64__		#ifdef __powerpc64__
if (mfmsr() & PSL_HV)		if (mfmsr() & PSL_HV) {
mtspr(SPR_LPCR, mfspr(SPR_LPCR) \| LPCR_LPES);		mtspr(SPR_LPCR, mfspr(SPR_LPCR) \| LPCR_LPES \|
		LPCR_PECE_WAKESET);
		isync();
		}
#endif		#endif
break;		break;
default:		default:
#ifdef __powerpc64__		#ifdef __powerpc64__
if (!(mfmsr() & PSL_HV)) /* Rely on HV to have set things up */		if (!(mfmsr() & PSL_HV)) /* Rely on HV to have set things up */
break;		break;
#endif		#endif
printf("WARNING: Unknown CPU type. Cache performace may be "		printf("WARNING: Unknown CPU type. Cache performace may be "
"suboptimal.\n");		"suboptimal.\n");
break;		break;
}		}
}		}