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sys/amd64/amd64/initcpu.c
| Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines | SYSCTL_INT(_hw, OID_AUTO, lower_amd64_sharedpage, CTLFLAG_RDTUN, | ||||
| &hw_lower_amd64_sharedpage, 0, | &hw_lower_amd64_sharedpage, 0, | ||||
| "Lower sharedpage to work around Ryzen issue with executing code near the top of user memory"); | "Lower sharedpage to work around Ryzen issue with executing code near the top of user memory"); | ||||
| /* | /* | ||||
| * -1: automatic (default) | * -1: automatic (default) | ||||
| * 0: keep enable CLFLUSH | * 0: keep enable CLFLUSH | ||||
| * 1: force disable CLFLUSH | * 1: force disable CLFLUSH | ||||
| */ | */ | ||||
| static int hw_clflush_disable = -1; | static int hw_clflush_disable = -1; | ||||
| uint32_t efer_nxe = 0; | |||||
| static void | static void | ||||
| init_amd(void) | init_amd(void) | ||||
| { | { | ||||
| uint64_t msr; | uint64_t msr; | ||||
| /* | /* | ||||
| * Work around Erratum 721 for Family 10h and 12h processors. | * Work around Erratum 721 for Family 10h and 12h processors. | ||||
| ▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines | initializecpu(void) | ||||
| * Postpone enabling the SMEP on the boot CPU until the page | * Postpone enabling the SMEP on the boot CPU until the page | ||||
| * tables are switched from the boot loader identity mapping | * tables are switched from the boot loader identity mapping | ||||
| * to the kernel tables. The boot loader enables the U bit in | * to the kernel tables. The boot loader enables the U bit in | ||||
| * its tables. | * its tables. | ||||
| */ | */ | ||||
| if (!IS_BSP() && (cpu_stdext_feature & CPUID_STDEXT_SMEP)) | if (!IS_BSP() && (cpu_stdext_feature & CPUID_STDEXT_SMEP)) | ||||
| cr4 |= CR4_SMEP; | cr4 |= CR4_SMEP; | ||||
| load_cr4(cr4); | load_cr4(cr4); | ||||
| if ((amd_feature & AMDID_NX) != 0) { | if (IS_BSP() && (amd_feature & AMDID_NX) != 0) { | ||||
| msr = rdmsr(MSR_EFER) | EFER_NXE; | msr = rdmsr(MSR_EFER) | EFER_NXE; | ||||
| wrmsr(MSR_EFER, msr); | wrmsr(MSR_EFER, msr); | ||||
| pg_nx = PG_NX; | pg_nx = PG_NX; | ||||
| efer_nxe = EFER_NXE; | |||||
| } | } | ||||
| hw_ibrs_recalculate(); | hw_ibrs_recalculate(); | ||||
| switch (cpu_vendor_id) { | switch (cpu_vendor_id) { | ||||
| case CPU_VENDOR_AMD: | case CPU_VENDOR_AMD: | ||||
| init_amd(); | init_amd(); | ||||
| break; | break; | ||||
| case CPU_VENDOR_CENTAUR: | case CPU_VENDOR_CENTAUR: | ||||
| init_via(); | init_via(); | ||||
| Show All 36 Lines | |||||