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head/sys/x86/include/specialreg.h
| Show First 20 Lines • Show All 691 Lines • ▼ Show 20 Lines | |||||
| #define IA32_MISC_EN_PERFMON 0x0000000000000080ULL | #define IA32_MISC_EN_PERFMON 0x0000000000000080ULL | ||||
| #define IA32_MISC_EN_PEBSU 0x0000000000001000ULL | #define IA32_MISC_EN_PEBSU 0x0000000000001000ULL | ||||
| #define IA32_MISC_EN_ESSTE 0x0000000000010000ULL | #define IA32_MISC_EN_ESSTE 0x0000000000010000ULL | ||||
| #define IA32_MISC_EN_MONE 0x0000000000040000ULL | #define IA32_MISC_EN_MONE 0x0000000000040000ULL | ||||
| #define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL | #define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL | ||||
| #define IA32_MISC_EN_xTPRD 0x0000000000800000ULL | #define IA32_MISC_EN_xTPRD 0x0000000000800000ULL | ||||
| #define IA32_MISC_EN_XDD 0x0000000400000000ULL | #define IA32_MISC_EN_XDD 0x0000000400000000ULL | ||||
| /* | |||||
| * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel' | |||||
| * document 336996-001 Speculative Execution Side Channel Mitigations. | |||||
| */ | |||||
| /* MSR IA32_SPEC_CTRL */ | /* MSR IA32_SPEC_CTRL */ | ||||
| #define IA32_SPEC_CTRL_IBRS 0x0000000000000001ULL | #define IA32_SPEC_CTRL_IBRS 0x0000000000000001ULL | ||||
| #define IA32_SPEC_CTRL_STIBP 0x0000000000000002ULL | #define IA32_SPEC_CTRL_STIBP 0x0000000000000002ULL | ||||
| /* MSR IA32_PRED_CMD */ | /* MSR IA32_PRED_CMD */ | ||||
| #define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL | #define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL | ||||
| /* | /* | ||||
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