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head/sys/arm/arm/swtch-v6.S
Show First 20 Lines • Show All 139 Lines • ▼ Show 20 Lines | ENTRY(cpu_context_switch) | ||||
mcr CP15_TLBIASID(r2) /* flush not global TLBs */ | mcr CP15_TLBIASID(r2) /* flush not global TLBs */ | ||||
/* | /* | ||||
* Flush entire Branch Target Cache because of the branch predictor | * Flush entire Branch Target Cache because of the branch predictor | ||||
* is not architecturally invisible. See ARM Architecture Reference | * is not architecturally invisible. See ARM Architecture Reference | ||||
* Manual ARMv7-A and ARMv7-R edition, page B2-1264(65), Branch | * Manual ARMv7-A and ARMv7-R edition, page B2-1264(65), Branch | ||||
* predictors and Requirements for branch predictor maintenance | * predictors and Requirements for branch predictor maintenance | ||||
* operations sections. | * operations sections. | ||||
*/ | */ | ||||
mcr CP15_BPIALL /* flush entire Branch Target Cache */ | /* | ||||
* Additionally, to mitigate mistrained branch predictor attack | |||||
* we must invalidate it on affected CPUs. Unfortunately, BPIALL | |||||
* is effectively NOP on Cortex-A15 so it needs special treatment. | |||||
*/ | |||||
ldr r0, [r8, #PC_BP_HARDEN_KIND] | |||||
cmp r0, #PCPU_BP_HARDEN_KIND_ICIALLU | |||||
mcrne CP15_BPIALL /* Flush entire Branch Target Cache */ | |||||
mcreq CP15_ICIALLU /* This is the only way how to flush */ | |||||
/* Branch Target Cache on Cortex-A15. */ | |||||
DSB | DSB | ||||
mov pc, lr | mov pc, lr | ||||
END(cpu_context_switch) | END(cpu_context_switch) | ||||
/* | /* | ||||
* cpu_throw(oldtd, newtd) | * cpu_throw(oldtd, newtd) | ||||
* | * | ||||
* Remove current thread state, then select the next thread to run | * Remove current thread state, then select the next thread to run | ||||
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