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Differential D13518 Diff 38239 sys/dev/bwn/if_bwn_phy_lp.c

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sys/dev/bwn/if_bwn_phy_lp.c

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines
#include <dev/pci/pcireg.h> #include <dev/pci/pcireg.h>
#include <net80211/ieee80211_var.h> #include <net80211/ieee80211_var.h>
#include <net80211/ieee80211_radiotap.h> #include <net80211/ieee80211_radiotap.h>
#include <net80211/ieee80211_regdomain.h> #include <net80211/ieee80211_regdomain.h>
#include <net80211/ieee80211_phy.h> #include <net80211/ieee80211_phy.h>
#include <net80211/ieee80211_ratectl.h> #include <net80211/ieee80211_ratectl.h>
#include <dev/bwn/if_bwn_siba.h> #include <dev/bhnd/bhnd.h>
#include <dev/bhnd/bhnd_ids.h>
#include <dev/bhnd/cores/pmu/bhnd_pmu.h>
#include <dev/bwn/if_bwnreg.h> #include <dev/bwn/if_bwnreg.h>
#include <dev/bwn/if_bwnvar.h> #include <dev/bwn/if_bwnvar.h>
#include <dev/bwn/if_bwn_debug.h> #include <dev/bwn/if_bwn_debug.h>
#include <dev/bwn/if_bwn_misc.h> #include <dev/bwn/if_bwn_misc.h>
#include <dev/bwn/if_bwn_util.h> #include <dev/bwn/if_bwn_util.h>
#include <dev/bwn/if_bwn_phy_common.h> #include <dev/bwn/if_bwn_phy_common.h>
#include <dev/bwn/if_bwn_phy_lp.h> #include <dev/bwn/if_bwn_phy_lp.h>
static void bwn_phy_lp_readsprom(struct bwn_mac *); #include "bhnd_nvram_map.h"
static int bwn_phy_lp_readsprom(struct bwn_mac *);
static void bwn_phy_lp_bbinit(struct bwn_mac *); static void bwn_phy_lp_bbinit(struct bwn_mac *);
static void bwn_phy_lp_txpctl_init(struct bwn_mac *); static void bwn_phy_lp_txpctl_init(struct bwn_mac *);
static void bwn_phy_lp_calib(struct bwn_mac *); static void bwn_phy_lp_calib(struct bwn_mac *);
static int bwn_phy_lp_b2062_switch_channel(struct bwn_mac *, uint8_t); static int bwn_phy_lp_b2062_switch_channel(struct bwn_mac *, uint8_t);
static int bwn_phy_lp_b2063_switch_channel(struct bwn_mac *, uint8_t); static int bwn_phy_lp_b2063_switch_channel(struct bwn_mac *, uint8_t);
static void bwn_phy_lp_set_anafilter(struct bwn_mac *, uint8_t); static void bwn_phy_lp_set_anafilter(struct bwn_mac *, uint8_t);
static void bwn_phy_lp_set_gaintbl(struct bwn_mac *, uint32_t); static void bwn_phy_lp_set_gaintbl(struct bwn_mac *, uint32_t);
static void bwn_phy_lp_digflt_save(struct bwn_mac *); static void bwn_phy_lp_digflt_save(struct bwn_mac *);
static void bwn_phy_lp_get_txpctlmode(struct bwn_mac *); static void bwn_phy_lp_get_txpctlmode(struct bwn_mac *);
static void bwn_phy_lp_set_txpctlmode(struct bwn_mac *, uint8_t); static void bwn_phy_lp_set_txpctlmode(struct bwn_mac *, uint8_t);
static void bwn_phy_lp_bugfix(struct bwn_mac *); static void bwn_phy_lp_bugfix(struct bwn_mac *);
static void bwn_phy_lp_digflt_restore(struct bwn_mac *); static void bwn_phy_lp_digflt_restore(struct bwn_mac *);
static void bwn_phy_lp_tblinit(struct bwn_mac *); static void bwn_phy_lp_tblinit(struct bwn_mac *);
static void bwn_phy_lp_bbinit_r2(struct bwn_mac *); static void bwn_phy_lp_bbinit_r2(struct bwn_mac *);
static void bwn_phy_lp_bbinit_r01(struct bwn_mac *); static void bwn_phy_lp_bbinit_r01(struct bwn_mac *);
static void bwn_phy_lp_b2062_init(struct bwn_mac *); static int bwn_phy_lp_b2062_init(struct bwn_mac *);
static void bwn_phy_lp_b2063_init(struct bwn_mac *); static int bwn_phy_lp_b2063_init(struct bwn_mac *);
static void bwn_phy_lp_rxcal_r2(struct bwn_mac *); static int bwn_phy_lp_rxcal_r2(struct bwn_mac *);
static void bwn_phy_lp_rccal_r12(struct bwn_mac *); static int bwn_phy_lp_rccal_r12(struct bwn_mac *);
static void bwn_phy_lp_set_rccap(struct bwn_mac *); static void bwn_phy_lp_set_rccap(struct bwn_mac *);
static uint32_t bwn_phy_lp_roundup(uint32_t, uint32_t, uint8_t); static uint32_t bwn_phy_lp_roundup(uint32_t, uint32_t, uint8_t);
static void bwn_phy_lp_b2062_reset_pllbias(struct bwn_mac *); static void bwn_phy_lp_b2062_reset_pllbias(struct bwn_mac *);
static void bwn_phy_lp_b2062_vco_calib(struct bwn_mac *); static void bwn_phy_lp_b2062_vco_calib(struct bwn_mac *);
static void bwn_tab_write_multi(struct bwn_mac *, uint32_t, int, static void bwn_tab_write_multi(struct bwn_mac *, uint32_t, int,
const void *); const void *);
static void bwn_tab_read_multi(struct bwn_mac *, uint32_t, int, void *); static void bwn_tab_read_multi(struct bwn_mac *, uint32_t, int, void *);
static struct bwn_txgain static struct bwn_txgain
▲ Show 20 Lines • Show All 290 Lines • ▼ Show 20 Linesbwn_phy_lp_init(struct bwn_mac *mac)
}; };
struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
struct bwn_softc *sc = mac->mac_sc; struct bwn_softc *sc = mac->mac_sc;
const struct bwn_stxtable *st; const struct bwn_stxtable *st;
struct ieee80211com *ic = &sc->sc_ic; struct ieee80211com *ic = &sc->sc_ic;
int i, error; int i, error;
uint16_t tmp; uint16_t tmp;
bwn_phy_lp_readsprom(mac); /* XXX bad place */ /* All LP-PHY devices have a PMU */
if (sc->sc_pmu == NULL) {
device_printf(sc->sc_dev, "no PMU; cannot configure PAREF "
"LDO\n");
return (ENXIO);
}
if ((error = bwn_phy_lp_readsprom(mac)))
return (error);
bwn_phy_lp_bbinit(mac); bwn_phy_lp_bbinit(mac);
/* initialize RF */ /* initialize RF */
BWN_PHY_SET(mac, BWN_PHY_4WIRECTL, 0x2); BWN_PHY_SET(mac, BWN_PHY_4WIRECTL, 0x2);
DELAY(1); DELAY(1);
BWN_PHY_MASK(mac, BWN_PHY_4WIRECTL, 0xfffd); BWN_PHY_MASK(mac, BWN_PHY_4WIRECTL, 0xfffd);
DELAY(1); DELAY(1);
if (mac->mac_phy.rf_ver == 0x2062) if (mac->mac_phy.rf_ver == 0x2062) {
bwn_phy_lp_b2062_init(mac); if ((error = bwn_phy_lp_b2062_init(mac)))
else { return (error);
bwn_phy_lp_b2063_init(mac); } else {
if ((error = bwn_phy_lp_b2063_init(mac)))
return (error);
/* synchronize stx table. */ /* synchronize stx table. */
for (i = 0; i < N(tables); i++) { for (i = 0; i < N(tables); i++) {
st = &tables[i]; st = &tables[i];
tmp = BWN_RF_READ(mac, st->st_rfaddr); tmp = BWN_RF_READ(mac, st->st_rfaddr);
tmp >>= st->st_rfshift; tmp >>= st->st_rfshift;
tmp <<= st->st_physhift; tmp <<= st->st_physhift;
BWN_PHY_SETMASK(mac, BWN_PHY_SETMASK(mac,
BWN_PHY_OFDM(0xf2 + st->st_phyoffset), BWN_PHY_OFDM(0xf2 + st->st_phyoffset),
~(st->st_mask << st->st_physhift), tmp); ~(st->st_mask << st->st_physhift), tmp);
} }
BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xf0), 0x5f80); BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xf0), 0x5f80);
BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xf1), 0); BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xf1), 0);
} }
/* calibrate RC */ /* calibrate RC */
if (mac->mac_phy.rev >= 2) if (mac->mac_phy.rev >= 2) {
bwn_phy_lp_rxcal_r2(mac); if ((error = bwn_phy_lp_rxcal_r2(mac)))
else if (!plp->plp_rccap) { return (error);
if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) } else if (!plp->plp_rccap) {
bwn_phy_lp_rccal_r12(mac); if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) {
if ((error = bwn_phy_lp_rccal_r12(mac)))
return (error);
}
} else } else
bwn_phy_lp_set_rccap(mac); bwn_phy_lp_set_rccap(mac);
error = bwn_phy_lp_switch_channel(mac, 7); error = bwn_phy_lp_switch_channel(mac, 7);
if (error) if (error)
device_printf(sc->sc_dev, device_printf(sc->sc_dev,
"failed to change channel 7 (%d)\n", error); "failed to change channel 7 (%d)\n", error);
bwn_phy_lp_txpctl_init(mac); bwn_phy_lp_txpctl_init(mac);
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void void
bwn_phy_lp_task_60s(struct bwn_mac *mac) bwn_phy_lp_task_60s(struct bwn_mac *mac)
{ {
bwn_phy_lp_calib(mac); bwn_phy_lp_calib(mac);
} }
static void static int
bwn_phy_lp_readsprom(struct bwn_mac *mac) bwn_phy_lp_readsprom(struct bwn_mac *mac)
{ {
struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
struct bwn_softc *sc = mac->mac_sc; struct bwn_softc *sc = mac->mac_sc;
struct ieee80211com *ic = &sc->sc_ic; struct ieee80211com *ic = &sc->sc_ic;
#define BWN_PHY_LP_READVAR(_dev, _type, _name, _result) \
do { \
int error; \
\
error = bhnd_nvram_getvar_ ##_type((_dev), (_name), (_result)); \
if (error) { \
device_printf((_dev), "NVRAM variable %s unreadable: " \
"%d\n", (_name), error); \
return (error); \
} \
} while(0)
if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) {
plp->plp_txisoband_m = siba_sprom_get_tri2g(sc->sc_dev); BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI2G,
plp->plp_bxarch = siba_sprom_get_bxa2g(sc->sc_dev); &plp->plp_txisoband_m);
plp->plp_rxpwroffset = siba_sprom_get_rxpo2g(sc->sc_dev); BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_BXA2G,
plp->plp_rssivf = siba_sprom_get_rssismf2g(sc->sc_dev); &plp->plp_bxarch);
plp->plp_rssivc = siba_sprom_get_rssismc2g(sc->sc_dev); BWN_PHY_LP_READVAR(sc->sc_dev, int8, BHND_NVAR_RXPO2G,
plp->plp_rssigs = siba_sprom_get_rssisav2g(sc->sc_dev); &plp->plp_rxpwroffset);
return; BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMF2G,
&plp->plp_rssivf);
BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMC2G,
&plp->plp_rssivc);
BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISAV2G,
&plp->plp_rssigs);
return (0);
} }
plp->plp_txisoband_l = siba_sprom_get_tri5gl(sc->sc_dev); BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5GL,
plp->plp_txisoband_m = siba_sprom_get_tri5g(sc->sc_dev); &plp->plp_txisoband_l);
plp->plp_txisoband_h = siba_sprom_get_tri5gh(sc->sc_dev); BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5G,
plp->plp_bxarch = siba_sprom_get_bxa5g(sc->sc_dev); &plp->plp_txisoband_m);
plp->plp_rxpwroffset = siba_sprom_get_rxpo5g(sc->sc_dev); BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5GH,
plp->plp_rssivf = siba_sprom_get_rssismf5g(sc->sc_dev); &plp->plp_txisoband_h);
plp->plp_rssivc = siba_sprom_get_rssismc5g(sc->sc_dev); BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_BXA5G,
plp->plp_rssigs = siba_sprom_get_rssisav5g(sc->sc_dev); &plp->plp_bxarch);
BWN_PHY_LP_READVAR(sc->sc_dev, int8, BHND_NVAR_RXPO5G,
&plp->plp_rxpwroffset);
BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMF5G,
&plp->plp_rssivf);
BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMC5G,
&plp->plp_rssivc);
BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISAV5G,
&plp->plp_rssigs);
#undef BWN_PHY_LP_READVAR
return (0);
} }
static void static void
bwn_phy_lp_bbinit(struct bwn_mac *mac) bwn_phy_lp_bbinit(struct bwn_mac *mac)
{ {
bwn_phy_lp_tblinit(mac); bwn_phy_lp_tblinit(mac);
if (mac->mac_phy.rev >= 2) if (mac->mac_phy.rev >= 2)
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines if (mac->mac_phy.rev >= 2 && fc == 1) {
bwn_phy_lp_set_txpctlmode(mac, omode); bwn_phy_lp_set_txpctlmode(mac, omode);
BWN_PHY_SETMASK(mac, BWN_PHY_RF_PWR_OVERRIDE, 0xff00, orf); BWN_PHY_SETMASK(mac, BWN_PHY_RF_PWR_OVERRIDE, 0xff00, orf);
} }
bwn_phy_lp_set_txpctlmode(mac, mode); bwn_phy_lp_set_txpctlmode(mac, mode);
if (mac->mac_phy.rev >= 2) if (mac->mac_phy.rev >= 2)
bwn_phy_lp_digflt_restore(mac); bwn_phy_lp_digflt_restore(mac);
/* do RX IQ Calculation; assumes that noise is true. */ /* do RX IQ Calculation; assumes that noise is true. */
if (siba_get_chipid(sc->sc_dev) == 0x5354) { if (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) {
for (i = 0; i < N(bwn_rxcompco_5354); i++) { for (i = 0; i < N(bwn_rxcompco_5354); i++) {
if (bwn_rxcompco_5354[i].rc_chan == plp->plp_chan) if (bwn_rxcompco_5354[i].rc_chan == plp->plp_chan)
rc = &bwn_rxcompco_5354[i]; rc = &bwn_rxcompco_5354[i];
} }
} else if (mac->mac_phy.rev >= 2) } else if (mac->mac_phy.rev >= 2)
rc = &bwn_rxcompco_r2; rc = &bwn_rxcompco_r2;
else { else {
for (i = 0; i < N(bwn_rxcompco_r12); i++) { for (i = 0; i < N(bwn_rxcompco_r12); i++) {
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Linesbwn_phy_lp_switch_analog(struct bwn_mac *mac, int on)
BWN_PHY_SET(mac, BWN_PHY_AFE_CTL_OVR, 0x0007); BWN_PHY_SET(mac, BWN_PHY_AFE_CTL_OVR, 0x0007);
} }
static int static int
bwn_phy_lp_b2063_switch_channel(struct bwn_mac *mac, uint8_t chan) bwn_phy_lp_b2063_switch_channel(struct bwn_mac *mac, uint8_t chan)
{ {
static const struct bwn_b206x_chan *bc = NULL; static const struct bwn_b206x_chan *bc = NULL;
struct bwn_softc *sc = mac->mac_sc; struct bwn_softc *sc = mac->mac_sc;
uint32_t count, freqref, freqvco, freqxtal, val[3], timeout, timeoutref, uint32_t count, freqref, freqvco, val[3], timeout, timeoutref,
tmp[6]; tmp[6];
uint16_t old, scale, tmp16; uint16_t old, scale, tmp16;
int i, div; u_int freqxtal;
int error, i, div;
for (i = 0; i < N(bwn_b2063_chantable); i++) { for (i = 0; i < N(bwn_b2063_chantable); i++) {
if (bwn_b2063_chantable[i].bc_chan == chan) { if (bwn_b2063_chantable[i].bc_chan == chan) {
bc = &bwn_b2063_chantable[i]; bc = &bwn_b2063_chantable[i];
break; break;
} }
} }
if (bc == NULL) if (bc == NULL)
return (EINVAL); return (EINVAL);
error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal);
if (error) {
device_printf(sc->sc_dev, "failed to fetch clock frequency: %d",
error);
return (error);
}
BWN_RF_WRITE(mac, BWN_B2063_LOGEN_VCOBUF1, bc->bc_data[0]); BWN_RF_WRITE(mac, BWN_B2063_LOGEN_VCOBUF1, bc->bc_data[0]);
BWN_RF_WRITE(mac, BWN_B2063_LOGEN_MIXER2, bc->bc_data[1]); BWN_RF_WRITE(mac, BWN_B2063_LOGEN_MIXER2, bc->bc_data[1]);
BWN_RF_WRITE(mac, BWN_B2063_LOGEN_BUF2, bc->bc_data[2]); BWN_RF_WRITE(mac, BWN_B2063_LOGEN_BUF2, bc->bc_data[2]);
BWN_RF_WRITE(mac, BWN_B2063_LOGEN_RCCR1, bc->bc_data[3]); BWN_RF_WRITE(mac, BWN_B2063_LOGEN_RCCR1, bc->bc_data[3]);
BWN_RF_WRITE(mac, BWN_B2063_A_RX_1ST3, bc->bc_data[4]); BWN_RF_WRITE(mac, BWN_B2063_A_RX_1ST3, bc->bc_data[4]);
BWN_RF_WRITE(mac, BWN_B2063_A_RX_2ND1, bc->bc_data[5]); BWN_RF_WRITE(mac, BWN_B2063_A_RX_2ND1, bc->bc_data[5]);
BWN_RF_WRITE(mac, BWN_B2063_A_RX_2ND4, bc->bc_data[6]); BWN_RF_WRITE(mac, BWN_B2063_A_RX_2ND4, bc->bc_data[6]);
BWN_RF_WRITE(mac, BWN_B2063_A_RX_2ND7, bc->bc_data[7]); BWN_RF_WRITE(mac, BWN_B2063_A_RX_2ND7, bc->bc_data[7]);
BWN_RF_WRITE(mac, BWN_B2063_A_RX_PS6, bc->bc_data[8]); BWN_RF_WRITE(mac, BWN_B2063_A_RX_PS6, bc->bc_data[8]);
BWN_RF_WRITE(mac, BWN_B2063_TX_RF_CTL2, bc->bc_data[9]); BWN_RF_WRITE(mac, BWN_B2063_TX_RF_CTL2, bc->bc_data[9]);
BWN_RF_WRITE(mac, BWN_B2063_TX_RF_CTL5, bc->bc_data[10]); BWN_RF_WRITE(mac, BWN_B2063_TX_RF_CTL5, bc->bc_data[10]);
BWN_RF_WRITE(mac, BWN_B2063_PA_CTL11, bc->bc_data[11]); BWN_RF_WRITE(mac, BWN_B2063_PA_CTL11, bc->bc_data[11]);
old = BWN_RF_READ(mac, BWN_B2063_COM15); old = BWN_RF_READ(mac, BWN_B2063_COM15);
BWN_RF_SET(mac, BWN_B2063_COM15, 0x1e); BWN_RF_SET(mac, BWN_B2063_COM15, 0x1e);
freqxtal = siba_get_cc_pmufreq(sc->sc_dev) * 1000;
freqvco = bc->bc_freq << ((bc->bc_freq > 4000) ? 1 : 2); freqvco = bc->bc_freq << ((bc->bc_freq > 4000) ? 1 : 2);
freqref = freqxtal * 3; freqref = freqxtal * 3;
div = (freqxtal <= 26000000 ? 1 : 2); div = (freqxtal <= 26000000 ? 1 : 2);
timeout = ((((8 * freqxtal) / (div * 5000000)) + 1) >> 1) - 1; timeout = ((((8 * freqxtal) / (div * 5000000)) + 1) >> 1) - 1;
timeoutref = ((((8 * freqxtal) / (div * (timeout + 1))) + timeoutref = ((((8 * freqxtal) / (div * (timeout + 1))) +
999999) / 1000000) + 1; 999999) / 1000000) + 1;
BWN_RF_WRITE(mac, BWN_B2063_JTAG_VCO_CALIB3, 0x2); BWN_RF_WRITE(mac, BWN_B2063_JTAG_VCO_CALIB3, 0x2);
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
} }
static int static int
bwn_phy_lp_b2062_switch_channel(struct bwn_mac *mac, uint8_t chan) bwn_phy_lp_b2062_switch_channel(struct bwn_mac *mac, uint8_t chan)
{ {
struct bwn_softc *sc = mac->mac_sc; struct bwn_softc *sc = mac->mac_sc;
struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
const struct bwn_b206x_chan *bc = NULL; const struct bwn_b206x_chan *bc = NULL;
uint32_t freqxtal = siba_get_cc_pmufreq(sc->sc_dev) * 1000;
uint32_t tmp[9]; uint32_t tmp[9];
int i; u_int freqxtal;
int error, i;
for (i = 0; i < N(bwn_b2062_chantable); i++) { for (i = 0; i < N(bwn_b2062_chantable); i++) {
if (bwn_b2062_chantable[i].bc_chan == chan) { if (bwn_b2062_chantable[i].bc_chan == chan) {
bc = &bwn_b2062_chantable[i]; bc = &bwn_b2062_chantable[i];
break; break;
} }
} }
if (bc == NULL) if (bc == NULL)
return (EINVAL); return (EINVAL);
error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal);
if (error) {
device_printf(sc->sc_dev, "failed to fetch clock frequency: %d",
error);
return (error);
}
BWN_RF_SET(mac, BWN_B2062_S_RFPLLCTL14, 0x04); BWN_RF_SET(mac, BWN_B2062_S_RFPLLCTL14, 0x04);
BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE0, bc->bc_data[0]); BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE0, bc->bc_data[0]);
BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE2, bc->bc_data[1]); BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE2, bc->bc_data[1]);
BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE3, bc->bc_data[2]); BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE3, bc->bc_data[2]);
BWN_RF_WRITE(mac, BWN_B2062_N_TX_TUNE, bc->bc_data[3]); BWN_RF_WRITE(mac, BWN_B2062_N_TX_TUNE, bc->bc_data[3]);
BWN_RF_WRITE(mac, BWN_B2062_S_LGENG_CTL1, bc->bc_data[4]); BWN_RF_WRITE(mac, BWN_B2062_S_LGENG_CTL1, bc->bc_data[4]);
BWN_RF_WRITE(mac, BWN_B2062_N_LGENACTL5, bc->bc_data[5]); BWN_RF_WRITE(mac, BWN_B2062_N_LGENACTL5, bc->bc_data[5]);
BWN_RF_WRITE(mac, BWN_B2062_N_LGENACTL6, bc->bc_data[6]); BWN_RF_WRITE(mac, BWN_B2062_N_LGENACTL6, bc->bc_data[6]);
▲ Show 20 Lines • Show All 374 Lines • ▼ Show 20 Lines for (i = 0; i < N(v1); i++)
BWN_PHY_WRITE(mac, v1[i].reg, v1[i].value); BWN_PHY_WRITE(mac, v1[i].reg, v1[i].value);
BWN_PHY_SET(mac, BWN_PHY_ADC_COMPENSATION_CTL, 0x10); BWN_PHY_SET(mac, BWN_PHY_ADC_COMPENSATION_CTL, 0x10);
for (i = 0; i < N(v2); i++) for (i = 0; i < N(v2); i++)
BWN_PHY_SETMASK(mac, v2[i].offset, v2[i].mask, v2[i].set); BWN_PHY_SETMASK(mac, v2[i].offset, v2[i].mask, v2[i].set);
BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x4000); BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x4000);
BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x2000); BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x2000);
BWN_PHY_SET(mac, BWN_PHY_OFDM(0x10a), 0x1); BWN_PHY_SET(mac, BWN_PHY_OFDM(0x10a), 0x1);
if (siba_get_pci_revid(sc->sc_dev) >= 0x18) { if (sc->sc_board_info.board_rev >= 0x18) {
bwn_tab_write(mac, BWN_TAB_4(17, 65), 0xec); bwn_tab_write(mac, BWN_TAB_4(17, 65), 0xec);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x10a), 0xff01, 0x14); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x10a), 0xff01, 0x14);
} else { } else {
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x10a), 0xff01, 0x10); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x10a), 0xff01, 0x10);
} }
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xdf), 0xff00, 0xf4); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xdf), 0xff00, 0xf4);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xdf), 0x00ff, 0xf100); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xdf), 0x00ff, 0xf100);
BWN_PHY_WRITE(mac, BWN_PHY_CLIPTHRESH, 0x48); BWN_PHY_WRITE(mac, BWN_PHY_CLIPTHRESH, 0x48);
BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0xff00, 0x46); BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0xff00, 0x46);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xe4), 0xff00, 0x10); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xe4), 0xff00, 0x10);
BWN_PHY_SETMASK(mac, BWN_PHY_PWR_THRESH1, 0xfff0, 0x9); BWN_PHY_SETMASK(mac, BWN_PHY_PWR_THRESH1, 0xfff0, 0x9);
BWN_PHY_MASK(mac, BWN_PHY_GAINDIRECTMISMATCH, ~0xf); BWN_PHY_MASK(mac, BWN_PHY_GAINDIRECTMISMATCH, ~0xf);
BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0x00ff, 0x5500); BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0x00ff, 0x5500);
BWN_PHY_SETMASK(mac, BWN_PHY_CLIPCTRTHRESH, 0xfc1f, 0xa0); BWN_PHY_SETMASK(mac, BWN_PHY_CLIPCTRTHRESH, 0xfc1f, 0xa0);
BWN_PHY_SETMASK(mac, BWN_PHY_GAINDIRECTMISMATCH, 0xe0ff, 0x300); BWN_PHY_SETMASK(mac, BWN_PHY_GAINDIRECTMISMATCH, 0xe0ff, 0x300);
BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0x00ff, 0x2a00); BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0x00ff, 0x2a00);
if ((siba_get_chipid(sc->sc_dev) == 0x4325) && if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 &&
(siba_get_chiprev(sc->sc_dev) == 0)) { sc->sc_cid.chip_pkg == 0) {
BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x2100); BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x2100);
BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0xa); BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0xa);
} else { } else {
BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x1e00); BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x1e00);
BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0xd); BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0xd);
} }
for (i = 0; i < N(v3); i++) for (i = 0; i < N(v3); i++)
BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask, v3[i].set); BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask, v3[i].set);
if ((siba_get_chipid(sc->sc_dev) == 0x4325) && if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 &&
(siba_get_chiprev(sc->sc_dev) == 0)) { sc->sc_cid.chip_pkg == 0) {
bwn_tab_write(mac, BWN_TAB_2(0x08, 0x14), 0); bwn_tab_write(mac, BWN_TAB_2(0x08, 0x14), 0);
bwn_tab_write(mac, BWN_TAB_2(0x08, 0x12), 0x40); bwn_tab_write(mac, BWN_TAB_2(0x08, 0x12), 0x40);
} }
if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) {
BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x40); BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x40);
BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xf0ff, 0xb00); BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xf0ff, 0xb00);
BWN_PHY_SETMASK(mac, BWN_PHY_SYNCPEAKCNT, 0xfff8, 0x6); BWN_PHY_SETMASK(mac, BWN_PHY_SYNCPEAKCNT, 0xfff8, 0x6);
BWN_PHY_SETMASK(mac, BWN_PHY_MINPWR_LEVEL, 0x00ff, 0x9d00); BWN_PHY_SETMASK(mac, BWN_PHY_MINPWR_LEVEL, 0x00ff, 0x9d00);
BWN_PHY_SETMASK(mac, BWN_PHY_MINPWR_LEVEL, 0xff00, 0xa1); BWN_PHY_SETMASK(mac, BWN_PHY_MINPWR_LEVEL, 0xff00, 0xa1);
BWN_PHY_MASK(mac, BWN_PHY_IDLEAFTERPKTRXTO, 0x00ff); BWN_PHY_MASK(mac, BWN_PHY_IDLEAFTERPKTRXTO, 0x00ff);
} else } else
BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x40); BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x40);
BWN_PHY_SETMASK(mac, BWN_PHY_CRS_ED_THRESH, 0xff00, 0xb3); BWN_PHY_SETMASK(mac, BWN_PHY_CRS_ED_THRESH, 0xff00, 0xb3);
BWN_PHY_SETMASK(mac, BWN_PHY_CRS_ED_THRESH, 0x00ff, 0xad00); BWN_PHY_SETMASK(mac, BWN_PHY_CRS_ED_THRESH, 0x00ff, 0xad00);
BWN_PHY_SETMASK(mac, BWN_PHY_INPUT_PWRDB, 0xff00, plp->plp_rxpwroffset); BWN_PHY_SETMASK(mac, BWN_PHY_INPUT_PWRDB, 0xff00, plp->plp_rxpwroffset);
BWN_PHY_SET(mac, BWN_PHY_RESET_CTL, 0x44); BWN_PHY_SET(mac, BWN_PHY_RESET_CTL, 0x44);
BWN_PHY_WRITE(mac, BWN_PHY_RESET_CTL, 0x80); BWN_PHY_WRITE(mac, BWN_PHY_RESET_CTL, 0x80);
BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_0, 0xa954); BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_0, 0xa954);
BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_1, BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_1,
0x2000 | ((uint16_t)plp->plp_rssigs << 10) | 0x2000 | ((uint16_t)plp->plp_rssigs << 10) |
((uint16_t)plp->plp_rssivc << 4) | plp->plp_rssivf); ((uint16_t)plp->plp_rssivc << 4) | plp->plp_rssivf);
if ((siba_get_chipid(sc->sc_dev) == 0x4325) && if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 &&
(siba_get_chiprev(sc->sc_dev) == 0)) { sc->sc_cid.chip_pkg == 0) {
BWN_PHY_SET(mac, BWN_PHY_AFE_ADC_CTL_0, 0x1c); BWN_PHY_SET(mac, BWN_PHY_AFE_ADC_CTL_0, 0x1c);
BWN_PHY_SETMASK(mac, BWN_PHY_AFE_CTL, 0x00ff, 0x8800); BWN_PHY_SETMASK(mac, BWN_PHY_AFE_CTL, 0x00ff, 0x8800);
BWN_PHY_SETMASK(mac, BWN_PHY_AFE_ADC_CTL_1, 0xfc3c, 0x0400); BWN_PHY_SETMASK(mac, BWN_PHY_AFE_ADC_CTL_1, 0xfc3c, 0x0400);
} }
bwn_phy_lp_digflt_save(mac); bwn_phy_lp_digflt_save(mac);
} }
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines static const struct bwn_smpair v5[] = {
{ BWN_PHY_TR_LOOKUP_1, 0xc0ff, 0x0900 }, { BWN_PHY_TR_LOOKUP_1, 0xc0ff, 0x0900 },
{ BWN_PHY_TR_LOOKUP_2, 0xffc0, 0x000a }, { BWN_PHY_TR_LOOKUP_2, 0xffc0, 0x000a },
{ BWN_PHY_TR_LOOKUP_2, 0xc0ff, 0x0b00 }, { BWN_PHY_TR_LOOKUP_2, 0xc0ff, 0x0b00 },
{ BWN_PHY_TR_LOOKUP_3, 0xffc0, 0x0006 }, { BWN_PHY_TR_LOOKUP_3, 0xffc0, 0x0006 },
{ BWN_PHY_TR_LOOKUP_3, 0xc0ff, 0x0500 }, { BWN_PHY_TR_LOOKUP_3, 0xc0ff, 0x0500 },
{ BWN_PHY_TR_LOOKUP_4, 0xffc0, 0x0006 }, { BWN_PHY_TR_LOOKUP_4, 0xffc0, 0x0006 },
{ BWN_PHY_TR_LOOKUP_4, 0xc0ff, 0x0700 } { BWN_PHY_TR_LOOKUP_4, 0xc0ff, 0x0700 }
}; };
int i; int error, i;
uint16_t tmp, tmp2; uint16_t tmp, tmp2;
BWN_PHY_MASK(mac, BWN_PHY_AFE_DAC_CTL, 0xf7ff); BWN_PHY_MASK(mac, BWN_PHY_AFE_DAC_CTL, 0xf7ff);
BWN_PHY_WRITE(mac, BWN_PHY_AFE_CTL, 0); BWN_PHY_WRITE(mac, BWN_PHY_AFE_CTL, 0);
BWN_PHY_WRITE(mac, BWN_PHY_AFE_CTL_OVR, 0); BWN_PHY_WRITE(mac, BWN_PHY_AFE_CTL_OVR, 0);
BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_0, 0); BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_0, 0);
BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_2, 0); BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_2, 0);
BWN_PHY_SET(mac, BWN_PHY_AFE_DAC_CTL, 0x0004); BWN_PHY_SET(mac, BWN_PHY_AFE_DAC_CTL, 0x0004);
BWN_PHY_SETMASK(mac, BWN_PHY_OFDMSYNCTHRESH0, 0xff00, 0x0078); BWN_PHY_SETMASK(mac, BWN_PHY_OFDMSYNCTHRESH0, 0xff00, 0x0078);
BWN_PHY_SETMASK(mac, BWN_PHY_CLIPCTRTHRESH, 0x83ff, 0x5800); BWN_PHY_SETMASK(mac, BWN_PHY_CLIPCTRTHRESH, 0x83ff, 0x5800);
BWN_PHY_WRITE(mac, BWN_PHY_ADC_COMPENSATION_CTL, 0x0016); BWN_PHY_WRITE(mac, BWN_PHY_ADC_COMPENSATION_CTL, 0x0016);
BWN_PHY_SETMASK(mac, BWN_PHY_AFE_ADC_CTL_0, 0xfff8, 0x0004); BWN_PHY_SETMASK(mac, BWN_PHY_AFE_ADC_CTL_0, 0xfff8, 0x0004);
BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0x00ff, 0x5400); BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0x00ff, 0x5400);
BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0x00ff, 0x2400); BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0x00ff, 0x2400);
BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x2100); BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x2100);
BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0x0006); BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0x0006);
BWN_PHY_MASK(mac, BWN_PHY_RX_RADIO_CTL, 0xfffe); BWN_PHY_MASK(mac, BWN_PHY_RX_RADIO_CTL, 0xfffe);
for (i = 0; i < N(v1); i++) for (i = 0; i < N(v1); i++)
BWN_PHY_SETMASK(mac, v1[i].offset, v1[i].mask, v1[i].set); BWN_PHY_SETMASK(mac, v1[i].offset, v1[i].mask, v1[i].set);
BWN_PHY_SETMASK(mac, BWN_PHY_INPUT_PWRDB, BWN_PHY_SETMASK(mac, BWN_PHY_INPUT_PWRDB,
0xff00, plp->plp_rxpwroffset); 0xff00, plp->plp_rxpwroffset);
if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM) && if ((sc->sc_board_info.board_flags & BHND_BFL_FEM) &&
((IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) || ((IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) ||
(siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_LDO_PAREF))) { (sc->sc_board_info.board_flags & BHND_BFL_PAREF))) {
siba_cc_pmu_set_ldovolt(sc->sc_dev, SIBA_LDO_PAREF, 0x28); error = bhnd_pmu_set_voltage_raw(sc->sc_pmu,
siba_cc_pmu_set_ldoparef(sc->sc_dev, 1); BHND_REGULATOR_PAREF_LDO, 0x28);
if (error)
device_printf(sc->sc_dev, "failed to set PAREF LDO "
"voltage: %d\n", error);
error = bhnd_pmu_enable_regulator(sc->sc_pmu,
BHND_REGULATOR_PAREF_LDO);
if (error)
device_printf(sc->sc_dev, "failed to enable PAREF LDO "
"regulator: %d\n", error);
if (mac->mac_phy.rev == 0) if (mac->mac_phy.rev == 0)
BWN_PHY_SETMASK(mac, BWN_PHY_LP_RF_SIGNAL_LUT, BWN_PHY_SETMASK(mac, BWN_PHY_LP_RF_SIGNAL_LUT,
0xffcf, 0x0010); 0xffcf, 0x0010);
bwn_tab_write(mac, BWN_TAB_2(11, 7), 60); bwn_tab_write(mac, BWN_TAB_2(11, 7), 60);
} else { } else {
siba_cc_pmu_set_ldoparef(sc->sc_dev, 0); error = bhnd_pmu_disable_regulator(sc->sc_pmu,
BHND_REGULATOR_PAREF_LDO);
if (error)
device_printf(sc->sc_dev, "failed to disable PAREF LDO "
"regulator: %d\n", error);
BWN_PHY_SETMASK(mac, BWN_PHY_LP_RF_SIGNAL_LUT, 0xffcf, 0x0020); BWN_PHY_SETMASK(mac, BWN_PHY_LP_RF_SIGNAL_LUT, 0xffcf, 0x0020);
bwn_tab_write(mac, BWN_TAB_2(11, 7), 100); bwn_tab_write(mac, BWN_TAB_2(11, 7), 100);
} }
tmp = plp->plp_rssivf | plp->plp_rssivc << 4 | 0xa000; tmp = plp->plp_rssivf | plp->plp_rssivc << 4 | 0xa000;
BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_0, tmp); BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_0, tmp);
if (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_RSSIINV) if (sc->sc_board_info.board_flags & BHND_BFL_RSSIINV)
BWN_PHY_SETMASK(mac, BWN_PHY_AFE_RSSI_CTL_1, 0xf000, 0x0aaa); BWN_PHY_SETMASK(mac, BWN_PHY_AFE_RSSI_CTL_1, 0xf000, 0x0aaa);
else else
BWN_PHY_SETMASK(mac, BWN_PHY_AFE_RSSI_CTL_1, 0xf000, 0x02aa); BWN_PHY_SETMASK(mac, BWN_PHY_AFE_RSSI_CTL_1, 0xf000, 0x02aa);
bwn_tab_write(mac, BWN_TAB_2(11, 1), 24); bwn_tab_write(mac, BWN_TAB_2(11, 1), 24);
BWN_PHY_SETMASK(mac, BWN_PHY_RX_RADIO_CTL, BWN_PHY_SETMASK(mac, BWN_PHY_RX_RADIO_CTL,
0xfff9, (plp->plp_bxarch << 1)); 0xfff9, (plp->plp_bxarch << 1));
if (mac->mac_phy.rev == 1 && if (mac->mac_phy.rev == 1 &&
(siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_FEM_BT)) { (sc->sc_board_info.board_flags & BHND_BFL_FEM_BT)) {
for (i = 0; i < N(v2); i++) for (i = 0; i < N(v2); i++)
BWN_PHY_SETMASK(mac, v2[i].offset, v2[i].mask, BWN_PHY_SETMASK(mac, v2[i].offset, v2[i].mask,
v2[i].set); v2[i].set);
} else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) || } else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ||
(siba_get_pci_subdevice(sc->sc_dev) == 0x048a) || (sc->sc_board_info.board_type == 0x048a) ||
((mac->mac_phy.rev == 0) && ((mac->mac_phy.rev == 0) &&
(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM))) { (sc->sc_board_info.board_flags & BHND_BFL_FEM))) {
for (i = 0; i < N(v3); i++) for (i = 0; i < N(v3); i++)
BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask, BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask,
v3[i].set); v3[i].set);
} else if (mac->mac_phy.rev == 1 || } else if (mac->mac_phy.rev == 1 ||
(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM)) { (sc->sc_board_info.board_flags & BHND_BFL_FEM)) {
for (i = 0; i < N(v4); i++) for (i = 0; i < N(v4); i++)
BWN_PHY_SETMASK(mac, v4[i].offset, v4[i].mask, BWN_PHY_SETMASK(mac, v4[i].offset, v4[i].mask,
v4[i].set); v4[i].set);
} else { } else {
for (i = 0; i < N(v5); i++) for (i = 0; i < N(v5); i++)
BWN_PHY_SETMASK(mac, v5[i].offset, v5[i].mask, BWN_PHY_SETMASK(mac, v5[i].offset, v5[i].mask,
v5[i].set); v5[i].set);
} }
if (mac->mac_phy.rev == 1 && if (mac->mac_phy.rev == 1 &&
(siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_LDO_PAREF)) { (sc->sc_board_info.board_flags & BHND_BFL_PAREF)) {
BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_5, BWN_PHY_TR_LOOKUP_1); BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_5, BWN_PHY_TR_LOOKUP_1);
BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_6, BWN_PHY_TR_LOOKUP_2); BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_6, BWN_PHY_TR_LOOKUP_2);
BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_7, BWN_PHY_TR_LOOKUP_3); BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_7, BWN_PHY_TR_LOOKUP_3);
BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_8, BWN_PHY_TR_LOOKUP_4); BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_8, BWN_PHY_TR_LOOKUP_4);
} }
if ((siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_FEM_BT) && if ((sc->sc_board_info.board_flags & BHND_BFL_FEM_BT) &&
(siba_get_chipid(sc->sc_dev) == 0x5354) && (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) &&
(siba_get_chippkg(sc->sc_dev) == SIBA_CHIPPACK_BCM4712S)) { (sc->sc_cid.chip_pkg == BHND_PKGID_BCM4712SMALL)) {
BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x0006); BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x0006);
BWN_PHY_WRITE(mac, BWN_PHY_GPIO_SELECT, 0x0005); BWN_PHY_WRITE(mac, BWN_PHY_GPIO_SELECT, 0x0005);
BWN_PHY_WRITE(mac, BWN_PHY_GPIO_OUTEN, 0xffff); BWN_PHY_WRITE(mac, BWN_PHY_GPIO_OUTEN, 0xffff);
bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_PR45960W); bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_PR45960W);
} }
if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) {
BWN_PHY_SET(mac, BWN_PHY_LP_PHY_CTL, 0x8000); BWN_PHY_SET(mac, BWN_PHY_LP_PHY_CTL, 0x8000);
BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x0040); BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x0040);
Show All 23 Linesbwn_phy_lp_bbinit_r01(struct bwn_mac *mac)
} }
} }
struct bwn_b2062_freq { struct bwn_b2062_freq {
uint16_t freq; uint16_t freq;
uint8_t value[6]; uint8_t value[6];
}; };
static void static int
bwn_phy_lp_b2062_init(struct bwn_mac *mac) bwn_phy_lp_b2062_init(struct bwn_mac *mac)
{ {
#define CALC_CTL7(freq, div) \ #define CALC_CTL7(freq, div) \
(((800000000 * (div) + (freq)) / (2 * (freq)) - 8) & 0xff) (((800000000 * (div) + (freq)) / (2 * (freq)) - 8) & 0xff)
#define CALC_CTL18(freq, div) \ #define CALC_CTL18(freq, div) \
((((100 * (freq) + 16000000 * (div)) / (32000000 * (div))) - 1) & 0xff) ((((100 * (freq) + 16000000 * (div)) / (32000000 * (div))) - 1) & 0xff)
#define CALC_CTL19(freq, div) \ #define CALC_CTL19(freq, div) \
((((2 * (freq) + 1000000 * (div)) / (2000000 * (div))) - 1) & 0xff) ((((2 * (freq) + 1000000 * (div)) / (2000000 * (div))) - 1) & 0xff)
Show All 14 Lines static const struct bwn_wpair v1[] = {
{ BWN_B2062_N_TXCTL5, 0 }, { BWN_B2062_N_TXCTL5, 0 },
{ BWN_B2062_N_TXCTL6, 0 }, { BWN_B2062_N_TXCTL6, 0 },
{ BWN_B2062_N_PDNCTL0, 0x40 }, { BWN_B2062_N_PDNCTL0, 0x40 },
{ BWN_B2062_N_PDNCTL0, 0 }, { BWN_B2062_N_PDNCTL0, 0 },
{ BWN_B2062_N_CALIB_TS, 0x10 }, { BWN_B2062_N_CALIB_TS, 0x10 },
{ BWN_B2062_N_CALIB_TS, 0 } { BWN_B2062_N_CALIB_TS, 0 }
}; };
const struct bwn_b2062_freq *f = NULL; const struct bwn_b2062_freq *f = NULL;
uint32_t xtalfreq, ref; uint32_t ref;
u_int xtalfreq;
unsigned int i; unsigned int i;
int error;
error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &xtalfreq);
if (error) {
device_printf(sc->sc_dev, "failed to fetch clock frequency: %d",
error);
return (error);
}
bwn_phy_lp_b2062_tblinit(mac); bwn_phy_lp_b2062_tblinit(mac);
for (i = 0; i < N(v1); i++) for (i = 0; i < N(v1); i++)
BWN_RF_WRITE(mac, v1[i].reg, v1[i].value); BWN_RF_WRITE(mac, v1[i].reg, v1[i].value);
if (mac->mac_phy.rev > 0) if (mac->mac_phy.rev > 0)
BWN_RF_WRITE(mac, BWN_B2062_S_BG_CTL1, BWN_RF_WRITE(mac, BWN_B2062_S_BG_CTL1,
(BWN_RF_READ(mac, BWN_B2062_N_COM2) >> 1) | 0x80); (BWN_RF_READ(mac, BWN_B2062_N_COM2) >> 1) | 0x80);
if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
BWN_RF_SET(mac, BWN_B2062_N_TSSI_CTL0, 0x1); BWN_RF_SET(mac, BWN_B2062_N_TSSI_CTL0, 0x1);
else else
BWN_RF_MASK(mac, BWN_B2062_N_TSSI_CTL0, ~0x1); BWN_RF_MASK(mac, BWN_B2062_N_TSSI_CTL0, ~0x1);
KASSERT(siba_get_cc_caps(sc->sc_dev) & SIBA_CC_CAPS_PMU,
("%s:%d: fail", __func__, __LINE__));
xtalfreq = siba_get_cc_pmufreq(sc->sc_dev) * 1000;
KASSERT(xtalfreq != 0, ("%s:%d: fail", __func__, __LINE__));
if (xtalfreq <= 30000000) { if (xtalfreq <= 30000000) {
plp->plp_div = 1; plp->plp_div = 1;
BWN_RF_MASK(mac, BWN_B2062_S_RFPLLCTL1, 0xfffb); BWN_RF_MASK(mac, BWN_B2062_S_RFPLLCTL1, 0xfffb);
} else { } else {
plp->plp_div = 2; plp->plp_div = 2;
BWN_RF_SET(mac, BWN_B2062_S_RFPLLCTL1, 0x4); BWN_RF_SET(mac, BWN_B2062_S_RFPLLCTL1, 0x4);
} }
Show All 15 Lines#define CALC_CTL19(freq, div) \
if (f == NULL) if (f == NULL)
f = &freqdata_tab[N(freqdata_tab) - 1]; f = &freqdata_tab[N(freqdata_tab) - 1];
BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL8, BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL8,
((uint16_t)(f->value[1]) << 4) | f->value[0]); ((uint16_t)(f->value[1]) << 4) | f->value[0]);
BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL9, BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL9,
((uint16_t)(f->value[3]) << 4) | f->value[2]); ((uint16_t)(f->value[3]) << 4) | f->value[2]);
BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL10, f->value[4]); BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL10, f->value[4]);
BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL11, f->value[5]); BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL11, f->value[5]);
return (0);
#undef CALC_CTL7 #undef CALC_CTL7
#undef CALC_CTL18 #undef CALC_CTL18
#undef CALC_CTL19 #undef CALC_CTL19
} }
static void static int
bwn_phy_lp_b2063_init(struct bwn_mac *mac) bwn_phy_lp_b2063_init(struct bwn_mac *mac)
{ {
bwn_phy_lp_b2063_tblinit(mac); bwn_phy_lp_b2063_tblinit(mac);
BWN_RF_WRITE(mac, BWN_B2063_LOGEN_SP5, 0); BWN_RF_WRITE(mac, BWN_B2063_LOGEN_SP5, 0);
BWN_RF_SET(mac, BWN_B2063_COM8, 0x38); BWN_RF_SET(mac, BWN_B2063_COM8, 0x38);
BWN_RF_WRITE(mac, BWN_B2063_REG_SP1, 0x56); BWN_RF_WRITE(mac, BWN_B2063_REG_SP1, 0x56);
BWN_RF_MASK(mac, BWN_B2063_RX_BB_CTL2, ~0x2); BWN_RF_MASK(mac, BWN_B2063_RX_BB_CTL2, ~0x2);
BWN_RF_WRITE(mac, BWN_B2063_PA_SP7, 0); BWN_RF_WRITE(mac, BWN_B2063_PA_SP7, 0);
BWN_RF_WRITE(mac, BWN_B2063_TX_RF_SP6, 0x20); BWN_RF_WRITE(mac, BWN_B2063_TX_RF_SP6, 0x20);
BWN_RF_WRITE(mac, BWN_B2063_TX_RF_SP9, 0x40); BWN_RF_WRITE(mac, BWN_B2063_TX_RF_SP9, 0x40);
if (mac->mac_phy.rev == 2) { if (mac->mac_phy.rev == 2) {
BWN_RF_WRITE(mac, BWN_B2063_PA_SP3, 0xa0); BWN_RF_WRITE(mac, BWN_B2063_PA_SP3, 0xa0);
BWN_RF_WRITE(mac, BWN_B2063_PA_SP4, 0xa0); BWN_RF_WRITE(mac, BWN_B2063_PA_SP4, 0xa0);
BWN_RF_WRITE(mac, BWN_B2063_PA_SP2, 0x18); BWN_RF_WRITE(mac, BWN_B2063_PA_SP2, 0x18);
} else { } else {
BWN_RF_WRITE(mac, BWN_B2063_PA_SP3, 0x20); BWN_RF_WRITE(mac, BWN_B2063_PA_SP3, 0x20);
BWN_RF_WRITE(mac, BWN_B2063_PA_SP2, 0x20); BWN_RF_WRITE(mac, BWN_B2063_PA_SP2, 0x20);
} }
return (0);
} }
static void static int
bwn_phy_lp_rxcal_r2(struct bwn_mac *mac) bwn_phy_lp_rxcal_r2(struct bwn_mac *mac)
{ {
struct bwn_softc *sc = mac->mac_sc; struct bwn_softc *sc = mac->mac_sc;
static const struct bwn_wpair v1[] = { static const struct bwn_wpair v1[] = {
{ BWN_B2063_RX_BB_SP8, 0x0 }, { BWN_B2063_RX_BB_SP8, 0x0 },
{ BWN_B2063_RC_CALIB_CTL1, 0x7e }, { BWN_B2063_RC_CALIB_CTL1, 0x7e },
{ BWN_B2063_RC_CALIB_CTL1, 0x7c }, { BWN_B2063_RC_CALIB_CTL1, 0x7c },
{ BWN_B2063_RC_CALIB_CTL2, 0x15 }, { BWN_B2063_RC_CALIB_CTL2, 0x15 },
{ BWN_B2063_RC_CALIB_CTL3, 0x70 }, { BWN_B2063_RC_CALIB_CTL3, 0x70 },
{ BWN_B2063_RC_CALIB_CTL4, 0x52 }, { BWN_B2063_RC_CALIB_CTL4, 0x52 },
{ BWN_B2063_RC_CALIB_CTL5, 0x1 }, { BWN_B2063_RC_CALIB_CTL5, 0x1 },
{ BWN_B2063_RC_CALIB_CTL1, 0x7d } { BWN_B2063_RC_CALIB_CTL1, 0x7d }
}; };
static const struct bwn_wpair v2[] = { static const struct bwn_wpair v2[] = {
{ BWN_B2063_TX_BB_SP3, 0x0 }, { BWN_B2063_TX_BB_SP3, 0x0 },
{ BWN_B2063_RC_CALIB_CTL1, 0x7e }, { BWN_B2063_RC_CALIB_CTL1, 0x7e },
{ BWN_B2063_RC_CALIB_CTL1, 0x7c }, { BWN_B2063_RC_CALIB_CTL1, 0x7c },
{ BWN_B2063_RC_CALIB_CTL2, 0x55 }, { BWN_B2063_RC_CALIB_CTL2, 0x55 },
{ BWN_B2063_RC_CALIB_CTL3, 0x76 } { BWN_B2063_RC_CALIB_CTL3, 0x76 }
}; };
uint32_t freqxtal = siba_get_cc_pmufreq(sc->sc_dev) * 1000; u_int freqxtal;
int i; int error, i;
uint8_t tmp; uint8_t tmp;
error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal);
if (error) {
device_printf(sc->sc_dev, "failed to fetch clock frequency: %d",
error);
return (error);
}
tmp = BWN_RF_READ(mac, BWN_B2063_RX_BB_SP8) & 0xff; tmp = BWN_RF_READ(mac, BWN_B2063_RX_BB_SP8) & 0xff;
for (i = 0; i < 2; i++) for (i = 0; i < 2; i++)
BWN_RF_WRITE(mac, v1[i].reg, v1[i].value); BWN_RF_WRITE(mac, v1[i].reg, v1[i].value);
BWN_RF_MASK(mac, BWN_B2063_PLL_SP1, 0xf7); BWN_RF_MASK(mac, BWN_B2063_PLL_SP1, 0xf7);
for (i = 2; i < N(v1); i++) for (i = 2; i < N(v1); i++)
BWN_RF_WRITE(mac, v1[i].reg, v1[i].value); BWN_RF_WRITE(mac, v1[i].reg, v1[i].value);
for (i = 0; i < 10000; i++) { for (i = 0; i < 10000; i++) {
Show All 20 Linesbwn_phy_lp_rxcal_r2(struct bwn_mac *mac)
for (i = 0; i < 10000; i++) { for (i = 0; i < 10000; i++) {
if (BWN_RF_READ(mac, BWN_B2063_RC_CALIB_CTL6) & 0x2) if (BWN_RF_READ(mac, BWN_B2063_RC_CALIB_CTL6) & 0x2)
break; break;
DELAY(1000); DELAY(1000);
} }
if (!(BWN_RF_READ(mac, BWN_B2063_RC_CALIB_CTL6) & 0x2)) if (!(BWN_RF_READ(mac, BWN_B2063_RC_CALIB_CTL6) & 0x2))
BWN_RF_WRITE(mac, BWN_B2063_TX_BB_SP3, tmp); BWN_RF_WRITE(mac, BWN_B2063_TX_BB_SP3, tmp);
BWN_RF_WRITE(mac, BWN_B2063_RC_CALIB_CTL1, 0x7e); BWN_RF_WRITE(mac, BWN_B2063_RC_CALIB_CTL1, 0x7e);
return (0);
} }
static void static int
bwn_phy_lp_rccal_r12(struct bwn_mac *mac) bwn_phy_lp_rccal_r12(struct bwn_mac *mac)
{ {
struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
struct bwn_softc *sc = mac->mac_sc; struct bwn_softc *sc = mac->mac_sc;
struct bwn_phy_lp_iq_est ie; struct bwn_phy_lp_iq_est ie;
struct bwn_txgain tx_gains; struct bwn_txgain tx_gains;
static const uint32_t pwrtbl[21] = { static const uint32_t pwrtbl[21] = {
0x10000, 0x10557, 0x10e2d, 0x113e0, 0x10f22, 0x0ff64, 0x10000, 0x10557, 0x10e2d, 0x113e0, 0x10f22, 0x0ff64,
▲ Show 20 Lines • Show All 99 Lines • ▼ Show 20 Linesdone:
BWN_PHY_WRITE(mac, BWN_PHY_LP_PHY_CTL, save[6]); BWN_PHY_WRITE(mac, BWN_PHY_LP_PHY_CTL, save[6]);
bwn_phy_lp_set_bbmult(mac, bbmult); bwn_phy_lp_set_bbmult(mac, bbmult);
if (txo) if (txo)
bwn_phy_lp_set_txgain(mac, &tx_gains); bwn_phy_lp_set_txgain(mac, &tx_gains);
bwn_phy_lp_set_txpctlmode(mac, txpctlmode); bwn_phy_lp_set_txpctlmode(mac, txpctlmode);
if (plp->plp_rccap) if (plp->plp_rccap)
bwn_phy_lp_set_rccap(mac); bwn_phy_lp_set_rccap(mac);
return (0);
} }
static void static void
bwn_phy_lp_set_rccap(struct bwn_mac *mac) bwn_phy_lp_set_rccap(struct bwn_mac *mac)
{ {
struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
uint8_t rc_cap = (plp->plp_rccap & 0x1f) >> 1; uint8_t rc_cap = (plp->plp_rccap & 0x1f) >> 1;
Show All 29 Lines
static void static void
bwn_phy_lp_b2062_reset_pllbias(struct bwn_mac *mac) bwn_phy_lp_b2062_reset_pllbias(struct bwn_mac *mac)
{ {
struct bwn_softc *sc = mac->mac_sc; struct bwn_softc *sc = mac->mac_sc;
BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 0xff); BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 0xff);
DELAY(20); DELAY(20);
if (siba_get_chipid(sc->sc_dev) == 0x5354) { if (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) {
BWN_RF_WRITE(mac, BWN_B2062_N_COM1, 4); BWN_RF_WRITE(mac, BWN_B2062_N_COM1, 4);
BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 4); BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 4);
} else { } else {
BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 0); BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 0);
} }
DELAY(5); DELAY(5);
} }
▲ Show 20 Lines • Show All 842 Lines • ▼ Show 20 Linesbwn_phy_lp_tblinit_r2(struct bwn_mac *mac)
bwn_tab_write_multi(mac, BWN_TAB_2(18, 0), N(gain), gain); bwn_tab_write_multi(mac, BWN_TAB_2(18, 0), N(gain), gain);
bwn_tab_write_multi(mac, BWN_TAB_1(6, 0), N(bwn_tab_pllfrac_tbl), bwn_tab_write_multi(mac, BWN_TAB_1(6, 0), N(bwn_tab_pllfrac_tbl),
bwn_tab_pllfrac_tbl); bwn_tab_pllfrac_tbl);
bwn_tab_write_multi(mac, BWN_TAB_2(0, 0), N(bwn_tabl_iqlocal_tbl), bwn_tab_write_multi(mac, BWN_TAB_2(0, 0), N(bwn_tabl_iqlocal_tbl),
bwn_tabl_iqlocal_tbl); bwn_tabl_iqlocal_tbl);
bwn_tab_write_multi(mac, BWN_TAB_4(9, 0), N(papdeps), papdeps); bwn_tab_write_multi(mac, BWN_TAB_4(9, 0), N(papdeps), papdeps);
bwn_tab_write_multi(mac, BWN_TAB_4(10, 0), N(papdmult), papdmult); bwn_tab_write_multi(mac, BWN_TAB_4(10, 0), N(papdmult), papdmult);
if ((siba_get_chipid(sc->sc_dev) == 0x4325) && if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 &&
(siba_get_chiprev(sc->sc_dev) == 0)) { sc->sc_cid.chip_pkg == 0) {
bwn_tab_write_multi(mac, BWN_TAB_4(13, 0), N(gainidx_a0), bwn_tab_write_multi(mac, BWN_TAB_4(13, 0), N(gainidx_a0),
gainidx_a0); gainidx_a0);
bwn_tab_write_multi(mac, BWN_TAB_2(14, 0), N(auxgainidx_a0), bwn_tab_write_multi(mac, BWN_TAB_2(14, 0), N(auxgainidx_a0),
auxgainidx_a0); auxgainidx_a0);
bwn_tab_write_multi(mac, BWN_TAB_4(17, 0), N(gainval_a0), bwn_tab_write_multi(mac, BWN_TAB_4(17, 0), N(gainval_a0),
gainval_a0); gainval_a0);
bwn_tab_write_multi(mac, BWN_TAB_2(18, 0), N(gain_a0), gain_a0); bwn_tab_write_multi(mac, BWN_TAB_2(18, 0), N(gain_a0), gain_a0);
} }
▲ Show 20 Lines • Show All 600 Lines • ▼ Show 20 Lines static struct bwn_txgain_entry txgain_5ghz_r1[] = {
{ 7, 11, 7, 0, 62 }, { 7, 11, 7, 0, 61 }, { 7, 11, 7, 0, 62 }, { 7, 11, 7, 0, 61 },
{ 7, 11, 7, 0, 59 }, { 7, 11, 7, 0, 57 }, { 7, 11, 7, 0, 59 }, { 7, 11, 7, 0, 57 },
{ 7, 11, 6, 0, 69 }, { 7, 11, 6, 0, 67 }, { 7, 11, 6, 0, 69 }, { 7, 11, 6, 0, 67 },
{ 7, 11, 6, 0, 65 }, { 7, 11, 6, 0, 63 }, { 7, 11, 6, 0, 65 }, { 7, 11, 6, 0, 63 },
{ 7, 11, 6, 0, 62 }, { 7, 11, 6, 0, 60 } { 7, 11, 6, 0, 62 }, { 7, 11, 6, 0, 60 }
}; };
if (mac->mac_phy.rev != 0 && mac->mac_phy.rev != 1) { if (mac->mac_phy.rev != 0 && mac->mac_phy.rev != 1) {
if (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_NOPA) if (sc->sc_board_info.board_flags & BHND_BFL_NOPA)
bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r2); bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r2);
else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, bwn_phy_lp_gaintbl_write_multi(mac, 0, 128,
txgain_2ghz_r2); txgain_2ghz_r2);
else else
bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, bwn_phy_lp_gaintbl_write_multi(mac, 0, 128,
txgain_5ghz_r2); txgain_5ghz_r2);
return; return;
} }
if (mac->mac_phy.rev == 0) { if (mac->mac_phy.rev == 0) {
if ((siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_NOPA) || if ((sc->sc_board_info.board_flags & BHND_BFL_NOPA) ||
(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_HGPA)) (sc->sc_board_info.board_flags & BHND_BFL_HGPA))
bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r0); bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r0);
else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, bwn_phy_lp_gaintbl_write_multi(mac, 0, 128,
txgain_2ghz_r0); txgain_2ghz_r0);
else else
bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, bwn_phy_lp_gaintbl_write_multi(mac, 0, 128,
txgain_5ghz_r0); txgain_5ghz_r0);
return; return;
} }
if ((siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_NOPA) || if ((sc->sc_board_info.board_flags & BHND_BFL_NOPA) ||
(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_HGPA)) (sc->sc_board_info.board_flags & BHND_BFL_HGPA))
bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r1); bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r1);
else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_2ghz_r1); bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_2ghz_r1);
else else
bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_5ghz_r1); bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_5ghz_r1);
} }
static void static void
▲ Show 20 Lines • Show All 271 Lines • Show Last 20 Lines