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sys/amd64/amd64/trap.c
Show First 20 Lines • Show All 696 Lines • ▼ Show 20 Lines | trap_pfault(struct trapframe *frame, int usermode) | ||||
* If the trap was caused by errant bits in the PTE then panic. | * If the trap was caused by errant bits in the PTE then panic. | ||||
*/ | */ | ||||
if (frame->tf_err & PGEX_RSV) { | if (frame->tf_err & PGEX_RSV) { | ||||
trap_fatal(frame, eva); | trap_fatal(frame, eva); | ||||
return (-1); | return (-1); | ||||
} | } | ||||
/* | /* | ||||
* If nx protection of the usermode portion of kernel page | |||||
* tables caused trap, panic. | |||||
*/ | |||||
if (pti && usermode && pg_nx != 0 && (frame->tf_err & (PGEX_P | PGEX_W | | |||||
PGEX_U | PGEX_I)) == (PGEX_P | PGEX_U | PGEX_I) && | |||||
(curpcb->pcb_saved_ucr3 & ~(PMAP_PCID_OVERMAX - 1))== | |||||
(PCPU_GET(curpmap)->pm_cr3 & ~(PMAP_PCID_OVERMAX - 1))) | |||||
panic("PTI: pid %d comm %s tf_err %#lx\n", p->p_pid, | |||||
p->p_comm, frame->tf_err); | |||||
/* | |||||
* PGEX_I is defined only if the execute disable bit capability is | * PGEX_I is defined only if the execute disable bit capability is | ||||
* supported and enabled. | * supported and enabled. | ||||
*/ | */ | ||||
if (frame->tf_err & PGEX_W) | if (frame->tf_err & PGEX_W) | ||||
ftype = VM_PROT_WRITE; | ftype = VM_PROT_WRITE; | ||||
else if ((frame->tf_err & PGEX_I) && pg_nx != 0) | else if ((frame->tf_err & PGEX_I) && pg_nx != 0) | ||||
ftype = VM_PROT_EXECUTE; | ftype = VM_PROT_EXECUTE; | ||||
else | else | ||||
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