Changeset View

Standalone View

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
#define CPU_ARCH_CORTEX_A9 0xC09		#define CPU_ARCH_CORTEX_A9 0xC09
#define CPU_ARCH_CORTEX_A12 0xC0D		#define CPU_ARCH_CORTEX_A12 0xC0D
#define CPU_ARCH_CORTEX_A15 0xC0F		#define CPU_ARCH_CORTEX_A15 0xC0F
#define CPU_ARCH_CORTEX_A17 0xC11		#define CPU_ARCH_CORTEX_A17 0xC11
#define CPU_ARCH_CORTEX_A53 0xD03		#define CPU_ARCH_CORTEX_A53 0xD03
#define CPU_ARCH_CORTEX_A57 0xD07		#define CPU_ARCH_CORTEX_A57 0xD07
#define CPU_ARCH_CORTEX_A72 0xD08		#define CPU_ARCH_CORTEX_A72 0xD08
#define CPU_ARCH_CORTEX_A73 0xD09		#define CPU_ARCH_CORTEX_A73 0xD09
		#define CPU_ARCH_CORTEX_A75 0xD0A


/* QCOM */		/* QCOM */
#define CPU_ARCH_KRAIT_300 0x06F		#define CPU_ARCH_KRAIT_300 0x06F

/* MRVL */		/* MRVL */
#define CPU_ARCH_SHEEVA_581 0x581 /* PJ4/PJ4B */		#define CPU_ARCH_SHEEVA_581 0x581 /* PJ4/PJ4B */
#define CPU_ARCH_SHEEVA_584 0x584 /* PJ4B-MP/PJ4C */		#define CPU_ARCH_SHEEVA_584 0x584 /* PJ4B-MP/PJ4C */
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines	struct cpuinfo {
/* mpidr */		/* mpidr */
int mp_ext;		int mp_ext;
};		};

extern struct cpuinfo cpuinfo;		extern struct cpuinfo cpuinfo;

void cpuinfo_init(void);		void cpuinfo_init(void);
#if __ARM_ARCH >= 6		#if __ARM_ARCH >= 6
		void cpuinfo_init_bp_hardening(void);
void cpuinfo_reinit_mmu(uint32_t ttb);		void cpuinfo_reinit_mmu(uint32_t ttb);
#endif		#endif
#endif /* _MACHINE_CPUINFO_H_ */		#endif /* _MACHINE_CPUINFO_H_ */