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Differential D13885 Diff 38091 sys/dev/ixgbe/ixgbe_type.h

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sys/dev/ixgbe/ixgbe_type.h

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#define IXGBE_I2C_DATA_OE_N_EN_X550EM_a IXGBE_I2C_DATA_OE_N_EN_X550 #define IXGBE_I2C_DATA_OE_N_EN_X550EM_a IXGBE_I2C_DATA_OE_N_EN_X550
#define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN) #define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN)
#define IXGBE_I2C_BB_EN 0 #define IXGBE_I2C_BB_EN 0
#define IXGBE_I2C_BB_EN_X540 IXGBE_I2C_BB_EN #define IXGBE_I2C_BB_EN_X540 IXGBE_I2C_BB_EN
#define IXGBE_I2C_BB_EN_X550 0x00000100 #define IXGBE_I2C_BB_EN_X550 0x00000100
#define IXGBE_I2C_BB_EN_X550EM_x IXGBE_I2C_BB_EN_X550 #define IXGBE_I2C_BB_EN_X550EM_x IXGBE_I2C_BB_EN_X550
#define IXGBE_I2C_BB_EN_X550EM_a IXGBE_I2C_BB_EN_X550 #define IXGBE_I2C_BB_EN_X550EM_a IXGBE_I2C_BB_EN_X550
#define IXGBE_I2C_BB_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN) #define IXGBE_I2C_BB_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN)
#define IXGBE_I2C_CLK_OE_N_EN 0 #define IXGBE_I2C_CLK_OE_N_EN 0
#define IXGBE_I2C_CLK_OE_N_EN_X540 IXGBE_I2C_CLK_OE_N_EN #define IXGBE_I2C_CLK_OE_N_EN_X540 IXGBE_I2C_CLK_OE_N_EN
#define IXGBE_I2C_CLK_OE_N_EN_X550 0x00002000 #define IXGBE_I2C_CLK_OE_N_EN_X550 0x00002000
#define IXGBE_I2C_CLK_OE_N_EN_X550EM_x IXGBE_I2C_CLK_OE_N_EN_X550 #define IXGBE_I2C_CLK_OE_N_EN_X550EM_x IXGBE_I2C_CLK_OE_N_EN_X550
#define IXGBE_I2C_CLK_OE_N_EN_X550EM_a IXGBE_I2C_CLK_OE_N_EN_X550 #define IXGBE_I2C_CLK_OE_N_EN_X550EM_a IXGBE_I2C_CLK_OE_N_EN_X550
#define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN) #define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN)
#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500 #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
#define NVM_OROM_OFFSET 0x17
#define NVM_OROM_BLK_LOW 0x83
#define NVM_OROM_BLK_HI 0x84
#define NVM_OROM_PATCH_MASK 0xFF
#define NVM_OROM_SHIFT 8
#define NVM_VER_MASK 0x00FF /* version mask */
#define NVM_VER_SHIFT 8 /* version bit shift */
#define NVM_OEM_PROD_VER_PTR 0x1B /* OEM Product version block pointer */
#define NVM_OEM_PROD_VER_CAP_OFF 0x1 /* OEM Product version format offset */
#define NVM_OEM_PROD_VER_OFF_L 0x2 /* OEM Product version offset low */
#define NVM_OEM_PROD_VER_OFF_H 0x3 /* OEM Product version offset high */
#define NVM_OEM_PROD_VER_CAP_MASK 0xF /* OEM Product version cap mask */
#define NVM_OEM_PROD_VER_MOD_LEN 0x3 /* OEM Product version module length */
#define NVM_ETK_OFF_LOW 0x2D /* version low order word */
#define NVM_ETK_OFF_HI 0x2E /* version high order word */
#define NVM_ETK_SHIFT 16 /* high version word shift */
#define NVM_VER_INVALID 0xFFFF
#define NVM_ETK_VALID 0x8000
#define NVM_INVALID_PTR 0xFFFF
#define NVM_VER_SIZE 32 /* version sting size */
struct ixgbe_nvm_version {
u32 etk_id;
u8 nvm_major;
u16 nvm_minor;
u8 nvm_id;
bool oem_valid;
u8 oem_major;
u8 oem_minor;
u16 oem_release;
bool or_valid;
u8 or_major;
u16 or_build;
u8 or_patch;
};
/* Interrupt Registers */ /* Interrupt Registers */
#define IXGBE_EICR 0x00800 #define IXGBE_EICR 0x00800
#define IXGBE_EICS 0x00808 #define IXGBE_EICS 0x00808
#define IXGBE_EIMS 0x00880 #define IXGBE_EIMS 0x00880
#define IXGBE_EIMC 0x00888 #define IXGBE_EIMC 0x00888
#define IXGBE_EIAC 0x00810 #define IXGBE_EIAC 0x00810
#define IXGBE_EIAM 0x00890 #define IXGBE_EIAM 0x00890
#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4) #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
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#define IXGBE_PROXYS 0x05F60 /* Proxying Status Register */ #define IXGBE_PROXYS 0x05F60 /* Proxying Status Register */
#define IXGBE_PROXYFC 0x05F64 /* Proxying Filter Control Register */ #define IXGBE_PROXYFC 0x05F64 /* Proxying Filter Control Register */
#define IXGBE_VXLANCTRL 0x0000507C /* Rx filter VXLAN UDPPORT Register */ #define IXGBE_VXLANCTRL 0x0000507C /* Rx filter VXLAN UDPPORT Register */
/* masks for accessing VXLAN and GENEVE UDP ports */ /* masks for accessing VXLAN and GENEVE UDP ports */
#define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK 0x0000ffff /* VXLAN port */ #define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK 0x0000ffff /* VXLAN port */
#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK 0xffff0000 /* GENEVE port */ #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK 0xffff0000 /* GENEVE port */
#define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK 0xffffffff /* GENEVE/VXLAN */ #define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK 0xffffffff /* GENEVE/VXLAN */
#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT 16 #define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT 16
#define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */ #define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */
/* Ext Flexible Host Filter Table */ /* Ext Flexible Host Filter Table */
#define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100)) #define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100))
#define IXGBE_FHFT_EXT_X550(_n) (0x09600 + ((_n) * 0x100)) #define IXGBE_FHFT_EXT_X550(_n) (0x09600 + ((_n) * 0x100))
/* Four Flexible Filters are supported */ /* Four Flexible Filters are supported */
#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
/* Six Flexible Filters are supported */ /* Six Flexible Filters are supported */
#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6 6 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6 6
/* Eight Flexible Filters are supported */ /* Eight Flexible Filters are supported */
#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_8 8 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_8 8
#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
/* Each Flexible Filter is at most 128 (0x80) bytes in length */ /* Each Flexible Filter is at most 128 (0x80) bytes in length */
#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
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/* EEE register fields */ /* EEE register fields */
#define IXGBE_EEER_TX_LPI_EN 0x00010000 /* Enable EEE LPI TX path */ #define IXGBE_EEER_TX_LPI_EN 0x00010000 /* Enable EEE LPI TX path */
#define IXGBE_EEER_RX_LPI_EN 0x00020000 /* Enable EEE LPI RX path */ #define IXGBE_EEER_RX_LPI_EN 0x00020000 /* Enable EEE LPI RX path */
#define IXGBE_EEE_STAT_NEG 0x20000000 /* EEE support neg on link */ #define IXGBE_EEE_STAT_NEG 0x20000000 /* EEE support neg on link */
#define IXGBE_EEE_RX_LPI_STATUS 0x40000000 /* RX Link in LPI status */ #define IXGBE_EEE_RX_LPI_STATUS 0x40000000 /* RX Link in LPI status */
#define IXGBE_EEE_TX_LPI_STATUS 0x80000000 /* TX Link in LPI status */ #define IXGBE_EEE_TX_LPI_STATUS 0x80000000 /* TX Link in LPI status */
/* Security Control Registers */ /* Security Control Registers */
#define IXGBE_SECTXCTRL 0x08800 #define IXGBE_SECTXCTRL 0x08800
#define IXGBE_SECTXSTAT 0x08804 #define IXGBE_SECTXSTAT 0x08804
#define IXGBE_SECTXBUFFAF 0x08808 #define IXGBE_SECTXBUFFAF 0x08808
#define IXGBE_SECTXMINIFG 0x08810 #define IXGBE_SECTXMINIFG 0x08810
#define IXGBE_SECRXCTRL 0x08D00 #define IXGBE_SECRXCTRL 0x08D00
#define IXGBE_SECRXSTAT 0x08D04 #define IXGBE_SECRXSTAT 0x08D04
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#define IXGBE_RTTBCNACL 0x08B08 #define IXGBE_RTTBCNACL 0x08B08
#define IXGBE_RTTBCNTG 0x04A90 #define IXGBE_RTTBCNTG 0x04A90
#define IXGBE_RTTBCNIDX 0x08B0C #define IXGBE_RTTBCNIDX 0x08B0C
#define IXGBE_RTTBCNCP 0x08B10 #define IXGBE_RTTBCNCP 0x08B10
#define IXGBE_RTFRTIMER 0x08B14 #define IXGBE_RTFRTIMER 0x08B14
#define IXGBE_RTTBCNRTT 0x05150 #define IXGBE_RTTBCNRTT 0x05150
#define IXGBE_RTTBCNRD 0x0498C #define IXGBE_RTTBCNRD 0x0498C
/* FCoE DMA Context Registers */ /* FCoE DMA Context Registers */
/* FCoE Direct DMA Context */ /* FCoE Direct DMA Context */
#define IXGBE_FCDDC(_i, _j) (0x20000 + ((_i) * 0x4) + ((_j) * 0x10)) #define IXGBE_FCDDC(_i, _j) (0x20000 + ((_i) * 0x4) + ((_j) * 0x10))
#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */ #define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */ #define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */
#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */ #define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */
#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */ #define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */
#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */ #define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */
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#define BYPASS_LOG_TIME_VALID_M 0x02000000 #define BYPASS_LOG_TIME_VALID_M 0x02000000
#define BYPASS_LOG_HEAD_M 0x04000000 #define BYPASS_LOG_HEAD_M 0x04000000
#define BYPASS_LOG_CLEAR_M 0x08000000 #define BYPASS_LOG_CLEAR_M 0x08000000
#define BYPASS_LOG_EVENT_M 0xf0000000 #define BYPASS_LOG_EVENT_M 0xf0000000
#define BYPASS_LOG_ACTION_M 0x03 #define BYPASS_LOG_ACTION_M 0x03
#define BYPASS_LOG_EVENT_SHIFT 28 #define BYPASS_LOG_EVENT_SHIFT 28
#define BYPASS_LOG_CLEAR_SHIFT 24 /* bit offset */ #define BYPASS_LOG_CLEAR_SHIFT 24 /* bit offset */
#define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4)) #define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4))
#define IXGBE_FUSES0_300MHZ (1 << 5) #define IXGBE_FUSES0_300MHZ (1 << 5)
#define IXGBE_FUSES0_REV_MASK (3 << 6) #define IXGBE_FUSES0_REV_MASK (3 << 6)
#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010) #define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)
#define IXGBE_KRM_LINK_S1(P) ((P) ? 0x8200 : 0x4200) #define IXGBE_KRM_LINK_S1(P) ((P) ? 0x8200 : 0x4200)
#define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C) #define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C)
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