Differential D13885 Diff 38091 sys/dev/ixgbe/ixgbe_phy.c

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sys/dev/ixgbe/ixgbe_phy.c

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines	static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw hw, u8 byte)
if (status)		if (status)
return status;		return status;
/* ACK */		/* ACK */
return ixgbe_clock_out_i2c_bit(hw, FALSE);		return ixgbe_clock_out_i2c_bit(hw, FALSE);
}		}

/**		/**
* ixgbe_ones_comp_byte_add - Perform one's complement addition		* ixgbe_ones_comp_byte_add - Perform one's complement addition
* @add1 - addend 1		* @add1: addend 1
* @add2 - addend 2		* @add2: addend 2
*		*
* Returns one's complement 8-bit sum.		* Returns one's complement 8-bit sum.
*/		*/
static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)		static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
{		{
u16 sum = add1 + add2;		u16 sum = add1 + add2;

sum = (sum & 0xFF) + (sum >> 8);		sum = (sum & 0xFF) + (sum >> 8);
▲ Show 20 Lines • Show All 294 Lines • ▼ Show 20 Lines	s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
}		}

return FALSE;		return FALSE;
}		}

/**		/**
* ixgbe_validate_phy_addr - Determines phy address is valid		* ixgbe_validate_phy_addr - Determines phy address is valid
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
		* @phy_addr: PHY address
*		*
**/		**/
bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)		bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
{		{
u16 phy_id = 0;		u16 phy_id = 0;
bool valid = FALSE;		bool valid = FALSE;

DEBUGFUNC("ixgbe_validate_phy_addr");		DEBUGFUNC("ixgbe_validate_phy_addr");
▲ Show 20 Lines • Show All 161 Lines • ▼ Show 20 Lines	out:
return status;		return status;
}		}

/**		/**
* ixgbe_read_phy_mdi - Reads a value from a specified PHY register without		* ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
* the SWFW lock		* the SWFW lock
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @reg_addr: 32 bit address of PHY register to read		* @reg_addr: 32 bit address of PHY register to read
		* @device_type: 5 bit device type
* @phy_data: Pointer to read data from PHY register		* @phy_data: Pointer to read data from PHY register
**/		**/
s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,		s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
u16 *phy_data)		u16 *phy_data)
{		{
u32 i, data, command;		u32 i, data, command;

/* Setup and write the address cycle command */		/* Setup and write the address cycle command */
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines	s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
return IXGBE_SUCCESS;		return IXGBE_SUCCESS;
}		}

/**		/**
* ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register		* ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
* using the SWFW lock - this function is needed in most cases		* using the SWFW lock - this function is needed in most cases
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @reg_addr: 32 bit address of PHY register to read		* @reg_addr: 32 bit address of PHY register to read
		* @device_type: 5 bit device type
* @phy_data: Pointer to read data from PHY register		* @phy_data: Pointer to read data from PHY register
**/		**/
s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,		s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 *phy_data)		u32 device_type, u16 *phy_data)
{		{
s32 status;		s32 status;
u32 gssr = hw->phy.phy_semaphore_mask;		u32 gssr = hw->phy.phy_semaphore_mask;

▲ Show 20 Lines • Show All 200 Lines • ▼ Show 20 Lines	s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)

return status;		return status;
}		}

/**		/**
* ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities		* ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @speed: new link speed		* @speed: new link speed
		* @autoneg_wait_to_complete: unused
**/		**/
s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,		s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
ixgbe_link_speed speed,		ixgbe_link_speed speed,
bool autoneg_wait_to_complete)		bool autoneg_wait_to_complete)
{		{
UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);		UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);

DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");		DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines	s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,

*speed = hw->phy.speeds_supported;		*speed = hw->phy.speeds_supported;
return status;		return status;
}		}

/**		/**
* ixgbe_check_phy_link_tnx - Determine link and speed status		* ixgbe_check_phy_link_tnx - Determine link and speed status
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
		* @speed: current link speed
		* @link_up: TRUE is link is up, FALSE otherwise
*		*
* Reads the VS1 register to determine if link is up and the current speed for		* Reads the VS1 register to determine if link is up and the current speed for
* the PHY.		* the PHY.
**/		**/
s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw hw, ixgbe_link_speed speed,		s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw hw, ixgbe_link_speed speed,
bool *link_up)		bool *link_up)
{		{
s32 status = IXGBE_SUCCESS;		s32 status = IXGBE_SUCCESS;
▲ Show 20 Lines • Show All 939 Lines • ▼ Show 20 Lines	return hw->phy.ops.read_i2c_byte(hw, byte_offset,
IXGBE_I2C_EEPROM_DEV_ADDR,		IXGBE_I2C_EEPROM_DEV_ADDR,
eeprom_data);		eeprom_data);
}		}

/**		/**
* ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface		* ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @byte_offset: byte offset at address 0xA2		* @byte_offset: byte offset at address 0xA2
* @eeprom_data: value read		* @sff8472_data: value read
*		*
* Performs byte read operation to SFP module's SFF-8472 data over I2C		* Performs byte read operation to SFP module's SFF-8472 data over I2C
**/		**/
static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,		static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 *sff8472_data)		u8 *sff8472_data)
{		{
return hw->phy.ops.read_i2c_byte(hw, byte_offset,		return hw->phy.ops.read_i2c_byte(hw, byte_offset,
IXGBE_I2C_EEPROM_DEV_ADDR2,		IXGBE_I2C_EEPROM_DEV_ADDR2,
Show All 32 Lines	if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
return TRUE;		return TRUE;
return FALSE;		return FALSE;
}		}

/**		/**
* ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C		* ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @byte_offset: byte offset to read		* @byte_offset: byte offset to read
		* @dev_addr: address to read from
* @data: value read		* @data: value read
* @lock: TRUE if to take and release semaphore		* @lock: TRUE if to take and release semaphore
*		*
* Performs byte read operation to SFP module's EEPROM over I2C interface at		* Performs byte read operation to SFP module's EEPROM over I2C interface at
* a specified device address.		* a specified device address.
**/		**/
static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,		static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data, bool lock)		u8 dev_addr, u8 *data, bool lock)
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines	fail:

return status;		return status;
}		}

/**		/**
* ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C		* ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @byte_offset: byte offset to read		* @byte_offset: byte offset to read
		* @dev_addr: address to read from
* @data: value read		* @data: value read
*		*
* Performs byte read operation to SFP module's EEPROM over I2C interface at		* Performs byte read operation to SFP module's EEPROM over I2C interface at
* a specified device address.		* a specified device address.
**/		**/
s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,		s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data)		u8 dev_addr, u8 *data)
{		{
return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,		return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
data, TRUE);		data, TRUE);
}		}

/**		/**
* ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C		* ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @byte_offset: byte offset to read		* @byte_offset: byte offset to read
		* @dev_addr: address to read from
* @data: value read		* @data: value read
*		*
* Performs byte read operation to SFP module's EEPROM over I2C interface at		* Performs byte read operation to SFP module's EEPROM over I2C interface at
* a specified device address.		* a specified device address.
**/		**/
s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,		s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data)		u8 dev_addr, u8 *data)
{		{
return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,		return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
data, FALSE);		data, FALSE);
}		}

/**		/**
* ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C		* ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @byte_offset: byte offset to write		* @byte_offset: byte offset to write
		* @dev_addr: address to write to
* @data: value to write		* @data: value to write
* @lock: TRUE if to take and release semaphore		* @lock: TRUE if to take and release semaphore
*		*
* Performs byte write operation to SFP module's EEPROM over I2C interface at		* Performs byte write operation to SFP module's EEPROM over I2C interface at
* a specified device address.		* a specified device address.
**/		**/
static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,		static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 data, bool lock)		u8 dev_addr, u8 data, bool lock)
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines	fail:

return status;		return status;
}		}

/**		/**
* ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C		* ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @byte_offset: byte offset to write		* @byte_offset: byte offset to write
		* @dev_addr: address to write to
* @data: value to write		* @data: value to write
*		*
* Performs byte write operation to SFP module's EEPROM over I2C interface at		* Performs byte write operation to SFP module's EEPROM over I2C interface at
* a specified device address.		* a specified device address.
**/		**/
s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,		s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 data)		u8 dev_addr, u8 data)
{		{
return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,		return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
data, TRUE);		data, TRUE);
}		}

/**		/**
* ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C		* ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @byte_offset: byte offset to write		* @byte_offset: byte offset to write
		* @dev_addr: address to write to
* @data: value to write		* @data: value to write
*		*
* Performs byte write operation to SFP module's EEPROM over I2C interface at		* Performs byte write operation to SFP module's EEPROM over I2C interface at
* a specified device address.		* a specified device address.
**/		**/
s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,		s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 data)		u8 dev_addr, u8 data)
{		{
▲ Show 20 Lines • Show All 366 Lines • ▼ Show 20 Lines
*		*
* Returns the I2C data bit value		* Returns the I2C data bit value
* Negates the I2C data output enable on X550 hardware.		* Negates the I2C data output enable on X550 hardware.
**/		**/
static bool ixgbe_get_i2c_data(struct ixgbe_hw hw, u32 i2cctl)		static bool ixgbe_get_i2c_data(struct ixgbe_hw hw, u32 i2cctl)
{		{
u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);		u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
bool data;		bool data;
		UNREFERENCED_1PARAMETER(hw);

DEBUGFUNC("ixgbe_get_i2c_data");		DEBUGFUNC("ixgbe_get_i2c_data");

if (data_oe_bit) {		if (data_oe_bit) {
*i2cctl \|= data_oe_bit;		*i2cctl \|= data_oe_bit;
IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
IXGBE_WRITE_FLUSH(hw);		IXGBE_WRITE_FLUSH(hw);
usec_delay(IXGBE_I2C_T_FALL);		usec_delay(IXGBE_I2C_T_FALL);
▲ Show 20 Lines • Show All 108 Lines • Show Last 20 Lines