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sys/dev/ixgbe/ixgbe_dcb_82598.c
| Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Lines | s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw, | ||||
| } | } | ||||
| return IXGBE_SUCCESS; | return IXGBE_SUCCESS; | ||||
| } | } | ||||
| /** | /** | ||||
| * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter | * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter | ||||
| * @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
| * @dcb_config: pointer to ixgbe_dcb_config structure | * @refill: refill credits index by traffic class | ||||
| * @max: max credits index by traffic class | |||||
| * @tsa: transmission selection algorithm indexed by traffic class | |||||
| * | * | ||||
| * Configure Rx Data Arbiter and credits for each traffic class. | * Configure Rx Data Arbiter and credits for each traffic class. | ||||
| */ | */ | ||||
| s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill, | s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill, | ||||
| u16 *max, u8 *tsa) | u16 *max, u8 *tsa) | ||||
| { | { | ||||
| u32 reg = 0; | u32 reg = 0; | ||||
| u32 credit_refill = 0; | u32 credit_refill = 0; | ||||
| Show All 38 Lines | s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill, | ||||
| IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg); | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg); | ||||
| return IXGBE_SUCCESS; | return IXGBE_SUCCESS; | ||||
| } | } | ||||
| /** | /** | ||||
| * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter | * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter | ||||
| * @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
| * @dcb_config: pointer to ixgbe_dcb_config structure | * @refill: refill credits index by traffic class | ||||
| * @max: max credits index by traffic class | |||||
| * @bwg_id: bandwidth grouping indexed by traffic class | |||||
| * @tsa: transmission selection algorithm indexed by traffic class | |||||
| * | * | ||||
| * Configure Tx Descriptor Arbiter and credits for each traffic class. | * Configure Tx Descriptor Arbiter and credits for each traffic class. | ||||
| */ | */ | ||||
| s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, | s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, | ||||
| u16 *refill, u16 *max, u8 *bwg_id, | u16 *refill, u16 *max, u8 *bwg_id, | ||||
| u8 *tsa) | u8 *tsa) | ||||
| { | { | ||||
| u32 reg, max_credits; | u32 reg, max_credits; | ||||
| Show All 27 Lines | s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw, | ||||
| } | } | ||||
| return IXGBE_SUCCESS; | return IXGBE_SUCCESS; | ||||
| } | } | ||||
| /** | /** | ||||
| * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter | * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter | ||||
| * @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
| * @dcb_config: pointer to ixgbe_dcb_config structure | * @refill: refill credits index by traffic class | ||||
| * @max: max credits index by traffic class | |||||
| * @bwg_id: bandwidth grouping indexed by traffic class | |||||
| * @tsa: transmission selection algorithm indexed by traffic class | |||||
| * | * | ||||
| * Configure Tx Data Arbiter and credits for each traffic class. | * Configure Tx Data Arbiter and credits for each traffic class. | ||||
| */ | */ | ||||
| s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, | s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, | ||||
| u16 *refill, u16 *max, u8 *bwg_id, | u16 *refill, u16 *max, u8 *bwg_id, | ||||
| u8 *tsa) | u8 *tsa) | ||||
| { | { | ||||
| u32 reg; | u32 reg; | ||||
| Show All 28 Lines | s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw, | ||||
| IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg); | IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg); | ||||
| return IXGBE_SUCCESS; | return IXGBE_SUCCESS; | ||||
| } | } | ||||
| /** | /** | ||||
| * ixgbe_dcb_config_pfc_82598 - Config priority flow control | * ixgbe_dcb_config_pfc_82598 - Config priority flow control | ||||
| * @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
| * @dcb_config: pointer to ixgbe_dcb_config structure | * @pfc_en: enabled pfc bitmask | ||||
| * | * | ||||
| * Configure Priority Flow Control for each traffic class. | * Configure Priority Flow Control for each traffic class. | ||||
| */ | */ | ||||
| s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en) | s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en) | ||||
| { | { | ||||
| u32 fcrtl, reg; | u32 fcrtl, reg; | ||||
| u8 i; | u8 i; | ||||
| ▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines | s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw) | ||||
| } | } | ||||
| return IXGBE_SUCCESS; | return IXGBE_SUCCESS; | ||||
| } | } | ||||
| /** | /** | ||||
| * ixgbe_dcb_hw_config_82598 - Config and enable DCB | * ixgbe_dcb_hw_config_82598 - Config and enable DCB | ||||
| * @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
| * @dcb_config: pointer to ixgbe_dcb_config structure | * @link_speed: unused | ||||
| * @refill: refill credits index by traffic class | |||||
| * @max: max credits index by traffic class | |||||
| * @bwg_id: bandwidth grouping indexed by traffic class | |||||
| * @tsa: transmission selection algorithm indexed by traffic class | |||||
| * | * | ||||
| * Configure dcb settings and enable dcb mode. | * Configure dcb settings and enable dcb mode. | ||||
| */ | */ | ||||
| s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, int link_speed, | s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, int link_speed, | ||||
| u16 *refill, u16 *max, u8 *bwg_id, | u16 *refill, u16 *max, u8 *bwg_id, | ||||
| u8 *tsa) | u8 *tsa) | ||||
| { | { | ||||
| UNREFERENCED_1PARAMETER(link_speed); | UNREFERENCED_1PARAMETER(link_speed); | ||||
| Show All 11 Lines | |||||