Differential D13885 Diff 38091 sys/dev/ixgbe/ixgbe_common.c

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sys/dev/ixgbe/ixgbe_common.c

Show First 20 Lines • Show All 2,093 Lines • ▼ Show 20 Lines	static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
eec &= ~IXGBE_EEC_DI;		eec &= ~IXGBE_EEC_DI;
IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);		IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
IXGBE_WRITE_FLUSH(hw);		IXGBE_WRITE_FLUSH(hw);
}		}

/**		/**
* ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM		* ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
		* @count: number of bits to shift
**/		**/
static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)		static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
{		{
u32 eec;		u32 eec;
u32 i;		u32 i;
u16 data = 0;		u16 data = 0;

DEBUGFUNC("ixgbe_shift_in_eeprom_bits");		DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines	static void ixgbe_raise_eeprom_clk(struct ixgbe_hw hw, u32 eec)
IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);		IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
IXGBE_WRITE_FLUSH(hw);		IXGBE_WRITE_FLUSH(hw);
usec_delay(1);		usec_delay(1);
}		}

/**		/**
* ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.		* ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @eecd: EECD's current value		* @eec: EEC's current value
**/		**/
static void ixgbe_lower_eeprom_clk(struct ixgbe_hw hw, u32 eec)		static void ixgbe_lower_eeprom_clk(struct ixgbe_hw hw, u32 eec)
{		{
DEBUGFUNC("ixgbe_lower_eeprom_clk");		DEBUGFUNC("ixgbe_lower_eeprom_clk");

/*		/*
* Lower the clock input to the EEPROM (clearing the SK bit), then		* Lower the clock input to the EEPROM (clearing the SK bit), then
* delay		* delay
▲ Show 20 Lines • Show All 363 Lines • ▼ Show 20 Lines	s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)

return IXGBE_SUCCESS;		return IXGBE_SUCCESS;
}		}

/**		/**
* ixgbe_add_uc_addr - Adds a secondary unicast address.		* ixgbe_add_uc_addr - Adds a secondary unicast address.
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @addr: new address		* @addr: new address
		* @vmdq: VMDq "set" or "pool" index
*		*
* Adds it to unused receive address register or goes into promiscuous mode.		* Adds it to unused receive address register or goes into promiscuous mode.
**/		**/
void ixgbe_add_uc_addr(struct ixgbe_hw hw, u8 addr, u32 vmdq)		void ixgbe_add_uc_addr(struct ixgbe_hw hw, u8 addr, u32 vmdq)
{		{
u32 rar_entries = hw->mac.num_rar_entries;		u32 rar_entries = hw->mac.num_rar_entries;
u32 rar;		u32 rar;

▲ Show 20 Lines • Show All 128 Lines • ▼ Show 20 Lines	static s32 ixgbe_mta_vector(struct ixgbe_hw hw, u8 mc_addr)
/* vector can only be 12-bits or boundary will be exceeded */		/* vector can only be 12-bits or boundary will be exceeded */
vector &= 0xFFF;		vector &= 0xFFF;
return vector;		return vector;
}		}

/**		/**
* ixgbe_set_mta - Set bit-vector in multicast table		* ixgbe_set_mta - Set bit-vector in multicast table
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @hash_value: Multicast address hash value		* @mc_addr: Multicast address
*		*
* Sets the bit-vector in the multicast table.		* Sets the bit-vector in the multicast table.
**/		**/
void ixgbe_set_mta(struct ixgbe_hw hw, u8 mc_addr)		void ixgbe_set_mta(struct ixgbe_hw hw, u8 mc_addr)
{		{
u32 vector;		u32 vector;
u32 vector_bit;		u32 vector_bit;
u32 vector_reg;		u32 vector_reg;
▲ Show 20 Lines • Show All 687 Lines • ▼ Show 20 Lines	DEBUGOUT("Rx unit being enabled before security "
"path fully disabled. Continuing with init.\n");		"path fully disabled. Continuing with init.\n");

return IXGBE_SUCCESS;		return IXGBE_SUCCESS;
}		}

/**		/**
* prot_autoc_read_generic - Hides MAC differences needed for AUTOC read		* prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
		* @locked: bool to indicate whether the SW/FW lock was taken
* @reg_val: Value we read from AUTOC		* @reg_val: Value we read from AUTOC
*		*
* The default case requires no protection so just to the register read.		* The default case requires no protection so just to the register read.
*/		*/
s32 prot_autoc_read_generic(struct ixgbe_hw hw, bool locked, u32 *reg_val)		s32 prot_autoc_read_generic(struct ixgbe_hw hw, bool locked, u32 *reg_val)
{		{
*locked = FALSE;		*locked = FALSE;
*reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);		*reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
▲ Show 20 Lines • Show All 510 Lines • ▼ Show 20 Lines	s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)

return IXGBE_SUCCESS;		return IXGBE_SUCCESS;
}		}

/**		/**
* ixgbe_find_vlvf_slot - find the vlanid or the first empty slot		* ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @vlan: VLAN id to write to VLAN filter		* @vlan: VLAN id to write to VLAN filter
		* @vlvf_bypass: TRUE to find vlanid only, FALSE returns first empty slot if
		* vlanid not found
*		*
		*
* return the VLVF index where this VLAN id should be placed		* return the VLVF index where this VLAN id should be placed
*		*
**/		**/
s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)		s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
{		{
s32 regindex, first_empty_slot;		s32 regindex, first_empty_slot;
u32 bits;		u32 bits;

▲ Show 20 Lines • Show All 325 Lines • ▼ Show 20 Lines	case IXGBE_LINKS_SPEED_100_82599:
if (hw->mac.type == ixgbe_mac_X550) {		if (hw->mac.type == ixgbe_mac_X550) {
if (links_reg & IXGBE_LINKS_SPEED_NON_STD)		if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
*speed = IXGBE_LINK_SPEED_5GB_FULL;		*speed = IXGBE_LINK_SPEED_5GB_FULL;
}		}
break;		break;
case IXGBE_LINKS_SPEED_10_X550EM_A:		case IXGBE_LINKS_SPEED_10_X550EM_A:
*speed = IXGBE_LINK_SPEED_UNKNOWN;		*speed = IXGBE_LINK_SPEED_UNKNOWN;
if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T \|\|		if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T \|\|
hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) {		hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
*speed = IXGBE_LINK_SPEED_10_FULL;		*speed = IXGBE_LINK_SPEED_10_FULL;
}
break;		break;
default:		default:
*speed = IXGBE_LINK_SPEED_UNKNOWN;		*speed = IXGBE_LINK_SPEED_UNKNOWN;
}		}

return IXGBE_SUCCESS;		return IXGBE_SUCCESS;
}		}

▲ Show 20 Lines • Show All 311 Lines • ▼ Show 20 Lines
* Communicates with the manageability block. On success return IXGBE_SUCCESS		* Communicates with the manageability block. On success return IXGBE_SUCCESS
* else returns semaphore error when encountering an error acquiring		* else returns semaphore error when encountering an error acquiring
* semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.		* semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
**/		**/
s32 ixgbe_host_interface_command(struct ixgbe_hw hw, u32 buffer,		s32 ixgbe_host_interface_command(struct ixgbe_hw hw, u32 buffer,
u32 length, u32 timeout, bool return_data)		u32 length, u32 timeout, bool return_data)
{		{
u32 hdr_size = sizeof(struct ixgbe_hic_hdr);		u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
u16 dword_len;		struct ixgbe_hic_hdr resp = (struct ixgbe_hic_hdr )buffer;
u16 buf_len;		u16 buf_len;
s32 status;		s32 status;
u32 bi;		u32 bi;
		u32 dword_len;

DEBUGFUNC("ixgbe_host_interface_command");		DEBUGFUNC("ixgbe_host_interface_command");

if (length == 0 \|\| length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {		if (length == 0 \|\| length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);		DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
return IXGBE_ERR_HOST_INTERFACE_COMMAND;		return IXGBE_ERR_HOST_INTERFACE_COMMAND;
}		}

Show All 13 Lines	s32 ixgbe_host_interface_command(struct ixgbe_hw hw, u32 buffer,
dword_len = hdr_size >> 2;		dword_len = hdr_size >> 2;

/* first pull in the header so we know the buffer length */		/* first pull in the header so we know the buffer length */
for (bi = 0; bi < dword_len; bi++) {		for (bi = 0; bi < dword_len; bi++) {
buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);		buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
IXGBE_LE32_TO_CPUS(&buffer[bi]);		IXGBE_LE32_TO_CPUS(&buffer[bi]);
}		}

/* If there is any thing in data position pull it in */		/*
buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;		* If there is any thing in data position pull it in
		* Read Flash command requires reading buffer length from
		* two byes instead of one byte
		*/
		if (resp->cmd == 0x30) {
		for (; bi < dword_len + 2; bi++) {
		buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
		bi);
		IXGBE_LE32_TO_CPUS(&buffer[bi]);
		}
		buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3)
		& 0xF00) \| resp->buf_len;
		hdr_size += (2 << 2);
		} else {
		buf_len = resp->buf_len;
		}
if (!buf_len)		if (!buf_len)
goto rel_out;		goto rel_out;

if (length < buf_len + hdr_size) {		if (length < buf_len + hdr_size) {
DEBUGOUT("Buffer not large enough for reply message.\n");		DEBUGOUT("Buffer not large enough for reply message.\n");
status = IXGBE_ERR_HOST_INTERFACE_COMMAND;		status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
goto rel_out;		goto rel_out;
}		}
Show All 15 Lines

/**		/**
* ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware		* ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
* @hw: pointer to the HW structure		* @hw: pointer to the HW structure
* @maj: driver version major number		* @maj: driver version major number
* @min: driver version minor number		* @min: driver version minor number
* @build: driver version build number		* @build: driver version build number
* @sub: driver version sub build number		* @sub: driver version sub build number
		* @len: unused
		* @driver_ver: unused
*		*
* Sends driver version number to firmware through the manageability		* Sends driver version number to firmware through the manageability
* block. On success return IXGBE_SUCCESS		* block. On success return IXGBE_SUCCESS
* else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring		* else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
* semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.		* semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
**/		**/
s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,		s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
u8 build, u8 sub, u16 len,		u8 build, u8 sub, u16 len,
Show All 10 Lines	s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;		fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;		fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
fw_cmd.port_num = (u8)hw->bus.func;		fw_cmd.port_num = (u8)hw->bus.func;
fw_cmd.ver_maj = maj;		fw_cmd.ver_maj = maj;
fw_cmd.ver_min = min;		fw_cmd.ver_min = min;
fw_cmd.ver_build = build;		fw_cmd.ver_build = build;
fw_cmd.ver_sub = sub;		fw_cmd.ver_sub = sub;
fw_cmd.hdr.checksum = 0;		fw_cmd.hdr.checksum = 0;
fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
(FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
fw_cmd.pad = 0;		fw_cmd.pad = 0;
fw_cmd.pad2 = 0;		fw_cmd.pad2 = 0;
		fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
		(FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));

for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {		for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,		ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
sizeof(fw_cmd),		sizeof(fw_cmd),
IXGBE_HI_COMMAND_TIMEOUT,		IXGBE_HI_COMMAND_TIMEOUT,
TRUE);		TRUE);
if (ret_val != IXGBE_SUCCESS)		if (ret_val != IXGBE_SUCCESS)
continue;		continue;
▲ Show 20 Lines • Show All 372 Lines • ▼ Show 20 Lines	s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw hw, u32 addr, u8 value)
if (ixgbe_bypass_rw_generic(hw, cmd, &status))		if (ixgbe_bypass_rw_generic(hw, cmd, &status))
return IXGBE_ERR_INVALID_ARGUMENT;		return IXGBE_ERR_INVALID_ARGUMENT;

*value = status & BYPASS_CTL2_DATA_M;		*value = status & BYPASS_CTL2_DATA_M;

return IXGBE_SUCCESS;		return IXGBE_SUCCESS;
}		}

		/**
		* ixgbe_get_orom_version - Return option ROM from EEPROM
		*
		* @hw: pointer to hardware structure
		* @nvm_ver: pointer to output structure
		*
		* if valid option ROM version, nvm_ver->or_valid set to TRUE
		* else nvm_ver->or_valid is FALSE.
		**/
		void ixgbe_get_orom_version(struct ixgbe_hw *hw,
		struct ixgbe_nvm_version *nvm_ver)
		{
		u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl;

		nvm_ver->or_valid = FALSE;
		/* Option Rom may or may not be present. Start with pointer */
		hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset);

		/* make sure offset is valid */
		if ((offset == 0x0) \|\| (offset == NVM_INVALID_PTR))
		return;

		hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh);
		hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl);

		/* option rom exists and is valid */
		if ((eeprom_cfg_blkl \| eeprom_cfg_blkh) == 0x0 \|\|
		eeprom_cfg_blkl == NVM_VER_INVALID \|\|
		eeprom_cfg_blkh == NVM_VER_INVALID)
		return;

		nvm_ver->or_valid = TRUE;
		nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT;
		nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) \|
		(eeprom_cfg_blkh >> NVM_OROM_SHIFT);
		nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK;
		}

/**		/**
		* ixgbe_get_oem_prod_version - Return OEM Product version
		*
		* @hw: pointer to hardware structure
		* @nvm_ver: pointer to output structure
		*
		* if valid OEM product version, nvm_ver->oem_valid set to TRUE
		* else nvm_ver->oem_valid is FALSE.
		**/
		void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
		struct ixgbe_nvm_version *nvm_ver)
		{
		u16 rel_num, prod_ver, mod_len, cap, offset;

		nvm_ver->oem_valid = FALSE;
		hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset);

		/* Return is offset to OEM Product Version block is invalid */
		if (offset == 0x0 && offset == NVM_INVALID_PTR)
		return;

		/* Read product version block */
		hw->eeprom.ops.read(hw, offset, &mod_len);
		hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap);

		/* Return if OEM product version block is invalid */
		if (mod_len != NVM_OEM_PROD_VER_MOD_LEN \|\|
		(cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0)
		return;

		hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver);
		hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num);

		/* Return if version is invalid */
		if ((rel_num \| prod_ver) == 0x0 \|\|
		rel_num == NVM_VER_INVALID \|\| prod_ver == NVM_VER_INVALID)
		return;

		nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT;
		nvm_ver->oem_minor = prod_ver & NVM_VER_MASK;
		nvm_ver->oem_release = rel_num;
		nvm_ver->oem_valid = TRUE;
		}

		/**
		* ixgbe_get_etk_id - Return Etrack ID from EEPROM
		*
		* @hw: pointer to hardware structure
		* @nvm_ver: pointer to output structure
		*
		* word read errors will return 0xFFFF
		**/
		void ixgbe_get_etk_id(struct ixgbe_hw hw, struct ixgbe_nvm_version nvm_ver)
		{
		u16 etk_id_l, etk_id_h;

		if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l))
		etk_id_l = NVM_VER_INVALID;
		if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h))
		etk_id_h = NVM_VER_INVALID;

		/* The word order for the version format is determined by high order
		* word bit 15.
		*/
		if ((etk_id_h & NVM_ETK_VALID) == 0) {
		nvm_ver->etk_id = etk_id_h;
		nvm_ver->etk_id \|= (etk_id_l << NVM_ETK_SHIFT);
		} else {
		nvm_ver->etk_id = etk_id_l;
		nvm_ver->etk_id \|= (etk_id_h << NVM_ETK_SHIFT);
		}
		}


		/**
* ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg		* ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @map: pointer to u8 arr for returning map		* @map: pointer to u8 arr for returning map
*		*
* Read the rtrup2tc HW register and resolve its content into map		* Read the rtrup2tc HW register and resolve its content into map
**/		**/
void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw hw, u8 map)		void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw hw, u8 map)
{		{
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
bool ixgbe_mng_present(struct ixgbe_hw *hw)		bool ixgbe_mng_present(struct ixgbe_hw *hw)
{		{
u32 fwsm;		u32 fwsm;

if (hw->mac.type < ixgbe_mac_82599EB)		if (hw->mac.type < ixgbe_mac_82599EB)
return FALSE;		return FALSE;

fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));		fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
fwsm &= IXGBE_FWSM_MODE_MASK;
return fwsm == IXGBE_FWSM_FW_MODE_PT;		return !!(fwsm & IXGBE_FWSM_FW_MODE_PT);
}		}

/**		/**
* ixgbe_mng_enabled - Is the manageability engine enabled?		* ixgbe_mng_enabled - Is the manageability engine enabled?
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
*		*
* Returns TRUE if the manageability engine is enabled.		* Returns TRUE if the manageability engine is enabled.
**/		**/
▲ Show 20 Lines • Show All 234 Lines • Show Last 20 Lines