Differential D13885 Diff 38091 sys/dev/ixgbe/ixgbe_82599.c

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sys/dev/ixgbe/ixgbe_82599.c

Show First 20 Lines • Show All 264 Lines • ▼ Show 20 Lines	s32 prot_autoc_read_82599(struct ixgbe_hw hw, bool locked, u32 *reg_val)

*reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);		*reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
return IXGBE_SUCCESS;		return IXGBE_SUCCESS;
}		}

/**		/**
* prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write		* prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @reg_val: value to write to AUTOC		* @autoc: value to write to AUTOC
* @locked: bool to indicate whether the SW/FW lock was already taken by		* @locked: bool to indicate whether the SW/FW lock was already taken by
* previous proc_autoc_read_82599.		* previous proc_autoc_read_82599.
*		*
* This part (82599) may need to hold the SW/FW lock around all writes to		* This part (82599) may need to hold the SW/FW lock around all writes to
* AUTOC. Likewise after a write we need to do a pipeline reset.		* AUTOC. Likewise after a write we need to do a pipeline reset.
*/		*/
s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)		s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
{		{
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* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @fdirctrl: value to write to flow director control register, initially		* @fdirctrl: value to write to flow director control register, initially
* contains just the value of the Rx packet buffer allocation		* contains just the value of the Rx packet buffer allocation
* @cloud_mode: TRUE - cloud mode, FALSE - other mode		* @cloud_mode: TRUE - cloud mode, FALSE - other mode
**/		**/
s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,		s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
bool cloud_mode)		bool cloud_mode)
{		{
		UNREFERENCED_1PARAMETER(cloud_mode);
DEBUGFUNC("ixgbe_init_fdir_perfect_82599");		DEBUGFUNC("ixgbe_init_fdir_perfect_82599");

/*		/*
* Continue setup of fdirctrl register bits:		* Continue setup of fdirctrl register bits:
* Turn perfect match filtering on		* Turn perfect match filtering on
* Report hash in RSS field of Rx wb descriptor		* Report hash in RSS field of Rx wb descriptor
* Initialize the drop queue to queue 127		* Initialize the drop queue to queue 127
* Move the flexible bytes to use the ethertype - shift 6 words		* Move the flexible bytes to use the ethertype - shift 6 words
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines	do { \
else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \		else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
bucket_hash ^= hi_hash_dword >> n; \		bucket_hash ^= hi_hash_dword >> n; \
else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \		else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
sig_hash ^= hi_hash_dword << (16 - n); \		sig_hash ^= hi_hash_dword << (16 - n); \
} while (0)		} while (0)

/**		/**
* ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash		* ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
* @stream: input bitstream to compute the hash on		* @input: input bitstream to compute the hash on
		* @common: compressed common input dword
*		*
* This function is almost identical to the function above but contains		* This function is almost identical to the function above but contains
* several optimizations such as unwinding all of the loops, letting the		* several optimizations such as unwinding all of the loops, letting the
* compiler work out all of the conditional ifs since the keys are static		* compiler work out all of the conditional ifs since the keys are static
* defines, and computing two keys at once since the hashed dword stream		* defines, and computing two keys at once since the hashed dword stream
* will be the same for both keys.		* will be the same for both keys.
**/		**/
u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,		u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines	do { \
if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \		if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
bucket_hash ^= lo_hash_dword >> n; \		bucket_hash ^= lo_hash_dword >> n; \
if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \		if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
bucket_hash ^= hi_hash_dword >> n; \		bucket_hash ^= hi_hash_dword >> n; \
} while (0)		} while (0)

/**		/**
* ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash		* ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
* @atr_input: input bitstream to compute the hash on		* @input: input bitstream to compute the hash on
* @input_mask: mask for the input bitstream		* @input_mask: mask for the input bitstream
*		*
* This function serves two main purposes. First it applies the input_mask		* This function serves two main purposes. First it applies the input_mask
* to the atr_input resulting in a cleaned up atr_input data stream.		* to the atr_input resulting in a cleaned up atr_input data stream.
* Secondly it computes the hash and stores it in the bkt_hash field at		* Secondly it computes the hash and stores it in the bkt_hash field at
* the end of the input byte stream. This way it will be available for		* the end of the input byte stream. This way it will be available for
* future use without needing to recompute the hash.		* future use without needing to recompute the hash.
**/		**/
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s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,		s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
union ixgbe_atr_input *input_mask, bool cloud_mode)		union ixgbe_atr_input *input_mask, bool cloud_mode)
{		{
/* mask IPv6 since it is currently not supported */		/* mask IPv6 since it is currently not supported */
u32 fdirm = IXGBE_FDIRM_DIPv6;		u32 fdirm = IXGBE_FDIRM_DIPv6;
u32 fdirtcpm;		u32 fdirtcpm;
u32 fdirip6m;		u32 fdirip6m;
		UNREFERENCED_1PARAMETER(cloud_mode);
DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");		DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");

/*		/*
* Program the relevant mask registers. If src/dst_port or src/dst_addr		* Program the relevant mask registers. If src/dst_port or src/dst_addr
* are zero, then assume a full mask for that field. Also assume that		* are zero, then assume a full mask for that field. Also assume that
* a VLAN of 0 is unspecified, so mask that out as well. L4type		* a VLAN of 0 is unspecified, so mask that out as well. L4type
* cannot be masked out in this implementation.		* cannot be masked out in this implementation.
*		*
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s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,		s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
union ixgbe_atr_input *input,		union ixgbe_atr_input *input,
u16 soft_id, u8 queue, bool cloud_mode)		u16 soft_id, u8 queue, bool cloud_mode)
{		{
u32 fdirport, fdirvlan, fdirhash, fdircmd;		u32 fdirport, fdirvlan, fdirhash, fdircmd;
u32 addr_low, addr_high;		u32 addr_low, addr_high;
u32 cloud_type = 0;		u32 cloud_type = 0;
s32 err;		s32 err;
		UNREFERENCED_1PARAMETER(cloud_mode);

DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");		DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
if (!cloud_mode) {		if (!cloud_mode) {
/* currently IPv6 is not supported, must be programmed with 0 */		/* currently IPv6 is not supported, must be programmed with 0 */
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
input->formatted.src_ip[0]);		input->formatted.src_ip[0]);
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
input->formatted.src_ip[1]);		input->formatted.src_ip[1]);
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/**		/**
* ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter		* ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @input: input bitstream		* @input: input bitstream
* @input_mask: mask for the input bitstream		* @input_mask: mask for the input bitstream
* @soft_id: software index for the filters		* @soft_id: software index for the filters
* @queue: queue index to direct traffic to		* @queue: queue index to direct traffic to
		* @cloud_mode: unused
*		*
* Note that the caller to this function must lock before calling, since the		* Note that the caller to this function must lock before calling, since the
* hardware writes must be protected from one another.		* hardware writes must be protected from one another.
**/		**/
s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,		s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
union ixgbe_atr_input *input,		union ixgbe_atr_input *input,
union ixgbe_atr_input *input_mask,		union ixgbe_atr_input *input_mask,
u16 soft_id, u8 queue, bool cloud_mode)		u16 soft_id, u8 queue, bool cloud_mode)
{		{
s32 err = IXGBE_ERR_CONFIG;		s32 err = IXGBE_ERR_CONFIG;
		UNREFERENCED_1PARAMETER(cloud_mode);

DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");		DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");

/*		/*
* Check flow_type formatting, and bail out before we touch the hardware		* Check flow_type formatting, and bail out before we touch the hardware
* if there's a configuration issue		* if there's a configuration issue
*/		*/
switch (input->formatted.flow_type) {		switch (input->formatted.flow_type) {
▲ Show 20 Lines • Show All 493 Lines • ▼ Show 20 Lines	reset_pipeline_out:

return ret_val;		return ret_val;
}		}

/**		/**
* ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C		* ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @byte_offset: byte offset to read		* @byte_offset: byte offset to read
		* @dev_addr: address to read from
* @data: value read		* @data: value read
*		*
* Performs byte read operation to SFP module's EEPROM over I2C interface at		* Performs byte read operation to SFP module's EEPROM over I2C interface at
* a specified device address.		* a specified device address.
**/		**/
static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,		static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data)		u8 dev_addr, u8 *data)
{		{
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines	release_i2c_access:

return status;		return status;
}		}

/**		/**
* ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C		* ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @byte_offset: byte offset to write		* @byte_offset: byte offset to write
		* @dev_addr: address to read from
* @data: value to write		* @data: value to write
*		*
* Performs byte write operation to SFP module's EEPROM over I2C interface at		* Performs byte write operation to SFP module's EEPROM over I2C interface at
* a specified device address.		* a specified device address.
**/		**/
static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,		static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 data)		u8 dev_addr, u8 data)
{		{
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