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head/sys/arm/allwinner/clk/aw_pll.c
Show First 20 Lines • Show All 859 Lines • ▼ Show 20 Lines | a23_pll1_recalc(struct aw_pll_sc *sc, uint64_t *freq) | ||||
return (0); | return (0); | ||||
} | } | ||||
static int | static int | ||||
h3_pll1_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout, | h3_pll1_set_freq(struct aw_pll_sc *sc, uint64_t fin, uint64_t *fout, | ||||
int flags) | int flags) | ||||
{ | { | ||||
struct aw_pll_factor *f; | struct aw_pll_factor *f; | ||||
uint32_t val, n, k, m, p; | uint32_t val, m, p; | ||||
int i; | int i; | ||||
f = NULL; | f = NULL; | ||||
for (i = 0; i < nitems(aw_a23_pll1_factors); i++) { | for (i = 0; i < nitems(aw_a23_pll1_factors); i++) { | ||||
if (aw_a23_pll1_factors[i].freq == *fout) { | if (aw_a23_pll1_factors[i].freq == *fout) { | ||||
f = &aw_a23_pll1_factors[i]; | f = &aw_a23_pll1_factors[i]; | ||||
break; | break; | ||||
} | } | ||||
} | } | ||||
if (f == NULL) | if (f == NULL) | ||||
return (EINVAL); | return (EINVAL); | ||||
if ((flags & CLK_SET_DRYRUN) != 0) | if ((flags & CLK_SET_DRYRUN) != 0) | ||||
return (0); | return (0); | ||||
DEVICE_LOCK(sc); | DEVICE_LOCK(sc); | ||||
PLL_READ(sc, &val); | PLL_READ(sc, &val); | ||||
n = (val & A23_PLL1_FACTOR_N) >> A23_PLL1_FACTOR_N_SHIFT; | |||||
k = (val & A23_PLL1_FACTOR_K) >> A23_PLL1_FACTOR_K_SHIFT; | |||||
m = (val & A23_PLL1_FACTOR_M) >> A23_PLL1_FACTOR_M_SHIFT; | m = (val & A23_PLL1_FACTOR_M) >> A23_PLL1_FACTOR_M_SHIFT; | ||||
p = (val & A23_PLL1_FACTOR_P) >> A23_PLL1_FACTOR_P_SHIFT; | p = (val & A23_PLL1_FACTOR_P) >> A23_PLL1_FACTOR_P_SHIFT; | ||||
if (p < f->p) { | if (p < f->p) { | ||||
val &= ~A23_PLL1_FACTOR_P; | val &= ~A23_PLL1_FACTOR_P; | ||||
val |= (f->p << A23_PLL1_FACTOR_P_SHIFT); | val |= (f->p << A23_PLL1_FACTOR_P_SHIFT); | ||||
PLL_WRITE(sc, val); | PLL_WRITE(sc, val); | ||||
DELAY(2000); | DELAY(2000); | ||||
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