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sys/dev/ixgbe/ixgbe_x550.c
Show First 20 Lines • Show All 331 Lines • ▼ Show 20 Lines | if (hw->bus.lan_id) { | ||||
esdp |= IXGBE_ESDP_SDP1_DIR; | esdp |= IXGBE_ESDP_SDP1_DIR; | ||||
} | } | ||||
esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); | esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); | ||||
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); | IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); | ||||
IXGBE_WRITE_FLUSH(hw); | IXGBE_WRITE_FLUSH(hw); | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_read_phy_reg_mdi_22 - Read from a clause 22 PHY register without lock | |||||
* @hw: pointer to hardware structure | |||||
* @reg_addr: 32 bit address of PHY register to read | |||||
* @dev_type: always unused | |||||
* @phy_data: Pointer to read data from PHY register | |||||
*/ | |||||
static s32 ixgbe_read_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr, | |||||
u32 dev_type, u16 *phy_data) | |||||
{ | |||||
u32 i, data, command; | |||||
UNREFERENCED_1PARAMETER(dev_type); | |||||
/* Setup and write the read command */ | |||||
command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) | | |||||
(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | | |||||
IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_READ_AUTOINC | | |||||
IXGBE_MSCA_MDI_COMMAND; | |||||
IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); | |||||
/* Check every 10 usec to see if the access completed. | |||||
* The MDI Command bit will clear when the operation is | |||||
* complete | |||||
*/ | |||||
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { | |||||
usec_delay(10); | |||||
command = IXGBE_READ_REG(hw, IXGBE_MSCA); | |||||
if (!(command & IXGBE_MSCA_MDI_COMMAND)) | |||||
break; | |||||
} | |||||
if (command & IXGBE_MSCA_MDI_COMMAND) { | |||||
ERROR_REPORT1(IXGBE_ERROR_POLLING, | |||||
"PHY read command did not complete.\n"); | |||||
return IXGBE_ERR_PHY; | |||||
} | |||||
/* Read operation is complete. Get the data from MSRWD */ | |||||
data = IXGBE_READ_REG(hw, IXGBE_MSRWD); | |||||
data >>= IXGBE_MSRWD_READ_DATA_SHIFT; | |||||
*phy_data = (u16)data; | |||||
return IXGBE_SUCCESS; | |||||
} | |||||
/** | |||||
* ixgbe_write_phy_reg_mdi_22 - Write to a clause 22 PHY register without lock | |||||
* @hw: pointer to hardware structure | |||||
* @reg_addr: 32 bit PHY register to write | |||||
* @dev_type: always unused | |||||
* @phy_data: Data to write to the PHY register | |||||
*/ | |||||
static s32 ixgbe_write_phy_reg_mdi_22(struct ixgbe_hw *hw, u32 reg_addr, | |||||
u32 dev_type, u16 phy_data) | |||||
{ | |||||
u32 i, command; | |||||
UNREFERENCED_1PARAMETER(dev_type); | |||||
/* Put the data in the MDI single read and write data register*/ | |||||
IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); | |||||
/* Setup and write the write command */ | |||||
command = (reg_addr << IXGBE_MSCA_DEV_TYPE_SHIFT) | | |||||
(hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | | |||||
IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE | | |||||
IXGBE_MSCA_MDI_COMMAND; | |||||
IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); | |||||
/* Check every 10 usec to see if the access completed. | |||||
* The MDI Command bit will clear when the operation is | |||||
* complete | |||||
*/ | |||||
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { | |||||
usec_delay(10); | |||||
command = IXGBE_READ_REG(hw, IXGBE_MSCA); | |||||
if (!(command & IXGBE_MSCA_MDI_COMMAND)) | |||||
break; | |||||
} | |||||
if (command & IXGBE_MSCA_MDI_COMMAND) { | |||||
ERROR_REPORT1(IXGBE_ERROR_POLLING, | |||||
"PHY write cmd didn't complete\n"); | |||||
return IXGBE_ERR_PHY; | |||||
} | |||||
return IXGBE_SUCCESS; | |||||
} | |||||
/** | |||||
* ixgbe_identify_phy_x550em - Get PHY type based on device id | * ixgbe_identify_phy_x550em - Get PHY type based on device id | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* | * | ||||
* Returns error code | * Returns error code | ||||
*/ | */ | ||||
static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) | static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) | ||||
{ | { | ||||
hw->mac.ops.set_lan_id(hw); | hw->mac.ops.set_lan_id(hw); | ||||
Show All 23 Lines | static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) | ||||
case IXGBE_DEV_ID_X550EM_A_KR_L: | case IXGBE_DEV_ID_X550EM_A_KR_L: | ||||
hw->phy.type = ixgbe_phy_x550em_kr; | hw->phy.type = ixgbe_phy_x550em_kr; | ||||
break; | break; | ||||
case IXGBE_DEV_ID_X550EM_A_10G_T: | case IXGBE_DEV_ID_X550EM_A_10G_T: | ||||
case IXGBE_DEV_ID_X550EM_X_10G_T: | case IXGBE_DEV_ID_X550EM_X_10G_T: | ||||
return ixgbe_identify_phy_generic(hw); | return ixgbe_identify_phy_generic(hw); | ||||
case IXGBE_DEV_ID_X550EM_X_1G_T: | case IXGBE_DEV_ID_X550EM_X_1G_T: | ||||
hw->phy.type = ixgbe_phy_ext_1g_t; | hw->phy.type = ixgbe_phy_ext_1g_t; | ||||
hw->phy.ops.read_reg = NULL; | |||||
hw->phy.ops.write_reg = NULL; | |||||
break; | break; | ||||
case IXGBE_DEV_ID_X550EM_A_1G_T: | case IXGBE_DEV_ID_X550EM_A_1G_T: | ||||
case IXGBE_DEV_ID_X550EM_A_1G_T_L: | case IXGBE_DEV_ID_X550EM_A_1G_T_L: | ||||
hw->phy.type = ixgbe_phy_fw; | hw->phy.type = ixgbe_phy_fw; | ||||
hw->phy.ops.read_reg = NULL; | |||||
hw->phy.ops.write_reg = NULL; | |||||
if (hw->bus.lan_id) | if (hw->bus.lan_id) | ||||
hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; | hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; | ||||
else | else | ||||
hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; | hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; | ||||
break; | break; | ||||
default: | default: | ||||
break; | break; | ||||
} | } | ||||
▲ Show 20 Lines • Show All 1,278 Lines • ▼ Show 20 Lines | static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw) | ||||
} | } | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_setup_sgmii - Set up link for sgmii | * ixgbe_setup_sgmii - Set up link for sgmii | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* @speed: new link speed | |||||
* @autoneg_wait: TRUE when waiting for completion is needed | |||||
*/ | */ | ||||
static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed, | static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed, | ||||
bool autoneg_wait) | bool autoneg_wait) | ||||
{ | { | ||||
struct ixgbe_mac_info *mac = &hw->mac; | struct ixgbe_mac_info *mac = &hw->mac; | ||||
u32 lval, sval, flx_val; | u32 lval, sval, flx_val; | ||||
s32 rc; | s32 rc; | ||||
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines | static s32 ixgbe_setup_sgmii(struct ixgbe_hw *hw, ixgbe_link_speed speed, | ||||
rc = ixgbe_restart_an_internal_phy_x550em(hw); | rc = ixgbe_restart_an_internal_phy_x550em(hw); | ||||
if (rc) | if (rc) | ||||
return rc; | return rc; | ||||
return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); | return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs | * ixgbe_setup_sgmii_fw - Set up link for internal PHY SGMII auto-negotiation | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* @speed: new link speed | |||||
* @autoneg_wait: TRUE when waiting for completion is needed | |||||
*/ | */ | ||||
static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed, | static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed, | ||||
bool autoneg_wait) | bool autoneg_wait) | ||||
{ | { | ||||
struct ixgbe_mac_info *mac = &hw->mac; | struct ixgbe_mac_info *mac = &hw->mac; | ||||
u32 lval, sval, flx_val; | u32 lval, sval, flx_val; | ||||
s32 rc; | s32 rc; | ||||
▲ Show 20 Lines • Show All 526 Lines • ▼ Show 20 Lines | if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { | ||||
phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; | phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; | ||||
ixgbe_setup_mux_ctl(hw); | ixgbe_setup_mux_ctl(hw); | ||||
phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em; | phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em; | ||||
} | } | ||||
switch (hw->device_id) { | switch (hw->device_id) { | ||||
case IXGBE_DEV_ID_X550EM_A_1G_T: | case IXGBE_DEV_ID_X550EM_A_1G_T: | ||||
case IXGBE_DEV_ID_X550EM_A_1G_T_L: | case IXGBE_DEV_ID_X550EM_A_1G_T_L: | ||||
phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22; | phy->ops.read_reg_mdi = NULL; | ||||
phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22; | phy->ops.write_reg_mdi = NULL; | ||||
hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a; | hw->phy.ops.read_reg = NULL; | ||||
hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a; | hw->phy.ops.write_reg = NULL; | ||||
phy->ops.check_overtemp = ixgbe_check_overtemp_fw; | phy->ops.check_overtemp = ixgbe_check_overtemp_fw; | ||||
if (hw->bus.lan_id) | if (hw->bus.lan_id) | ||||
hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; | hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; | ||||
else | else | ||||
hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; | hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; | ||||
break; | break; | ||||
case IXGBE_DEV_ID_X550EM_A_10G_T: | case IXGBE_DEV_ID_X550EM_A_10G_T: | ||||
case IXGBE_DEV_ID_X550EM_A_SFP: | case IXGBE_DEV_ID_X550EM_A_SFP: | ||||
hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a; | hw->phy.ops.read_reg = ixgbe_read_phy_reg_x550a; | ||||
hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a; | hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a; | ||||
if (hw->bus.lan_id) | if (hw->bus.lan_id) | ||||
hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; | hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; | ||||
else | else | ||||
hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; | hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; | ||||
break; | break; | ||||
case IXGBE_DEV_ID_X550EM_X_SFP: | case IXGBE_DEV_ID_X550EM_X_SFP: | ||||
/* set up for CS4227 usage */ | /* set up for CS4227 usage */ | ||||
hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; | hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; | ||||
break; | break; | ||||
case IXGBE_DEV_ID_X550EM_X_1G_T: | |||||
phy->ops.read_reg_mdi = NULL; | |||||
phy->ops.write_reg_mdi = NULL; | |||||
default: | default: | ||||
break; | break; | ||||
} | } | ||||
/* Identify the PHY or SFP module */ | /* Identify the PHY or SFP module */ | ||||
ret_val = phy->ops.identify(hw); | ret_val = phy->ops.identify(hw); | ||||
if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED || | if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED || | ||||
ret_val == IXGBE_ERR_PHY_ADDR_INVALID) | ret_val == IXGBE_ERR_PHY_ADDR_INVALID) | ||||
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines | s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) | ||||
/* PHY ops must be identified and initialized prior to reset */ | /* PHY ops must be identified and initialized prior to reset */ | ||||
status = hw->phy.ops.init(hw); | status = hw->phy.ops.init(hw); | ||||
if (status) | if (status) | ||||
DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n", | DEBUGOUT1("Failed to initialize PHY ops, STATUS = %d\n", | ||||
status); | status); | ||||
if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) { | if (status == IXGBE_ERR_SFP_NOT_SUPPORTED || | ||||
status == IXGBE_ERR_PHY_ADDR_INVALID) { | |||||
DEBUGOUT("Returning from reset HW due to PHY init failure\n"); | DEBUGOUT("Returning from reset HW due to PHY init failure\n"); | ||||
return status; | return status; | ||||
} | } | ||||
/* start the external PHY */ | /* start the external PHY */ | ||||
if (hw->phy.type == ixgbe_phy_x550em_ext_t) { | if (hw->phy.type == ixgbe_phy_x550em_ext_t) { | ||||
status = ixgbe_init_ext_t_x550em(hw); | status = ixgbe_init_ext_t_x550em(hw); | ||||
if (status) { | if (status) { | ||||
▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines | if (ixgbe_check_reset_blocked(hw)) | ||||
return 0; | return 0; | ||||
return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); | return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP | * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* @speed: new link speed | |||||
* @autoneg_wait_to_complete: unused | |||||
* | * | ||||
* Configure the external PHY and the integrated KR PHY for SFP support. | * Configure the external PHY and the integrated KR PHY for SFP support. | ||||
**/ | **/ | ||||
s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, | s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, | ||||
ixgbe_link_speed speed, | ixgbe_link_speed speed, | ||||
bool autoneg_wait_to_complete) | bool autoneg_wait_to_complete) | ||||
{ | { | ||||
s32 ret_val; | s32 ret_val; | ||||
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines | static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed) | ||||
status = ixgbe_restart_an_internal_phy_x550em(hw); | status = ixgbe_restart_an_internal_phy_x550em(hw); | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP | * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* @speed: new link speed | |||||
* @autoneg_wait_to_complete: unused | |||||
* | * | ||||
* Configure the the integrated PHY for SFP support. | * Configure the the integrated PHY for SFP support. | ||||
**/ | **/ | ||||
s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, | s32 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, | ||||
ixgbe_link_speed speed, | ixgbe_link_speed speed, | ||||
bool autoneg_wait_to_complete) | bool autoneg_wait_to_complete) | ||||
{ | { | ||||
s32 ret_val; | s32 ret_val; | ||||
▲ Show 20 Lines • Show All 406 Lines • ▼ Show 20 Lines | s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) | ||||
buffer.hdr.req.buf_lenh = 0; | buffer.hdr.req.buf_lenh = 0; | ||||
buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; | buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; | ||||
buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; | buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; | ||||
/* convert offset from words to bytes */ | /* convert offset from words to bytes */ | ||||
buffer.address = IXGBE_CPU_TO_BE32(offset * 2); | buffer.address = IXGBE_CPU_TO_BE32(offset * 2); | ||||
/* one word */ | /* one word */ | ||||
buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); | buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); | ||||
buffer.pad2 = 0; | |||||
buffer.pad3 = 0; | |||||
status = hw->mac.ops.acquire_swfw_sync(hw, mask); | status = hw->mac.ops.acquire_swfw_sync(hw, mask); | ||||
if (status) | if (status) | ||||
return status; | return status; | ||||
status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), | status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), | ||||
IXGBE_HI_COMMAND_TIMEOUT); | IXGBE_HI_COMMAND_TIMEOUT); | ||||
if (!status) { | if (!status) { | ||||
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines | while (words) { | ||||
buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; | buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; | ||||
buffer.hdr.req.buf_lenh = 0; | buffer.hdr.req.buf_lenh = 0; | ||||
buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; | buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; | ||||
buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; | buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; | ||||
/* convert offset from words to bytes */ | /* convert offset from words to bytes */ | ||||
buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2); | buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2); | ||||
buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2); | buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2); | ||||
buffer.pad2 = 0; | |||||
buffer.pad3 = 0; | |||||
status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), | status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), | ||||
IXGBE_HI_COMMAND_TIMEOUT); | IXGBE_HI_COMMAND_TIMEOUT); | ||||
if (status) { | if (status) { | ||||
DEBUGOUT("Host interface command failed\n"); | DEBUGOUT("Host interface command failed\n"); | ||||
goto out; | goto out; | ||||
} | } | ||||
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines | |||||
} | } | ||||
/** | /** | ||||
* ixgbe_checksum_ptr_x550 - Checksum one pointer region | * ixgbe_checksum_ptr_x550 - Checksum one pointer region | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* @ptr: pointer offset in eeprom | * @ptr: pointer offset in eeprom | ||||
* @size: size of section pointed by ptr, if 0 first word will be used as size | * @size: size of section pointed by ptr, if 0 first word will be used as size | ||||
* @csum: address of checksum to update | * @csum: address of checksum to update | ||||
* @buffer: pointer to buffer containing calculated checksum | |||||
* @buffer_size: size of buffer | |||||
* | * | ||||
* Returns error status for any failure | * Returns error status for any failure | ||||
*/ | */ | ||||
static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, | static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, | ||||
u16 size, u16 *csum, u16 *buffer, | u16 size, u16 *csum, u16 *buffer, | ||||
u32 buffer_size) | u32 buffer_size) | ||||
{ | { | ||||
u16 buf[256]; | u16 buf[256]; | ||||
▲ Show 20 Lines • Show All 355 Lines • ▼ Show 20 Lines | s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) | ||||
hw->mac.ops.set_lan_id(hw); | hw->mac.ops.set_lan_id(hw); | ||||
return IXGBE_SUCCESS; | return IXGBE_SUCCESS; | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_disable_rx_x550 - Disable RX unit | * ixgbe_disable_rx_x550 - Disable RX unit | ||||
* @hw: pointer to hardware structure | |||||
* | * | ||||
* Enables the Rx DMA unit for x550 | * Enables the Rx DMA unit for x550 | ||||
**/ | **/ | ||||
void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) | void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) | ||||
{ | { | ||||
u32 rxctrl, pfdtxgswc; | u32 rxctrl, pfdtxgswc; | ||||
s32 status; | s32 status; | ||||
struct ixgbe_hic_disable_rxen fw_cmd; | struct ixgbe_hic_disable_rxen fw_cmd; | ||||
▲ Show 20 Lines • Show All 628 Lines • ▼ Show 20 Lines | static void ixgbe_release_swfw_sync_X550a(struct ixgbe_hw *hw, u32 mask) | ||||
if (hmask) | if (hmask) | ||||
ixgbe_release_swfw_sync_X540(hw, hmask); | ixgbe_release_swfw_sync_X540(hw, hmask); | ||||
} | } | ||||
/** | /** | ||||
* ixgbe_read_phy_reg_x550a - Reads specified PHY register | * ixgbe_read_phy_reg_x550a - Reads specified PHY register | ||||
* @hw: pointer to hardware structure | * @hw: pointer to hardware structure | ||||
* @reg_addr: 32 bit address of PHY register to read | * @reg_addr: 32 bit address of PHY register to read | ||||
* @device_type: 5 bit device type | |||||
* @phy_data: Pointer to read data from PHY register | * @phy_data: Pointer to read data from PHY register | ||||
* | * | ||||
* Reads a value from a specified PHY register using the SWFW lock and PHY | * Reads a value from a specified PHY register using the SWFW lock and PHY | ||||
* Token. The PHY Token is needed since the MDIO is shared between to MAC | * Token. The PHY Token is needed since the MDIO is shared between to MAC | ||||
* instances. | * instances. | ||||
**/ | **/ | ||||
s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, | s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, | ||||
u32 device_type, u16 *phy_data) | u32 device_type, u16 *phy_data) | ||||
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