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sys/amd64/amd64/cpu_switch.S
Context not available. | |||||
movq %r8,PCPU(RSP0) | movq %r8,PCPU(RSP0) | ||||
movq %r8,PCPU(CURPCB) | movq %r8,PCPU(CURPCB) | ||||
/* Update the TSS_RSP0 pointer for the next interrupt */ | /* Update the TSS_RSP0 pointer for the next interrupt */ | ||||
cmpb $0,pti(%rip) | |||||
jne 1f | |||||
movq %r8,TSS_RSP0(%rdx) | movq %r8,TSS_RSP0(%rdx) | ||||
jtl: I'm probably missing something obvious, but can you explain why this isn't needed when pti != 0? | |||||
Not Done Inline ActionsWhen PTI is enabled, inter-ring exceptions and interrupts use trampoline stack which is carved from the always mapped PCPU page, see pc_pti_stack member. It is per-cpu and is not changed on the context switch. Trap frame is copied from the trampoline stack to the thread kstack by the trampoline code. In non-PTI mode, kernel sets up the thread kstack as the interrupts stack directly. This instruction is what changes the CPU pointer to the ring 0 interrupt stack on context switch, so it must be avoided in PTI config. kib: When PTI is enabled, inter-ring exceptions and interrupts use trampoline stack which is carved… | |||||
movq %r12,PCPU(CURTHREAD) /* into next thread */ | 1: movq %r12,PCPU(CURTHREAD) /* into next thread */ | ||||
/* Test if debug registers should be restored. */ | /* Test if debug registers should be restored. */ | ||||
testl $PCB_DBREGS,PCB_FLAGS(%r8) | testl $PCB_DBREGS,PCB_FLAGS(%r8) | ||||
Context not available. | |||||
shrq $8,%rcx | shrq $8,%rcx | ||||
movl %ecx,8(%rax) | movl %ecx,8(%rax) | ||||
movb $0x89,5(%rax) /* unset busy */ | movb $0x89,5(%rax) /* unset busy */ | ||||
movl $TSSSEL,%eax | cmpb $0,pti(%rip) | ||||
je 1f | |||||
movq PCPU(PRVSPACE),%rax | |||||
addq $PC_PTI_STACK+PC_PTI_STACK_SZ*8,%rax | |||||
movq %rax,TSS_RSP0(%rdx) | |||||
1: movl $TSSSEL,%eax | |||||
ltr %ax | ltr %ax | ||||
jmp done_tss | jmp done_tss | ||||
Context not available. |
I'm probably missing something obvious, but can you explain why this isn't needed when pti != 0? Thanks in advance for educating me. :-)